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  • ipipe-arm
  • drivers
  • clk
  • samsung
  • clk-exynos4.c
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  • Marek Szyprowski's avatar
    clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle · 5dcbeca6
    Marek Szyprowski authored Sep 19, 2017
    Commit 6edfa11c ("clk: samsung: Add enable/disable operation for
    PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that
    VPLL and EPPL clocks were always enabled because the enable bit was never
    touched. Those clocks have to be enabled during suspend/resume cycle,
    because otherwise board fails to enter sleep mode. This patch enables them
    unconditionally before entering system suspend state. System restore
    function will set them to the previous state saved in the register cache
    done before that unconditional enable.
    
    Fixes: 6edfa11c
    
     ("clk: samsung: Add enable/disable operation for PLL36XX clocks")
    CC: stable@vger.kernel.org # v4.13
    Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
    Reviewed-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
    Reviewed-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
    Acked-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
    Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
    5dcbeca6

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