Commit 72cd4064 authored by Vladimir Murzin's avatar Vladimir Murzin Committed by Russell King
Browse files

ARM: 8830/1: NOMMU: Toggle only bits in EXC_RETURN we are really care of

ARMv8M introduces support for Security extension to M class, among
other things it affects exception handling, especially, encoding of

The new bits have been added:

Bit [6]	Secure or Non-secure stack
Bit [5]	Default callee register stacking
Bit [0]	Exception Secure

which conflicts with hard-coded value of EXC_RETURN:

In fact, we only care of few bits:

Bit [3]	 Mode (0 - Handler, 1 - Thread)
Bit [2]	 Stack pointer selection (0 - Main, 1 - Process)

We can toggle only those bits and left other bits as they were on
exception entry.

It is basically, what patch does - saves EXC_RETURN when we do
transition form Thread to Handler mode (it is first svc), so later
saved value is used instead of EXC_RET_THREADMODE_PROCESSSTACK.

Signed-off-by: default avatarVladimir Murzin <>
Signed-off-by: default avatarRussell King <>
parent eb7ff902
......@@ -49,7 +49,7 @@
* (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
#define EXC_RET_STACK_MASK 0x00000004
/* Cache related definitions */
......@@ -127,7 +127,8 @@
.macro v7m_exception_slow_exit ret_r0
cpsid i
ldr lr, =exc_ret
ldr lr, [lr]
@ read original r12, sp, lr, pc and xPSR
add r12, sp, #S_IP
......@@ -146,3 +146,7 @@ ENTRY(vector_table)
.long __irq_entry @ External Interrupts
.align 2
.globl exc_ret
.space 4
......@@ -139,6 +139,9 @@ __v7m_setup_cont:
cpsie i
svc #0
1: cpsid i
ldr r0, =exc_ret
str lr, [r0]
ldmia sp, {r0-r3, r12}
str r5, [r12, #11 * 4] @ restore the original SVC vector entry
mov lr, r6 @ restore LR
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