Commit a8c21a54 authored by The etnaviv authors's avatar The etnaviv authors Committed by Lucas Stach
Browse files

drm/etnaviv: add initial etnaviv DRM driver



This adds the etnaviv DRM driver and hooks it up in Makefiles
and Kconfig.
Signed-off-by: default avatarChristian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f04b205a
......@@ -266,3 +266,5 @@ source "drivers/gpu/drm/amd/amdkfd/Kconfig"
source "drivers/gpu/drm/imx/Kconfig"
source "drivers/gpu/drm/vc4/Kconfig"
source "drivers/gpu/drm/etnaviv/Kconfig"
......@@ -75,3 +75,4 @@ obj-y += i2c/
obj-y += panel/
obj-y += bridge/
obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/
obj-$(CONFIG_DRM_ETNAVIV) += etnaviv/
config DRM_ETNAVIV
tristate "ETNAVIV (DRM support for Vivante GPU IP cores)"
depends on DRM
depends on ARCH_MXC || ARCH_DOVE
select SHMEM
select TMPFS
select IOMMU_API
select IOMMU_SUPPORT
select WANT_DEV_COREDUMP
help
DRM driver for Vivante GPUs.
config DRM_ETNAVIV_REGISTER_LOGGING
bool "enable ETNAVIV register logging"
depends on DRM_ETNAVIV
help
Compile in support for logging register reads/writes in a format
that can be parsed by envytools demsm tool. If enabled, register
logging can be switched on via etnaviv.reglog=y module param.
etnaviv-y := \
etnaviv_buffer.o \
etnaviv_cmd_parser.o \
etnaviv_drv.o \
etnaviv_dump.o \
etnaviv_gem_prime.o \
etnaviv_gem_submit.o \
etnaviv_gem.o \
etnaviv_gpu.o \
etnaviv_iommu_v2.o \
etnaviv_iommu.o \
etnaviv_mmu.o
obj-$(CONFIG_DRM_ETNAVIV) += etnaviv.o
#ifndef CMDSTREAM_XML
#define CMDSTREAM_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
- cmdstream.xml ( 12589 bytes, from 2014-02-17 14:57:56)
- common.xml ( 18437 bytes, from 2015-03-25 11:27:41)
Copyright (C) 2014
*/
#define FE_OPCODE_LOAD_STATE 0x00000001
#define FE_OPCODE_END 0x00000002
#define FE_OPCODE_NOP 0x00000003
#define FE_OPCODE_DRAW_2D 0x00000004
#define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
#define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
#define FE_OPCODE_WAIT 0x00000007
#define FE_OPCODE_LINK 0x00000008
#define FE_OPCODE_STALL 0x00000009
#define FE_OPCODE_CALL 0x0000000a
#define FE_OPCODE_RETURN 0x0000000b
#define FE_OPCODE_CHIP_SELECT 0x0000000d
#define PRIMITIVE_TYPE_POINTS 0x00000001
#define PRIMITIVE_TYPE_LINES 0x00000002
#define PRIMITIVE_TYPE_LINE_STRIP 0x00000003
#define PRIMITIVE_TYPE_TRIANGLES 0x00000004
#define PRIMITIVE_TYPE_TRIANGLE_STRIP 0x00000005
#define PRIMITIVE_TYPE_TRIANGLE_FAN 0x00000006
#define PRIMITIVE_TYPE_LINE_LOOP 0x00000007
#define PRIMITIVE_TYPE_QUADS 0x00000008
#define VIV_FE_LOAD_STATE 0x00000000
#define VIV_FE_LOAD_STATE_HEADER 0x00000000
#define VIV_FE_LOAD_STATE_HEADER_OP__MASK 0xf8000000
#define VIV_FE_LOAD_STATE_HEADER_OP__SHIFT 27
#define VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE 0x08000000
#define VIV_FE_LOAD_STATE_HEADER_FIXP 0x04000000
#define VIV_FE_LOAD_STATE_HEADER_COUNT__MASK 0x03ff0000
#define VIV_FE_LOAD_STATE_HEADER_COUNT__SHIFT 16
#define VIV_FE_LOAD_STATE_HEADER_COUNT(x) (((x) << VIV_FE_LOAD_STATE_HEADER_COUNT__SHIFT) & VIV_FE_LOAD_STATE_HEADER_COUNT__MASK)
#define VIV_FE_LOAD_STATE_HEADER_OFFSET__MASK 0x0000ffff
#define VIV_FE_LOAD_STATE_HEADER_OFFSET__SHIFT 0
#define VIV_FE_LOAD_STATE_HEADER_OFFSET(x) (((x) << VIV_FE_LOAD_STATE_HEADER_OFFSET__SHIFT) & VIV_FE_LOAD_STATE_HEADER_OFFSET__MASK)
#define VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR 2
#define VIV_FE_END 0x00000000
#define VIV_FE_END_HEADER 0x00000000
#define VIV_FE_END_HEADER_EVENT_ID__MASK 0x0000001f
#define VIV_FE_END_HEADER_EVENT_ID__SHIFT 0
#define VIV_FE_END_HEADER_EVENT_ID(x) (((x) << VIV_FE_END_HEADER_EVENT_ID__SHIFT) & VIV_FE_END_HEADER_EVENT_ID__MASK)
#define VIV_FE_END_HEADER_EVENT_ENABLE 0x00000100
#define VIV_FE_END_HEADER_OP__MASK 0xf8000000
#define VIV_FE_END_HEADER_OP__SHIFT 27
#define VIV_FE_END_HEADER_OP_END 0x10000000
#define VIV_FE_NOP 0x00000000
#define VIV_FE_NOP_HEADER 0x00000000
#define VIV_FE_NOP_HEADER_OP__MASK 0xf8000000
#define VIV_FE_NOP_HEADER_OP__SHIFT 27
#define VIV_FE_NOP_HEADER_OP_NOP 0x18000000
#define VIV_FE_DRAW_2D 0x00000000
#define VIV_FE_DRAW_2D_HEADER 0x00000000
#define VIV_FE_DRAW_2D_HEADER_COUNT__MASK 0x0000ff00
#define VIV_FE_DRAW_2D_HEADER_COUNT__SHIFT 8
#define VIV_FE_DRAW_2D_HEADER_COUNT(x) (((x) << VIV_FE_DRAW_2D_HEADER_COUNT__SHIFT) & VIV_FE_DRAW_2D_HEADER_COUNT__MASK)
#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT__MASK 0x07ff0000
#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT__SHIFT 16
#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT(x) (((x) << VIV_FE_DRAW_2D_HEADER_DATA_COUNT__SHIFT) & VIV_FE_DRAW_2D_HEADER_DATA_COUNT__MASK)
#define VIV_FE_DRAW_2D_HEADER_OP__MASK 0xf8000000
#define VIV_FE_DRAW_2D_HEADER_OP__SHIFT 27
#define VIV_FE_DRAW_2D_HEADER_OP_DRAW_2D 0x20000000
#define VIV_FE_DRAW_2D_TOP_LEFT 0x00000008
#define VIV_FE_DRAW_2D_TOP_LEFT_X__MASK 0x0000ffff
#define VIV_FE_DRAW_2D_TOP_LEFT_X__SHIFT 0
#define VIV_FE_DRAW_2D_TOP_LEFT_X(x) (((x) << VIV_FE_DRAW_2D_TOP_LEFT_X__SHIFT) & VIV_FE_DRAW_2D_TOP_LEFT_X__MASK)
#define VIV_FE_DRAW_2D_TOP_LEFT_Y__MASK 0xffff0000
#define VIV_FE_DRAW_2D_TOP_LEFT_Y__SHIFT 16
#define VIV_FE_DRAW_2D_TOP_LEFT_Y(x) (((x) << VIV_FE_DRAW_2D_TOP_LEFT_Y__SHIFT) & VIV_FE_DRAW_2D_TOP_LEFT_Y__MASK)
#define VIV_FE_DRAW_2D_BOTTOM_RIGHT 0x0000000c
#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__MASK 0x0000ffff
#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__SHIFT 0
#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X(x) (((x) << VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__SHIFT) & VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__MASK)
#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__MASK 0xffff0000
#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__SHIFT 16
#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y(x) (((x) << VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__SHIFT) & VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__MASK)
#define VIV_FE_DRAW_PRIMITIVES 0x00000000
#define VIV_FE_DRAW_PRIMITIVES_HEADER 0x00000000
#define VIV_FE_DRAW_PRIMITIVES_HEADER_OP__MASK 0xf8000000
#define VIV_FE_DRAW_PRIMITIVES_HEADER_OP__SHIFT 27
#define VIV_FE_DRAW_PRIMITIVES_HEADER_OP_DRAW_PRIMITIVES 0x28000000
#define VIV_FE_DRAW_PRIMITIVES_COMMAND 0x00000004
#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__MASK 0x000000ff
#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__SHIFT 0
#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE(x) (((x) << VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__SHIFT) & VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__MASK)
#define VIV_FE_DRAW_PRIMITIVES_START 0x00000008
#define VIV_FE_DRAW_PRIMITIVES_COUNT 0x0000000c
#define VIV_FE_DRAW_INDEXED_PRIMITIVES 0x00000000
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER 0x00000000
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP__MASK 0xf8000000
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP__SHIFT 27
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP_DRAW_INDEXED_PRIMITIVES 0x30000000
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND 0x00000004
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__MASK 0x000000ff
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__SHIFT 0
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE(x) (((x) << VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__SHIFT) & VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__MASK)
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_START 0x00000008
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COUNT 0x0000000c
#define VIV_FE_DRAW_INDEXED_PRIMITIVES_OFFSET 0x00000010
#define VIV_FE_WAIT 0x00000000
#define VIV_FE_WAIT_HEADER 0x00000000
#define VIV_FE_WAIT_HEADER_DELAY__MASK 0x0000ffff
#define VIV_FE_WAIT_HEADER_DELAY__SHIFT 0
#define VIV_FE_WAIT_HEADER_DELAY(x) (((x) << VIV_FE_WAIT_HEADER_DELAY__SHIFT) & VIV_FE_WAIT_HEADER_DELAY__MASK)
#define VIV_FE_WAIT_HEADER_OP__MASK 0xf8000000
#define VIV_FE_WAIT_HEADER_OP__SHIFT 27
#define VIV_FE_WAIT_HEADER_OP_WAIT 0x38000000
#define VIV_FE_LINK 0x00000000
#define VIV_FE_LINK_HEADER 0x00000000
#define VIV_FE_LINK_HEADER_PREFETCH__MASK 0x0000ffff
#define VIV_FE_LINK_HEADER_PREFETCH__SHIFT 0
#define VIV_FE_LINK_HEADER_PREFETCH(x) (((x) << VIV_FE_LINK_HEADER_PREFETCH__SHIFT) & VIV_FE_LINK_HEADER_PREFETCH__MASK)
#define VIV_FE_LINK_HEADER_OP__MASK 0xf8000000
#define VIV_FE_LINK_HEADER_OP__SHIFT 27
#define VIV_FE_LINK_HEADER_OP_LINK 0x40000000
#define VIV_FE_LINK_ADDRESS 0x00000004
#define VIV_FE_STALL 0x00000000
#define VIV_FE_STALL_HEADER 0x00000000
#define VIV_FE_STALL_HEADER_OP__MASK 0xf8000000
#define VIV_FE_STALL_HEADER_OP__SHIFT 27
#define VIV_FE_STALL_HEADER_OP_STALL 0x48000000
#define VIV_FE_STALL_TOKEN 0x00000004
#define VIV_FE_STALL_TOKEN_FROM__MASK 0x0000001f
#define VIV_FE_STALL_TOKEN_FROM__SHIFT 0
#define VIV_FE_STALL_TOKEN_FROM(x) (((x) << VIV_FE_STALL_TOKEN_FROM__SHIFT) & VIV_FE_STALL_TOKEN_FROM__MASK)
#define VIV_FE_STALL_TOKEN_TO__MASK 0x00001f00
#define VIV_FE_STALL_TOKEN_TO__SHIFT 8
#define VIV_FE_STALL_TOKEN_TO(x) (((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK)
#define VIV_FE_CALL 0x00000000
#define VIV_FE_CALL_HEADER 0x00000000
#define VIV_FE_CALL_HEADER_PREFETCH__MASK 0x0000ffff
#define VIV_FE_CALL_HEADER_PREFETCH__SHIFT 0
#define VIV_FE_CALL_HEADER_PREFETCH(x) (((x) << VIV_FE_CALL_HEADER_PREFETCH__SHIFT) & VIV_FE_CALL_HEADER_PREFETCH__MASK)
#define VIV_FE_CALL_HEADER_OP__MASK 0xf8000000
#define VIV_FE_CALL_HEADER_OP__SHIFT 27
#define VIV_FE_CALL_HEADER_OP_CALL 0x50000000
#define VIV_FE_CALL_ADDRESS 0x00000004
#define VIV_FE_CALL_RETURN_PREFETCH 0x00000008
#define VIV_FE_CALL_RETURN_ADDRESS 0x0000000c
#define VIV_FE_RETURN 0x00000000
#define VIV_FE_RETURN_HEADER 0x00000000
#define VIV_FE_RETURN_HEADER_OP__MASK 0xf8000000
#define VIV_FE_RETURN_HEADER_OP__SHIFT 27
#define VIV_FE_RETURN_HEADER_OP_RETURN 0x58000000
#define VIV_FE_CHIP_SELECT 0x00000000
#define VIV_FE_CHIP_SELECT_HEADER 0x00000000
#define VIV_FE_CHIP_SELECT_HEADER_OP__MASK 0xf8000000
#define VIV_FE_CHIP_SELECT_HEADER_OP__SHIFT 27
#define VIV_FE_CHIP_SELECT_HEADER_OP_CHIP_SELECT 0x68000000
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP15 0x00008000
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP14 0x00004000
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP13 0x00002000
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP12 0x00001000
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP11 0x00000800
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP10 0x00000400
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP9 0x00000200
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP8 0x00000100
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP7 0x00000080
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP6 0x00000040
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP5 0x00000020
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP4 0x00000010
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP3 0x00000008
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP2 0x00000004
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP1 0x00000002
#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP0 0x00000001
#endif /* CMDSTREAM_XML */
#ifndef COMMON_XML
#define COMMON_XML
/* Autogenerated file, DO NOT EDIT manually!
This file was generated by the rules-ng-ng headergen tool in this git repository:
http://0x04.net/cgit/index.cgi/rules-ng-ng
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
- state_vg.xml ( 5973 bytes, from 2015-03-25 11:26:01)
- common.xml ( 18437 bytes, from 2015-03-25 11:27:41)
Copyright (C) 2015
*/
#define PIPE_ID_PIPE_3D 0x00000000
#define PIPE_ID_PIPE_2D 0x00000001
#define SYNC_RECIPIENT_FE 0x00000001
#define SYNC_RECIPIENT_RA 0x00000005
#define SYNC_RECIPIENT_PE 0x00000007
#define SYNC_RECIPIENT_DE 0x0000000b
#define SYNC_RECIPIENT_VG 0x0000000f
#define SYNC_RECIPIENT_TESSELATOR 0x00000010
#define SYNC_RECIPIENT_VG2 0x00000011
#define SYNC_RECIPIENT_TESSELATOR2 0x00000012
#define SYNC_RECIPIENT_VG3 0x00000013
#define SYNC_RECIPIENT_TESSELATOR3 0x00000014
#define ENDIAN_MODE_NO_SWAP 0x00000000
#define ENDIAN_MODE_SWAP_16 0x00000001
#define ENDIAN_MODE_SWAP_32 0x00000002
#define chipModel_GC300 0x00000300
#define chipModel_GC320 0x00000320
#define chipModel_GC350 0x00000350
#define chipModel_GC355 0x00000355
#define chipModel_GC400 0x00000400
#define chipModel_GC410 0x00000410
#define chipModel_GC420 0x00000420
#define chipModel_GC450 0x00000450
#define chipModel_GC500 0x00000500
#define chipModel_GC530 0x00000530
#define chipModel_GC600 0x00000600
#define chipModel_GC700 0x00000700
#define chipModel_GC800 0x00000800
#define chipModel_GC860 0x00000860
#define chipModel_GC880 0x00000880
#define chipModel_GC1000 0x00001000
#define chipModel_GC2000 0x00002000
#define chipModel_GC2100 0x00002100
#define chipModel_GC4000 0x00004000
#define RGBA_BITS_R 0x00000001
#define RGBA_BITS_G 0x00000002
#define RGBA_BITS_B 0x00000004
#define RGBA_BITS_A 0x00000008
#define chipFeatures_FAST_CLEAR 0x00000001
#define chipFeatures_SPECIAL_ANTI_ALIASING 0x00000002
#define chipFeatures_PIPE_3D 0x00000004
#define chipFeatures_DXT_TEXTURE_COMPRESSION 0x00000008
#define chipFeatures_DEBUG_MODE 0x00000010
#define chipFeatures_Z_COMPRESSION 0x00000020
#define chipFeatures_YUV420_SCALER 0x00000040
#define chipFeatures_MSAA 0x00000080
#define chipFeatures_DC 0x00000100
#define chipFeatures_PIPE_2D 0x00000200
#define chipFeatures_ETC1_TEXTURE_COMPRESSION 0x00000400
#define chipFeatures_FAST_SCALER 0x00000800
#define chipFeatures_HIGH_DYNAMIC_RANGE 0x00001000
#define chipFeatures_YUV420_TILER 0x00002000
#define chipFeatures_MODULE_CG 0x00004000
#define chipFeatures_MIN_AREA 0x00008000
#define chipFeatures_NO_EARLY_Z 0x00010000
#define chipFeatures_NO_422_TEXTURE 0x00020000
#define chipFeatures_BUFFER_INTERLEAVING 0x00040000
#define chipFeatures_BYTE_WRITE_2D 0x00080000
#define chipFeatures_NO_SCALER 0x00100000
#define chipFeatures_YUY2_AVERAGING 0x00200000
#define chipFeatures_HALF_PE_CACHE 0x00400000
#define chipFeatures_HALF_TX_CACHE 0x00800000
#define chipFeatures_YUY2_RENDER_TARGET 0x01000000
#define chipFeatures_MEM32 0x02000000
#define chipFeatures_PIPE_VG 0x04000000
#define chipFeatures_VGTS 0x08000000
#define chipFeatures_FE20 0x10000000
#define chipFeatures_BYTE_WRITE_3D 0x20000000
#define chipFeatures_RS_YUV_TARGET 0x40000000
#define chipFeatures_32_BIT_INDICES 0x80000000
#define chipMinorFeatures0_FLIP_Y 0x00000001
#define chipMinorFeatures0_DUAL_RETURN_BUS 0x00000002
#define chipMinorFeatures0_ENDIANNESS_CONFIG 0x00000004
#define chipMinorFeatures0_TEXTURE_8K 0x00000008
#define chipMinorFeatures0_CORRECT_TEXTURE_CONVERTER 0x00000010
#define chipMinorFeatures0_SPECIAL_MSAA_LOD 0x00000020
#define chipMinorFeatures0_FAST_CLEAR_FLUSH 0x00000040
#define chipMinorFeatures0_2DPE20 0x00000080
#define chipMinorFeatures0_CORRECT_AUTO_DISABLE 0x00000100
#define chipMinorFeatures0_RENDERTARGET_8K 0x00000200
#define chipMinorFeatures0_2BITPERTILE 0x00000400
#define chipMinorFeatures0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED 0x00000800
#define chipMinorFeatures0_SUPER_TILED 0x00001000
#define chipMinorFeatures0_VG_20 0x00002000
#define chipMinorFeatures0_TS_EXTENDED_COMMANDS 0x00004000
#define chipMinorFeatures0_COMPRESSION_FIFO_FIXED 0x00008000
#define chipMinorFeatures0_HAS_SIGN_FLOOR_CEIL 0x00010000
#define chipMinorFeatures0_VG_FILTER 0x00020000
#define chipMinorFeatures0_VG_21 0x00040000
#define chipMinorFeatures0_SHADER_HAS_W 0x00080000
#define chipMinorFeatures0_HAS_SQRT_TRIG 0x00100000
#define chipMinorFeatures0_MORE_MINOR_FEATURES 0x00200000
#define chipMinorFeatures0_MC20 0x00400000
#define chipMinorFeatures0_MSAA_SIDEBAND 0x00800000
#define chipMinorFeatures0_BUG_FIXES0 0x01000000
#define chipMinorFeatures0_VAA 0x02000000
#define chipMinorFeatures0_BYPASS_IN_MSAA 0x04000000
#define chipMinorFeatures0_HZ 0x08000000
#define chipMinorFeatures0_NEW_TEXTURE 0x10000000
#define chipMinorFeatures0_2D_A8_TARGET 0x20000000
#define chipMinorFeatures0_CORRECT_STENCIL 0x40000000
#define chipMinorFeatures0_ENHANCE_VR 0x80000000
#define chipMinorFeatures1_RSUV_SWIZZLE 0x00000001
#define chipMinorFeatures1_V2_COMPRESSION 0x00000002
#define chipMinorFeatures1_VG_DOUBLE_BUFFER 0x00000004
#define chipMinorFeatures1_EXTRA_EVENT_STATES 0x00000008
#define chipMinorFeatures1_NO_STRIPING_NEEDED 0x00000010
#define chipMinorFeatures1_TEXTURE_STRIDE 0x00000020
#define chipMinorFeatures1_BUG_FIXES3 0x00000040
#define chipMinorFeatures1_AUTO_DISABLE 0x00000080
#define chipMinorFeatures1_AUTO_RESTART_TS 0x00000100
#define chipMinorFeatures1_DISABLE_PE_GATING 0x00000200
#define chipMinorFeatures1_L2_WINDOWING 0x00000400
#define chipMinorFeatures1_HALF_FLOAT 0x00000800
#define chipMinorFeatures1_PIXEL_DITHER 0x00001000
#define chipMinorFeatures1_TWO_STENCIL_REFERENCE 0x00002000
#define chipMinorFeatures1_EXTENDED_PIXEL_FORMAT 0x00004000
#define chipMinorFeatures1_CORRECT_MIN_MAX_DEPTH 0x00008000
#define chipMinorFeatures1_2D_DITHER 0x00010000
#define chipMinorFeatures1_BUG_FIXES5 0x00020000
#define chipMinorFeatures1_NEW_2D 0x00040000
#define chipMinorFeatures1_NEW_FP 0x00080000
#define chipMinorFeatures1_TEXTURE_HALIGN 0x00100000
#define chipMinorFeatures1_NON_POWER_OF_TWO 0x00200000
#define chipMinorFeatures1_LINEAR_TEXTURE_SUPPORT 0x00400000
#define chipMinorFeatures1_HALTI0 0x00800000
#define chipMinorFeatures1_CORRECT_OVERFLOW_VG 0x01000000
#define chipMinorFeatures1_NEGATIVE_LOG_FIX 0x02000000
#define chipMinorFeatures1_RESOLVE_OFFSET 0x04000000
#define chipMinorFeatures1_OK_TO_GATE_AXI_CLOCK 0x08000000
#define chipMinorFeatures1_MMU_VERSION 0x10000000
#define chipMinorFeatures1_WIDE_LINE 0x20000000
#define chipMinorFeatures1_BUG_FIXES6 0x40000000
#define chipMinorFeatures1_FC_FLUSH_STALL 0x80000000
#define chipMinorFeatures2_LINE_LOOP 0x00000001
#define chipMinorFeatures2_LOGIC_OP 0x00000002
#define chipMinorFeatures2_UNK2 0x00000004
#define chipMinorFeatures2_SUPERTILED_TEXTURE 0x00000008
#define chipMinorFeatures2_UNK4 0x00000010
#define chipMinorFeatures2_RECT_PRIMITIVE 0x00000020
#define chipMinorFeatures2_COMPOSITION 0x00000040
#define chipMinorFeatures2_CORRECT_AUTO_DISABLE_COUNT 0x00000080
#define chipMinorFeatures2_UNK8 0x00000100
#define chipMinorFeatures2_UNK9 0x00000200
#define chipMinorFeatures2_UNK10 0x00000400
#define chipMinorFeatures2_SAMPLERBASE_16 0x00000800
#define chipMinorFeatures2_UNK12 0x00001000
#define chipMinorFeatures2_UNK13 0x00002000
#define chipMinorFeatures2_UNK14 0x00004000
#define chipMinorFeatures2_EXTRA_TEXTURE_STATE 0x00008000
#define chipMinorFeatures2_FULL_DIRECTFB 0x00010000
#define chipMinorFeatures2_2D_TILING 0x00020000
#define chipMinorFeatures2_THREAD_WALKER_IN_PS 0x00040000
#define chipMinorFeatures2_TILE_FILLER 0x00080000
#define chipMinorFeatures2_UNK20 0x00100000
#define chipMinorFeatures2_2D_MULTI_SOURCE_BLIT 0x00200000
#define chipMinorFeatures2_UNK22 0x00400000
#define chipMinorFeatures2_UNK23 0x00800000
#define chipMinorFeatures2_UNK24 0x01000000
#define chipMinorFeatures2_MIXED_STREAMS 0x02000000
#define chipMinorFeatures2_2D_420_L2CACHE 0x04000000
#define chipMinorFeatures2_UNK27 0x08000000
#define chipMinorFeatures2_2D_NO_INDEX8_BRUSH 0x10000000
#define chipMinorFeatures2_TEXTURE_TILED_READ 0x20000000
#define chipMinorFeatures2_UNK30 0x40000000
#define chipMinorFeatures2_UNK31 0x80000000
#define chipMinorFeatures3_ROTATION_STALL_FIX 0x00000001
#define chipMinorFeatures3_UNK1 0x00000002
#define chipMinorFeatures3_2D_MULTI_SOURCE_BLT_EX 0x00000004
#define chipMinorFeatures3_UNK3 0x00000008
#define chipMinorFeatures3_UNK4 0x00000010
#define chipMinorFeatures3_UNK5 0x00000020
#define chipMinorFeatures3_UNK6 0x00000040
#define chipMinorFeatures3_UNK7 0x00000080
#define chipMinorFeatures3_UNK8 0x00000100
#define chipMinorFeatures3_UNK9 0x00000200
#define chipMinorFeatures3_BUG_FIXES10 0x00000400
#define chipMinorFeatures3_UNK11 0x00000800
#define chipMinorFeatures3_BUG_FIXES11 0x00001000
#define chipMinorFeatures3_UNK13 0x00002000
#define chipMinorFeatures3_UNK14 0x00004000
#define chipMinorFeatures3_UNK15 0x00008000
#define chipMinorFeatures3_UNK16 0x00010000
#define chipMinorFeatures3_UNK17 0x00020000
#define chipMinorFeatures3_UNK18 0x00040000
#define chipMinorFeatures3_UNK19 0x00080000
#define chipMinorFeatures3_UNK20 0x00100000
#define chipMinorFeatures3_UNK21 0x00200000
#define chipMinorFeatures3_UNK22 0x00400000
#define chipMinorFeatures3_UNK23 0x00800000
#define chipMinorFeatures3_UNK24 0x01000000
#define chipMinorFeatures3_UNK25 0x02000000
#define chipMinorFeatures3_UNK26 0x04000000
#define chipMinorFeatures3_UNK27 0x08000000
#define chipMinorFeatures3_UNK28 0x10000000
#define chipMinorFeatures3_UNK29 0x20000000
#define chipMinorFeatures3_UNK30 0x40000000
#define chipMinorFeatures3_UNK31 0x80000000
#define chipMinorFeatures4_UNK0 0x00000001
#define chipMinorFeatures4_UNK1 0x00000002
#define chipMinorFeatures4_UNK2 0x00000004
#define chipMinorFeatures4_UNK3 0x00000008
#define chipMinorFeatures4_UNK4 0x00000010
#define chipMinorFeatures4_UNK5 0x00000020
#define chipMinorFeatures4_UNK6 0x00000040
#define chipMinorFeatures4_UNK7 0x00000080
#define chipMinorFeatures4_UNK8 0x00000100
#define chipMinorFeatures4_UNK9 0x00000200
#define chipMinorFeatures4_UNK10 0x00000400
#define chipMinorFeatures4_UNK11 0x00000800
#define chipMinorFeatures4_UNK12 0x00001000
#define chipMinorFeatures4_UNK13 0x00002000
#define chipMinorFeatures4_UNK14 0x00004000
#define chipMinorFeatures4_UNK15 0x00008000
#define chipMinorFeatures4_UNK16 0x00010000
#define chipMinorFeatures4_UNK17 0x00020000
#define chipMinorFeatures4_UNK18 0x00040000
#define chipMinorFeatures4_UNK19 0x00080000
#define chipMinorFeatures4_UNK20 0x00100000
#define chipMinorFeatures4_UNK21 0x00200000
#define chipMinorFeatures4_UNK22 0x00400000
#define chipMinorFeatures4_UNK23 0x00800000
#define chipMinorFeatures4_UNK24 0x01000000
#define chipMinorFeatures4_UNK25 0x02000000
#define chipMinorFeatures4_UNK26 0x04000000
#define chipMinorFeatures4_UNK27 0x08000000
#define chipMinorFeatures4_UNK28 0x10000000
#define chipMinorFeatures4_UNK29 0x20000000
#define chipMinorFeatures4_UNK30 0x40000000
#define chipMinorFeatures4_UNK31 0x80000000
#endif /* COMMON_XML */
/*
* Copyright (C) 2014 Etnaviv Project
* Author: Christian Gmeiner <christian.gmeiner@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "etnaviv_gpu.h"
#include "etnaviv_gem.h"
#include "etnaviv_mmu.h"
#include "common.xml.h"
#include "state.xml.h"
#include "cmdstream.xml.h"
/*
* Command Buffer helper:
*/
static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data)
{
u32 *vaddr = (u32 *)buffer->vaddr;
BUG_ON(buffer->user_size >= buffer->size);
vaddr[buffer->user_size / 4] = data;
buffer->user_size += 4;
}
static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer,
u32 reg, u32 value)
{
u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR;
buffer->user_size = ALIGN(buffer->user_size, 8);
/* write a register via cmd stream */
OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE |
VIV_FE_LOAD_STATE_HEADER_COUNT(1) |
VIV_FE_LOAD_STATE_HEADER_OFFSET(index));
OUT(buffer, value);
}
static inline void CMD_END(struct etnaviv_cmdbuf *buffer)
{
buffer->user_size = ALIGN(buffer->user_size, 8);
OUT(buffer, VIV_FE_END_HEADER_OP_END);
}
static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer)
{
buffer->user_size = ALIGN(buffer->user_size, 8);
OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT | 200);
}
static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer,
u16 prefetch, u32 address)
{
buffer->user_size = ALIGN(buffer->user_size, 8);
OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK |
VIV_FE_LINK_HEADER_PREFETCH(prefetch));
OUT(buffer, address);
}
static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer,
u32 from, u32 to)
{
buffer->user_size = ALIGN(buffer->user_size, 8);
OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL);
OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
}
static void etnaviv_cmd_select_pipe(struct etnaviv_cmdbuf *buffer, u8 pipe)
{
u32 flush;
u32 stall;
/*
* This assumes that if we're switching to 2D, we're switching
* away from 3D, and vice versa. Hence, if we're switching to
* the 2D core, we need to flush the 3D depth and color caches,
* otherwise we need to flush the 2D pixel engine cache.
*/
if (pipe == ETNA_PIPE_2D)
flush = VIVS_GL_FLUSH_CACHE_DEPTH | VIVS_GL_FLUSH_CACHE_COLOR;
else
flush = VIVS_GL_FLUSH_CACHE_PE2D;
stall = VIVS_GL_SEMAPHORE_TOKEN_FROM(SYNC_RECIPIENT_FE) |
VIVS_GL_SEMAPHORE_TOKEN_TO(SYNC_RECIPIENT_PE);
CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush);
CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN, stall);
CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);