Commit ec72fce4 authored by Ram Amrani's avatar Ram Amrani Committed by Doug Ledford
Browse files

qedr: Add support for RoCE HW init



Allocate and setup RoCE resources, interrupts and completion queues.
Adds device attributes.
Signed-off-by: default avatarRajesh Borundia <rajesh.borundia@cavium.com>
Signed-off-by: default avatarRam Amrani <Ram.Amrani@cavium.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent 2e0cbc4d
......@@ -36,6 +36,8 @@
#include <linux/iommu.h>
#include <net/addrconf.h>
#include <linux/qed/qede_roce.h>
#include <linux/qed/qed_chain.h>
#include <linux/qed/qed_if.h>
#include "qedr.h"
MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
......@@ -61,6 +63,17 @@ static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
return IB_LINK_LAYER_ETHERNET;
}
static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str,
size_t str_len)
{
struct qedr_dev *qedr = get_qedr_dev(ibdev);
u32 fw_ver = (u32)qedr->attr.fw_ver;
snprintf(str, str_len, "%d. %d. %d. %d",
(fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
(fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
}
static int qedr_register_device(struct qedr_dev *dev)
{
strlcpy(dev->ibdev.name, "qedr%d", IB_DEVICE_NAME_MAX);
......@@ -69,10 +82,139 @@ static int qedr_register_device(struct qedr_dev *dev)
dev->ibdev.owner = THIS_MODULE;
dev->ibdev.get_link_layer = qedr_link_layer;
dev->ibdev.get_dev_fw_str = qedr_get_dev_fw_str;
return 0;
}
/* This function allocates fast-path status block memory */
static int qedr_alloc_mem_sb(struct qedr_dev *dev,
struct qed_sb_info *sb_info, u16 sb_id)
{
struct status_block *sb_virt;
dma_addr_t sb_phys;
int rc;
sb_virt = dma_alloc_coherent(&dev->pdev->dev,
sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
if (!sb_virt)
return -ENOMEM;
rc = dev->ops->common->sb_init(dev->cdev, sb_info,
sb_virt, sb_phys, sb_id,
QED_SB_TYPE_CNQ);
if (rc) {
pr_err("Status block initialization failed\n");
dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
sb_virt, sb_phys);
return rc;
}
return 0;
}
static void qedr_free_mem_sb(struct qedr_dev *dev,
struct qed_sb_info *sb_info, int sb_id)
{
if (sb_info->sb_virt) {
dev->ops->common->sb_release(dev->cdev, sb_info, sb_id);
dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
(void *)sb_info->sb_virt, sb_info->sb_phys);
}
}
static void qedr_free_resources(struct qedr_dev *dev)
{
int i;
for (i = 0; i < dev->num_cnq; i++) {
qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
}
kfree(dev->cnq_array);
kfree(dev->sb_array);
kfree(dev->sgid_tbl);
}
static int qedr_alloc_resources(struct qedr_dev *dev)
{
struct qedr_cnq *cnq;
__le16 *cons_pi;
u16 n_entries;
int i, rc;
dev->sgid_tbl = kzalloc(sizeof(union ib_gid) *
QEDR_MAX_SGID, GFP_KERNEL);
if (!dev->sgid_tbl)
return -ENOMEM;
spin_lock_init(&dev->sgid_lock);
/* Allocate Status blocks for CNQ */
dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
GFP_KERNEL);
if (!dev->sb_array) {
rc = -ENOMEM;
goto err1;
}
dev->cnq_array = kcalloc(dev->num_cnq,
sizeof(*dev->cnq_array), GFP_KERNEL);
if (!dev->cnq_array) {
rc = -ENOMEM;
goto err2;
}
dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
/* Allocate CNQ PBLs */
n_entries = min_t(u32, QED_RDMA_MAX_CNQ_SIZE, QEDR_ROCE_MAX_CNQ_SIZE);
for (i = 0; i < dev->num_cnq; i++) {
cnq = &dev->cnq_array[i];
rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
dev->sb_start + i);
if (rc)
goto err3;
rc = dev->ops->common->chain_alloc(dev->cdev,
QED_CHAIN_USE_TO_CONSUME,
QED_CHAIN_MODE_PBL,
QED_CHAIN_CNT_TYPE_U16,
n_entries,
sizeof(struct regpair *),
&cnq->pbl);
if (rc)
goto err4;
cnq->dev = dev;
cnq->sb = &dev->sb_array[i];
cons_pi = dev->sb_array[i].sb_virt->pi_array;
cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
cnq->index = i;
sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
i, qed_chain_get_cons_idx(&cnq->pbl));
}
return 0;
err4:
qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
err3:
for (--i; i >= 0; i--) {
dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
}
kfree(dev->cnq_array);
err2:
kfree(dev->sb_array);
err1:
kfree(dev->sgid_tbl);
return rc;
}
/* QEDR sysfs interface */
static ssize_t show_rev(struct device *device, struct device_attribute *attr,
char *buf)
......@@ -146,9 +288,240 @@ static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
}
}
static const struct qed_rdma_ops *qed_ops;
#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
static irqreturn_t qedr_irq_handler(int irq, void *handle)
{
u16 hw_comp_cons, sw_comp_cons;
struct qedr_cnq *cnq = handle;
qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
qed_sb_update_sb_idx(cnq->sb);
hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
/* Align protocol-index and chain reads */
rmb();
while (sw_comp_cons != hw_comp_cons) {
sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
cnq->n_comp++;
}
qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
sw_comp_cons);
qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
return IRQ_HANDLED;
}
static void qedr_sync_free_irqs(struct qedr_dev *dev)
{
u32 vector;
int i;
for (i = 0; i < dev->int_info.used_cnt; i++) {
if (dev->int_info.msix_cnt) {
vector = dev->int_info.msix[i * dev->num_hwfns].vector;
synchronize_irq(vector);
free_irq(vector, &dev->cnq_array[i]);
}
}
dev->int_info.used_cnt = 0;
}
static int qedr_req_msix_irqs(struct qedr_dev *dev)
{
int i, rc = 0;
if (dev->num_cnq > dev->int_info.msix_cnt) {
DP_ERR(dev,
"Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
dev->num_cnq, dev->int_info.msix_cnt);
return -EINVAL;
}
for (i = 0; i < dev->num_cnq; i++) {
rc = request_irq(dev->int_info.msix[i * dev->num_hwfns].vector,
qedr_irq_handler, 0, dev->cnq_array[i].name,
&dev->cnq_array[i]);
if (rc) {
DP_ERR(dev, "Request cnq %d irq failed\n", i);
qedr_sync_free_irqs(dev);
} else {
DP_DEBUG(dev, QEDR_MSG_INIT,
"Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
dev->cnq_array[i].name, i,
&dev->cnq_array[i]);
dev->int_info.used_cnt++;
}
}
return rc;
}
static int qedr_setup_irqs(struct qedr_dev *dev)
{
int rc;
DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
/* Learn Interrupt configuration */
rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
if (rc < 0)
return rc;
rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
if (rc) {
DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
return rc;
}
if (dev->int_info.msix_cnt) {
DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
dev->int_info.msix_cnt);
rc = qedr_req_msix_irqs(dev);
if (rc)
return rc;
}
DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
return 0;
}
static int qedr_set_device_attr(struct qedr_dev *dev)
{
struct qed_rdma_device *qed_attr;
struct qedr_device_attr *attr;
u32 page_size;
/* Part 1 - query core capabilities */
qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
/* Part 2 - check capabilities */
page_size = ~dev->attr.page_size_caps + 1;
if (page_size > PAGE_SIZE) {
DP_ERR(dev,
"Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
PAGE_SIZE, page_size);
return -ENODEV;
}
/* Part 3 - copy and update capabilities */
attr = &dev->attr;
attr->vendor_id = qed_attr->vendor_id;
attr->vendor_part_id = qed_attr->vendor_part_id;
attr->hw_ver = qed_attr->hw_ver;
attr->fw_ver = qed_attr->fw_ver;
attr->node_guid = qed_attr->node_guid;
attr->sys_image_guid = qed_attr->sys_image_guid;
attr->max_cnq = qed_attr->max_cnq;
attr->max_sge = qed_attr->max_sge;
attr->max_inline = qed_attr->max_inline;
attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
attr->max_dev_resp_rd_atomic_resc =
qed_attr->max_dev_resp_rd_atomic_resc;
attr->max_cq = qed_attr->max_cq;
attr->max_qp = qed_attr->max_qp;
attr->max_mr = qed_attr->max_mr;
attr->max_mr_size = qed_attr->max_mr_size;
attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
attr->max_mw = qed_attr->max_mw;
attr->max_fmr = qed_attr->max_fmr;
attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
attr->max_pd = qed_attr->max_pd;
attr->max_ah = qed_attr->max_ah;
attr->max_pkey = qed_attr->max_pkey;
attr->max_srq = qed_attr->max_srq;
attr->max_srq_wr = qed_attr->max_srq_wr;
attr->dev_caps = qed_attr->dev_caps;
attr->page_size_caps = qed_attr->page_size_caps;
attr->dev_ack_delay = qed_attr->dev_ack_delay;
attr->reserved_lkey = qed_attr->reserved_lkey;
attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
attr->max_stats_queues = qed_attr->max_stats_queues;
return 0;
}
static int qedr_init_hw(struct qedr_dev *dev)
{
struct qed_rdma_add_user_out_params out_params;
struct qed_rdma_start_in_params *in_params;
struct qed_rdma_cnq_params *cur_pbl;
struct qed_rdma_events events;
dma_addr_t p_phys_table;
u32 page_cnt;
int rc = 0;
int i;
in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
if (!in_params) {
rc = -ENOMEM;
goto out;
}
in_params->desired_cnq = dev->num_cnq;
for (i = 0; i < dev->num_cnq; i++) {
cur_pbl = &in_params->cnq_pbl_list[i];
page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
cur_pbl->num_pbl_pages = page_cnt;
p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
cur_pbl->pbl_ptr = (u64)p_phys_table;
}
events.context = dev;
in_params->events = &events;
in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
in_params->max_mtu = dev->ndev->mtu;
ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
rc = dev->ops->rdma_init(dev->cdev, in_params);
if (rc)
goto out;
rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
if (rc)
goto out;
dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr;
dev->db_phys_addr = out_params.dpi_phys_addr;
dev->db_size = out_params.dpi_size;
dev->dpi = out_params.dpi;
rc = qedr_set_device_attr(dev);
out:
kfree(in_params);
if (rc)
DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
return rc;
}
void qedr_stop_hw(struct qedr_dev *dev)
{
dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
dev->ops->rdma_stop(dev->rdma_ctx);
}
static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
struct net_device *ndev)
{
struct qed_dev_rdma_info dev_info;
struct qedr_dev *dev;
int rc = 0, i;
......@@ -164,21 +537,59 @@ static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
dev->ndev = ndev;
dev->cdev = cdev;
qed_ops = qed_get_rdma_ops();
if (!qed_ops) {
DP_ERR(dev, "Failed to get qed roce operations\n");
goto init_err;
}
dev->ops = qed_ops;
rc = qed_ops->fill_dev_info(cdev, &dev_info);
if (rc)
goto init_err;
dev->num_hwfns = dev_info.common.num_hwfns;
dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
if (!dev->num_cnq) {
DP_ERR(dev, "not enough CNQ resources.\n");
goto init_err;
}
qedr_pci_set_atomic(dev, pdev);
rc = qedr_alloc_resources(dev);
if (rc)
goto init_err;
rc = qedr_init_hw(dev);
if (rc)
goto alloc_err;
rc = qedr_setup_irqs(dev);
if (rc)
goto irq_err;
rc = qedr_register_device(dev);
if (rc) {
DP_ERR(dev, "Unable to allocate register device\n");
goto init_err;
goto reg_err;
}
for (i = 0; i < ARRAY_SIZE(qedr_attributes); i++)
if (device_create_file(&dev->ibdev.dev, qedr_attributes[i]))
goto init_err;
goto reg_err;
DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
return dev;
reg_err:
qedr_sync_free_irqs(dev);
irq_err:
qedr_stop_hw(dev);
alloc_err:
qedr_free_resources(dev);
init_err:
ib_dealloc_device(&dev->ibdev);
DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
......@@ -193,6 +604,9 @@ static void qedr_remove(struct qedr_dev *dev)
*/
qedr_remove_sysfiles(dev);
qedr_stop_hw(dev);
qedr_sync_free_irqs(dev);
qedr_free_resources(dev);
ib_dealloc_device(&dev->ibdev);
}
......
......@@ -35,7 +35,10 @@
#include <linux/pci.h>
#include <rdma/ib_addr.h>
#include <linux/qed/qed_if.h>
#include <linux/qed/qed_chain.h>
#include <linux/qed/qed_roce_if.h>
#include <linux/qed/qede_roce.h>
#include "qedr_hsi.h"
#define QEDR_MODULE_VERSION "8.10.10.0"
#define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
......@@ -47,6 +50,60 @@
#define QEDR_MSG_INIT "INIT"
struct qedr_dev;
struct qedr_cnq {
struct qedr_dev *dev;
struct qed_chain pbl;
struct qed_sb_info *sb;
char name[32];
u64 n_comp;
__le16 *hw_cons_ptr;
u8 index;
};
#define QEDR_MAX_SGID 128
struct qedr_device_attr {
u32 vendor_id;
u32 vendor_part_id;
u32 hw_ver;
u64 fw_ver;
u64 node_guid;
u64 sys_image_guid;
u8 max_cnq;
u8 max_sge;
u16 max_inline;
u32 max_sqe;
u32 max_rqe;
u8 max_qp_resp_rd_atomic_resc;
u8 max_qp_req_rd_atomic_resc;
u64 max_dev_resp_rd_atomic_resc;
u32 max_cq;
u32 max_qp;
u32 max_mr;
u64 max_mr_size;
u32 max_cqe;
u32 max_mw;
u32 max_fmr;
u32 max_mr_mw_fmr_pbl;
u64 max_mr_mw_fmr_size;
u32 max_pd;
u32 max_ah;
u8 max_pkey;
u32 max_srq;
u32 max_srq_wr;
u8 max_srq_sge;
u8 max_stats_queues;
u32 dev_caps;
u64 page_size_caps;
u8 dev_ack_delay;
u32 reserved_lkey;
u32 bad_pkey_counter;
struct qed_rdma_events events;
};
struct qedr_dev {
struct ib_device ibdev;
struct qed_dev *cdev;
......@@ -55,7 +112,73 @@ struct qedr_dev {
enum ib_atomic_cap atomic_cap;
void *rdma_ctx;
struct qedr_device_attr attr;
const struct qed_rdma_ops *ops;
struct qed_int_info int_info;
struct qed_sb_info *sb_array;
struct qedr_cnq *cnq_array;
int num_cnq;
int sb_start;
void __iomem *db_addr;
u64 db_phys_addr;
u32 db_size;
u16 dpi;
union ib_gid *sgid_tbl;
/* Lock for sgid table */
spinlock_t sgid_lock;
u64 guid;
u32 dp_module;
u8 dp_level;
u8 num_hwfns;
};
#define QEDR_MAX_SQ_PBL (0x8000)
#define QEDR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *))
#define QEDR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge))
#define QEDR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
QEDR_SQE_ELEMENT_SIZE)
#define QEDR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
QEDR_SQE_ELEMENT_SIZE)
#define QEDR_MAX_SQE ((QEDR_MAX_SQ_PBL_ENTRIES) *\
(RDMA_RING_PAGE_SIZE) / \
(QEDR_SQE_ELEMENT_SIZE) /\
(QEDR_MAX_SQE_ELEMENTS_PER_SQE))
/* RQ */
#define QEDR_MAX_RQ_PBL (0x2000)
#define QEDR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *))
#define QEDR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge))
#define QEDR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE)
#define QEDR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \
QEDR_RQE_ELEMENT_SIZE)
#define QEDR_MAX_RQE ((QEDR_MAX_RQ_PBL_ENTRIES) *\
(RDMA_RING_PAGE_SIZE) / \
(QEDR_RQE_ELEMENT_SIZE) /\
(QEDR_MAX_RQE_ELEMENTS_PER_RQE))
#define QEDR_CQE_SIZE (sizeof(union rdma_cqe))
#define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
#define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
sizeof(u64)) - 1)
#define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
(QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
#define QEDR_ROCE_MAX_CNQ_SIZE (0x4000)
#define QEDR_MAX_PORT (1)
#define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)