- 08 Nov, 2019 40 commits
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Philippe Gerum authored
At this chance, switch the min_delay_tick value to unsigned long to match the corresponding clockevent definition.
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Philippe Gerum authored
Drop the legacy support for architectures not enabling the generic clock event framework, which would only provide periodic timing. We don't support any of those archs, and there is no point in running a Xenomai co-kernel on a hardware not capable of handling oneshot timing requests.
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Philippe Gerum authored
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Philippe Gerum authored
Now that stop_machine() guarantees fully atomic execution of the stop routine via hard interrupt disabling, there is no point in using ipipe_critical_enter/exit() for the same purpose in order to patch the kernel text.
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Philippe Gerum authored
stop_machine() guarantees that all online CPUs are spinning non-preemptible in a known code location before a subset of them may safely run a stop-context function. This service is typically useful for live patching the kernel code, or changing global memory mappings, so that no activity could run in parallel until the system has returned to a stable state after all stop-context operations have completed. When interrupt pipelining is enabled, we have to provide the same guarantee by restoring hard interrupt disabling where virtualizing the interrupt disable flag would defeat it.
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Philippe Gerum authored
The lockdep engine will check for the current interrupt state as part of the locking validation process, which must encompass: - the CPU interrupt state - the current pipeline domain - the virtual interrupt disable flag so that we can traverse the tracepoints from any context sanely and safely. In addition trace_hardirqs_on_virt_caller() should be called by the arch-dependent code when tracking the interrupt state before returning to user-space after a kernel entry (exceptions, IRQ). This makes sure that the tracking logic only applies to the root domain, and considers the virtual disable flag exclusively. For instance, the kernel may be entered when interrupts are (only) virtually disabled for the root domain (i.e. stalled), and we should tell the IRQ tracing logic that IRQs are about to be enabled back only if the root domain is unstalled before leaving to user-space. In such a context, the state of the interrupt bit in the CPU would be irrelevant.
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Fix up the PMU controller driver of the Marvell Dove SoC in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up Synopsys's PCIE driver in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up Altera's PCIE driver in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up the pin controller driver of the Allwinner A1x SoCs in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up the pin controller driver of the Broadcom 2835 SoC in order to channel interrupts through the interrupt pipeline.
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Fix up the pin controller driver of the Rockchip SoC in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Enable the serial driver for raw_printk() output.
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Philippe Gerum authored
Enable the serial driver for raw_printk() output.
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Philippe Gerum authored
Enable the serial driver for raw_printk() output.
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Philippe Gerum authored
Fix up Freescale's general power controller driver in order to channel interrupts through the interrupt pipeline.
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Fix up Broadcom's Generic Set Top Box (Level 2) interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Fixup Broadcom's BCM7120 (Level 2) interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Fix up ATMEL's AIC5 interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Fix up the OMAP INTC interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Fix up the OMAP GPMC interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Fix up the ARM VIC interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up the Versatile FPGA interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up Allwinner's (A20/A31) IRQ controller driver in order to channel interrupts through the interrupt pipeline.
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Fix up the ARM generic interrupt controller (v3) driver in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up the ARM generic interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Fix up the Synopsys APB interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Fix up TI's crossbar interrupt controller driver in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up the interrupt controller driver of the Broadcom 2836 SoC in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up the interrupt controller driver of the Broadcom 2835 SoC in order to channel interrupts through the interrupt pipeline.
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Fix up the Atmel AIC driver in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up the IPU (GPU) driver in order to channel interrupts through the interrupt pipeline.
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Philippe Gerum authored
Fix up the Zynq GPIO driver in order to channel interrupts through the interrupt pipeline.
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Fix up the pl061 GPIO driver in order to channel interrupts through the interrupt pipeline.
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