wilc_spi.c 24.8 KB
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/* ////////////////////////////////////////////////////////////////////////// */
/*  */
/* Copyright (c) Atmel Corporation.  All rights reserved. */
/*  */
/* Module Name:  wilc_spi.c */
/*  */
/*  */
/* //////////////////////////////////////////////////////////////////////////// */
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#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/cdev.h>
#include <linux/uaccess.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/of_gpio.h>
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#include <linux/string.h>
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#include "wilc_wlan_if.h"
#include "wilc_wlan.h"
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#include "wilc_wfi_netdevice.h"
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struct wilc_spi {
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	int crc_off;
	int nint;
	int has_thrpt_enh;
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};
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static struct wilc_spi g_spi;
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static int wilc_spi_read(struct wilc *wilc, u32, u8 *, u32);
static int wilc_spi_write(struct wilc *wilc, u32, u8 *, u32);
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/********************************************
 *
 *      Crc7
 *
 ********************************************/

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static const u8 crc7_syndrome_table[256] = {
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	0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
	0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
	0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
	0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
	0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
	0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
	0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
	0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
	0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
	0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
	0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
	0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
	0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
	0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
	0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
	0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
	0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
	0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
	0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
	0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
	0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
	0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
	0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
	0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
	0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
	0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
	0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
	0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
	0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
	0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
	0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
	0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
};

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static u8 crc7_byte(u8 crc, u8 data)
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{
	return crc7_syndrome_table[(crc << 1) ^ data];
}

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static u8 crc7(u8 crc, const u8 *buffer, u32 len)
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{
	while (len--)
		crc = crc7_byte(crc, *buffer++);
	return crc;
}

/********************************************
 *
 *      Spi protocol Function
 *
 ********************************************/

#define CMD_DMA_WRITE				0xc1
#define CMD_DMA_READ				0xc2
#define CMD_INTERNAL_WRITE		0xc3
#define CMD_INTERNAL_READ		0xc4
#define CMD_TERMINATE				0xc5
#define CMD_REPEAT					0xc6
#define CMD_DMA_EXT_WRITE		0xc7
#define CMD_DMA_EXT_READ		0xc8
#define CMD_SINGLE_WRITE			0xc9
#define CMD_SINGLE_READ			0xca
#define CMD_RESET						0xcf

#define N_OK								1
#define N_FAIL								0
#define N_RESET							-1
#define N_RETRY							-2

#define DATA_PKT_SZ_256				256
#define DATA_PKT_SZ_512			512
#define DATA_PKT_SZ_1K				1024
#define DATA_PKT_SZ_4K				(4 * 1024)
#define DATA_PKT_SZ_8K				(8 * 1024)
#define DATA_PKT_SZ					DATA_PKT_SZ_8K

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#define USE_SPI_DMA     0

static int wilc_bus_probe(struct spi_device *spi)
{
	int ret, gpio;
	struct wilc *wilc;

	gpio = of_get_gpio(spi->dev.of_node, 0);
	if (gpio < 0)
		gpio = GPIO_NUM;

	ret = wilc_netdev_init(&wilc, NULL, HIF_SPI, GPIO_NUM, &wilc_hif_spi);
	if (ret)
		return ret;

	spi_set_drvdata(spi, wilc);
	wilc->dev = &spi->dev;

	return 0;
}

static int wilc_bus_remove(struct spi_device *spi)
{
	wilc_netdev_cleanup(spi_get_drvdata(spi));
	return 0;
}

static const struct of_device_id wilc1000_of_match[] = {
	{ .compatible = "atmel,wilc_spi", },
	{}
};
MODULE_DEVICE_TABLE(of, wilc1000_of_match);

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static struct spi_driver wilc1000_spi_driver = {
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	.driver = {
		.name = MODALIAS,
		.of_match_table = wilc1000_of_match,
	},
	.probe =  wilc_bus_probe,
	.remove = wilc_bus_remove,
};
module_spi_driver(wilc1000_spi_driver);
MODULE_LICENSE("GPL");

static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
{
	struct spi_device *spi = to_spi_device(wilc->dev);
	int ret;
	struct spi_message msg;

	if (len > 0 && b) {
		struct spi_transfer tr = {
			.tx_buf = b,
			.len = len,
			.delay_usecs = 0,
		};
		char *r_buffer = kzalloc(len, GFP_KERNEL);

		if (!r_buffer)
			return -ENOMEM;

		tr.rx_buf = r_buffer;
		dev_dbg(&spi->dev, "Request writing %d bytes\n", len);

		memset(&msg, 0, sizeof(msg));
		spi_message_init(&msg);
		msg.spi = spi;
		msg.is_dma_mapped = USE_SPI_DMA;
		spi_message_add_tail(&tr, &msg);

		ret = spi_sync(spi, &msg);
		if (ret < 0)
			dev_err(&spi->dev, "SPI transaction failed\n");

		kfree(r_buffer);
	} else {
		dev_err(&spi->dev,
			"can't write data with the following length: %d\n",
			len);
		ret = -EINVAL;
	}

	return ret;
}

static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
{
	struct spi_device *spi = to_spi_device(wilc->dev);
	int ret;

	if (rlen > 0) {
		struct spi_message msg;
		struct spi_transfer tr = {
			.rx_buf = rb,
			.len = rlen,
			.delay_usecs = 0,

		};
		char *t_buffer = kzalloc(rlen, GFP_KERNEL);

		if (!t_buffer)
			return -ENOMEM;

		tr.tx_buf = t_buffer;

		memset(&msg, 0, sizeof(msg));
		spi_message_init(&msg);
		msg.spi = spi;
		msg.is_dma_mapped = USE_SPI_DMA;
		spi_message_add_tail(&tr, &msg);

		ret = spi_sync(spi, &msg);
		if (ret < 0)
			dev_err(&spi->dev, "SPI transaction failed\n");
		kfree(t_buffer);
	} else {
		dev_err(&spi->dev,
			"can't read data with the following length: %u\n",
			rlen);
		ret = -EINVAL;
	}

	return ret;
}

static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
{
	struct spi_device *spi = to_spi_device(wilc->dev);
	int ret;

	if (rlen > 0) {
		struct spi_message msg;
		struct spi_transfer tr = {
			.rx_buf = rb,
			.tx_buf = wb,
			.len = rlen,
			.bits_per_word = 8,
			.delay_usecs = 0,

		};

		memset(&msg, 0, sizeof(msg));
		spi_message_init(&msg);
		msg.spi = spi;
		msg.is_dma_mapped = USE_SPI_DMA;

		spi_message_add_tail(&tr, &msg);
		ret = spi_sync(spi, &msg);
		if (ret < 0)
			dev_err(&spi->dev, "SPI transaction failed\n");
	} else {
		dev_err(&spi->dev,
			"can't read data with the following length: %u\n",
			rlen);
		ret = -EINVAL;
	}

	return ret;
}

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static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
			    u8 clockless)
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{
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	struct spi_device *spi = to_spi_device(wilc->dev);
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	u8 wb[32], rb[32];
	u8 wix, rix;
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	u32 len2;
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	u8 rsp;
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	int len = 0;
	int result = N_OK;

	wb[0] = cmd;
	switch (cmd) {
	case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
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		wb[1] = (u8)(adr >> 16);
		wb[2] = (u8)(adr >> 8);
		wb[3] = (u8)adr;
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		len = 5;
		break;

	case CMD_INTERNAL_READ:                 /* internal register read */
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		wb[1] = (u8)(adr >> 8);
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		if (clockless == 1)
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			wb[1] |= BIT(7);
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		wb[2] = (u8)adr;
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		wb[3] = 0x00;
		len = 5;
		break;

	case CMD_TERMINATE:                                     /* termination */
		wb[1] = 0x00;
		wb[2] = 0x00;
		wb[3] = 0x00;
		len = 5;
		break;

	case CMD_REPEAT:                                                /* repeat */
		wb[1] = 0x00;
		wb[2] = 0x00;
		wb[3] = 0x00;
		len = 5;
		break;

	case CMD_RESET:                                                 /* reset */
		wb[1] = 0xff;
		wb[2] = 0xff;
		wb[3] = 0xff;
		len = 5;
		break;

	case CMD_DMA_WRITE:                                     /* dma write */
	case CMD_DMA_READ:                                      /* dma read */
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		wb[1] = (u8)(adr >> 16);
		wb[2] = (u8)(adr >> 8);
		wb[3] = (u8)adr;
		wb[4] = (u8)(sz >> 8);
		wb[5] = (u8)(sz);
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		len = 7;
		break;

	case CMD_DMA_EXT_WRITE:         /* dma extended write */
	case CMD_DMA_EXT_READ:                  /* dma extended read */
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		wb[1] = (u8)(adr >> 16);
		wb[2] = (u8)(adr >> 8);
		wb[3] = (u8)adr;
		wb[4] = (u8)(sz >> 16);
		wb[5] = (u8)(sz >> 8);
		wb[6] = (u8)(sz);
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		len = 8;
		break;

	case CMD_INTERNAL_WRITE:                /* internal register write */
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		wb[1] = (u8)(adr >> 8);
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		if (clockless == 1)
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			wb[1] |= BIT(7);
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		wb[2] = (u8)(adr);
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		wb[3] = b[3];
		wb[4] = b[2];
		wb[5] = b[1];
		wb[6] = b[0];
		len = 8;
		break;

	case CMD_SINGLE_WRITE:                  /* single word write */
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		wb[1] = (u8)(adr >> 16);
		wb[2] = (u8)(adr >> 8);
		wb[3] = (u8)(adr);
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		wb[4] = b[3];
		wb[5] = b[2];
		wb[6] = b[1];
		wb[7] = b[0];
		len = 9;
		break;

	default:
		result = N_FAIL;
		break;
	}

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	if (result != N_OK)
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		return result;

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	if (!g_spi.crc_off)
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		wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
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	else
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		len -= 1;

#define NUM_SKIP_BYTES (1)
#define NUM_RSP_BYTES (2)
#define NUM_DATA_HDR_BYTES (1)
#define NUM_DATA_BYTES (4)
#define NUM_CRC_BYTES (2)
#define NUM_DUMMY_BYTES (3)
	if ((cmd == CMD_RESET) ||
	    (cmd == CMD_TERMINATE) ||
	    (cmd == CMD_REPEAT)) {
		len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
	} else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
		if (!g_spi.crc_off) {
			len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
				      + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
		} else {
			len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
				      + NUM_DUMMY_BYTES);
		}
	} else {
		len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
	}
#undef NUM_DUMMY_BYTES

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	if (len2 > ARRAY_SIZE(wb)) {
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		dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
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			 len2, ARRAY_SIZE(wb));
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		result = N_FAIL;
		return result;
	}
	/* zero spi write buffers. */
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	for (wix = len; wix < len2; wix++)
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		wb[wix] = 0;
	rix = len;

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	if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
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		dev_err(&spi->dev, "Failed cmd write, bus error...\n");
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		result = N_FAIL;
		return result;
	}

	/**
	 * Command/Control response
	 **/
	if ((cmd == CMD_RESET) ||
	    (cmd == CMD_TERMINATE) ||
	    (cmd == CMD_REPEAT)) {
		rix++;         /* skip 1 byte */
	}

	/* do { */
	rsp = rb[rix++];
	/*	if(rsp == cmd) break; */
	/* } while(&rptr[1] <= &rb[len2]); */

	if (rsp != cmd) {
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		dev_err(&spi->dev,
			"Failed cmd response, cmd (%02x), resp (%02x)\n",
			cmd, rsp);
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		result = N_FAIL;
		return result;
	}

	/**
	 * State response
	 **/
	rsp = rb[rix++];
	if (rsp != 0x00) {
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		dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
			rsp);
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		result = N_FAIL;
		return result;
	}

	if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
	    || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
		int retry;
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		/* u16 crc1, crc2; */
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		u8 crc[2];
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		/**
		 * Data Respnose header
		 **/
		retry = 100;
		do {
			/* ensure there is room in buffer later to read data and crc */
			if (rix < len2) {
				rsp = rb[rix++];
			} else {
				retry = 0;
				break;
			}
			if (((rsp >> 4) & 0xf) == 0xf)
				break;
		} while (retry--);

		if (retry <= 0) {
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			dev_err(&spi->dev,
				"Error, data read response (%02x)\n", rsp);
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			result = N_RESET;
			return result;
		}

		if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
			/**
			 * Read bytes
			 **/
			if ((rix + 3) < len2) {
				b[0] = rb[rix++];
				b[1] = rb[rix++];
				b[2] = rb[rix++];
				b[3] = rb[rix++];
			} else {
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				dev_err(&spi->dev,
					"buffer overrun when reading data.\n");
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				result = N_FAIL;
				return result;
			}

			if (!g_spi.crc_off) {
				/**
				 * Read Crc
				 **/
				if ((rix + 1) < len2) {
					crc[0] = rb[rix++];
					crc[1] = rb[rix++];
				} else {
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					dev_err(&spi->dev, "buffer overrun when reading crc.\n");
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					result = N_FAIL;
					return result;
				}
			}
		} else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
			int ix;

			/* some data may be read in response to dummy bytes. */
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			for (ix = 0; (rix < len2) && (ix < sz); )
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				b[ix++] = rb[rix++];
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			sz -= ix;

			if (sz > 0) {
				int nbytes;

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				if (sz <= (DATA_PKT_SZ - ix))
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					nbytes = sz;
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				else
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					nbytes = DATA_PKT_SZ - ix;

				/**
				 * Read bytes
				 **/
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				if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
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					dev_err(&spi->dev, "Failed data block read, bus error...\n");
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					result = N_FAIL;
					goto _error_;
				}

				/**
				 * Read Crc
				 **/
				if (!g_spi.crc_off) {
547
					if (wilc_spi_rx(wilc, crc, 2)) {
548
						dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
549
550
551
552
553
554
555
556
557
558
559
560
561
562
						result = N_FAIL;
						goto _error_;
					}
				}


				ix += nbytes;
				sz -= nbytes;
			}

			/*  if any data in left unread, then read the rest using normal DMA code.*/
			while (sz > 0) {
				int nbytes;

563
				if (sz <= DATA_PKT_SZ)
564
					nbytes = sz;
565
				else
566
567
568
569
570
571
572
573
574
575
576
577
					nbytes = DATA_PKT_SZ;

				/**
				 * read data response only on the next DMA cycles not
				 * the first DMA since data response header is already
				 * handled above for the first DMA.
				 **/
				/**
				 * Data Respnose header
				 **/
				retry = 10;
				do {
578
					if (wilc_spi_rx(wilc, &rsp, 1)) {
579
						dev_err(&spi->dev, "Failed data response read, bus error...\n");
580
581
582
583
584
585
586
587
588
589
590
591
592
593
						result = N_FAIL;
						break;
					}
					if (((rsp >> 4) & 0xf) == 0xf)
						break;
				} while (retry--);

				if (result == N_FAIL)
					break;


				/**
				 * Read bytes
				 **/
594
				if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
595
					dev_err(&spi->dev, "Failed data block read, bus error...\n");
596
597
598
599
600
601
602
603
					result = N_FAIL;
					break;
				}

				/**
				 * Read Crc
				 **/
				if (!g_spi.crc_off) {
604
					if (wilc_spi_rx(wilc, crc, 2)) {
605
						dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
606
607
608
609
610
611
612
613
614
615
616
617
618
619
						result = N_FAIL;
						break;
					}
				}

				ix += nbytes;
				sz -= nbytes;
			}
		}
	}
_error_:
	return result;
}

620
static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
621
{
622
	struct spi_device *spi = to_spi_device(wilc->dev);
623
624
	int ix, nbytes;
	int result = 1;
625
626
	u8 cmd, order, crc[2] = {0};
	/* u8 rsp; */
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654

	/**
	 *      Data
	 **/
	ix = 0;
	do {
		if (sz <= DATA_PKT_SZ)
			nbytes = sz;
		else
			nbytes = DATA_PKT_SZ;

		/**
		 *      Write command
		 **/
		cmd = 0xf0;
		if (ix == 0) {
			if (sz <= DATA_PKT_SZ)

				order = 0x3;
			else
				order = 0x1;
		} else {
			if (sz <= DATA_PKT_SZ)
				order = 0x3;
			else
				order = 0x2;
		}
		cmd |= order;
655
		if (wilc_spi_tx(wilc, &cmd, 1)) {
656
657
			dev_err(&spi->dev,
				"Failed data block cmd write, bus error...\n");
658
659
660
661
662
663
664
			result = N_FAIL;
			break;
		}

		/**
		 *      Write data
		 **/
665
		if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
666
667
			dev_err(&spi->dev,
				"Failed data block write, bus error...\n");
668
669
670
671
672
673
674
675
			result = N_FAIL;
			break;
		}

		/**
		 *      Write Crc
		 **/
		if (!g_spi.crc_off) {
676
			if (wilc_spi_tx(wilc, crc, 2)) {
677
				dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
				result = N_FAIL;
				break;
			}
		}

		/**
		 *      No need to wait for response
		 **/
		ix += nbytes;
		sz -= nbytes;
	} while (sz);


	return result;
}

/********************************************
 *
 *      Spi Internal Read/Write Function
 *
 ********************************************/

700
static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
701
{
702
	struct spi_device *spi = to_spi_device(wilc->dev);
703
704
	int result;

705
	dat = cpu_to_le32(dat);
706
707
	result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
				  0);
708
	if (result != N_OK)
709
		dev_err(&spi->dev, "Failed internal write cmd...\n");
710
711
712
713

	return result;
}

714
static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
715
{
716
	struct spi_device *spi = to_spi_device(wilc->dev);
717
718
	int result;

719
720
	result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
				  0);
721
	if (result != N_OK) {
722
		dev_err(&spi->dev, "Failed internal read cmd...\n");
723
724
725
		return 0;
	}

726
	*data = cpu_to_le32(*data);
727
728
729
730
731
732
733
734
735
736

	return 1;
}

/********************************************
 *
 *      Spi interfaces
 *
 ********************************************/

737
static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
738
{
739
	struct spi_device *spi = to_spi_device(wilc->dev);
740
	int result = N_OK;
741
742
	u8 cmd = CMD_SINGLE_WRITE;
	u8 clockless = 0;
743

744
	data = cpu_to_le32(data);
745
746
747
748
749
750
	if (addr < 0x30) {
		/* Clockless register*/
		cmd = CMD_INTERNAL_WRITE;
		clockless = 1;
	}

751
	result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
752
	if (result != N_OK)
753
		dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
754
755
756
757

	return result;
}

758
static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
759
{
760
	struct spi_device *spi = to_spi_device(wilc->dev);
761
	int result;
762
	u8 cmd = CMD_DMA_EXT_WRITE;
763
764
765
766
767
768
769

	/**
	 *      has to be greated than 4
	 **/
	if (size <= 4)
		return 0;

770
	result = spi_cmd_complete(wilc, cmd, addr, NULL, size, 0);
771
	if (result != N_OK) {
772
773
		dev_err(&spi->dev,
			"Failed cmd, write block (%08x)...\n", addr);
774
775
776
777
778
779
		return 0;
	}

	/**
	 *      Data
	 **/
780
	result = spi_data_write(wilc, buf, size);
781
	if (result != N_OK)
782
		dev_err(&spi->dev, "Failed block data write...\n");
783
784
785
786

	return 1;
}

787
static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
788
{
789
	struct spi_device *spi = to_spi_device(wilc->dev);
790
	int result = N_OK;
791
792
	u8 cmd = CMD_SINGLE_READ;
	u8 clockless = 0;
793
794

	if (addr < 0x30) {
795
		/* dev_err(&spi->dev, "***** read addr %d\n\n", addr); */
796
797
798
799
800
		/* Clockless register*/
		cmd = CMD_INTERNAL_READ;
		clockless = 1;
	}

801
	result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
802
	if (result != N_OK) {
803
		dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
804
805
806
		return 0;
	}

807
	*data = cpu_to_le32(*data);
808
809
810
811

	return 1;
}

812
static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
813
{
814
	struct spi_device *spi = to_spi_device(wilc->dev);
815
	u8 cmd = CMD_DMA_EXT_READ;
816
817
818
819
820
	int result;

	if (size <= 4)
		return 0;

821
	result = spi_cmd_complete(wilc, cmd, addr, buf, size, 0);
822
	if (result != N_OK) {
823
		dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
824
825
826
827
828
829
830
831
832
833
834
835
		return 0;
	}

	return 1;
}

/********************************************
 *
 *      Bus interfaces
 *
 ********************************************/

836
static int _wilc_spi_deinit(struct wilc *wilc)
837
838
839
840
841
842
843
{
	/**
	 *      TODO:
	 **/
	return 1;
}

844
static int wilc_spi_init(struct wilc *wilc, bool resume)
845
{
846
	struct spi_device *spi = to_spi_device(wilc->dev);
847
848
	u32 reg;
	u32 chipid;
849
850
851
852
853

	static int isinit;

	if (isinit) {

854
		if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
855
			dev_err(&spi->dev, "Fail cmd read chip id...\n");
856
857
858
859
860
			return 0;
		}
		return 1;
	}

861
	memset(&g_spi, 0, sizeof(struct wilc_spi));
862
863
864
865
866
867
868
869

	/**
	 *      configure protocol
	 **/
	g_spi.crc_off = 0;

	/* TODO: We can remove the CRC trials if there is a definite way to reset */
	/* the SPI to it's initial value. */
870
	if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
871
872
873
		/* Read failed. Try with CRC off. This might happen when module
		 * is removed but chip isn't reset*/
		g_spi.crc_off = 1;
874
		dev_err(&spi->dev, "Failed internal read protocol with CRC on, retyring with CRC off...\n");
875
		if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
876
			/* Reaad failed with both CRC on and off, something went bad */
877
878
			dev_err(&spi->dev,
				"Failed internal read protocol...\n");
879
880
881
882
883
884
885
			return 0;
		}
	}
	if (g_spi.crc_off == 0)	{
		reg &= ~0xc;    /* disable crc checking */
		reg &= ~0x70;
		reg |= (0x5 << 4);
886
		if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
887
			dev_err(&spi->dev, "[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
888
889
890
891
892
893
894
895
896
			return 0;
		}
		g_spi.crc_off = 1;
	}


	/**
	 *      make sure can read back chip id correctly
	 **/
897
	if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
898
		dev_err(&spi->dev, "Fail cmd read chip id...\n");
899
900
		return 0;
	}
901
	/* dev_err(&spi->dev, "chipid (%08x)\n", chipid); */
902
903
904
905
906
907
908
909

	g_spi.has_thrpt_enh = 1;

	isinit = 1;

	return 1;
}

910
static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
911
{
912
	struct spi_device *spi = to_spi_device(wilc->dev);
913
	int ret;
914

915
	if (g_spi.has_thrpt_enh) {
916
917
		ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
					size);
918
919
		*size = *size  & IRQ_DMA_WD_CNT_MASK;
	} else {
920
921
		u32 tmp;
		u32 byte_cnt;
922

923
924
		ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
					&byte_cnt);
925
		if (!ret) {
926
927
			dev_err(&spi->dev,
				"Failed read WILC_VMM_TO_HOST_SIZE ...\n");
928
929
930
931
932
933
934
935
936
937
938
939
940
941
			goto _fail_;
		}
		tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
		*size = tmp;
	}



_fail_:
	return ret;
}



942
static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
943
{
944
	struct spi_device *spi = to_spi_device(wilc->dev);
945
	int ret;
946

947
	if (g_spi.has_thrpt_enh) {
948
949
		ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
					int_status);
950
	} else {
951
952
		u32 tmp;
		u32 byte_cnt;
953

954
955
		ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
					&byte_cnt);
956
		if (!ret) {
957
958
			dev_err(&spi->dev,
				"Failed read WILC_VMM_TO_HOST_SIZE ...\n");
959
960
961
962
963
964
965
966
967
			goto _fail_;
		}
		tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;

		{
			int happended, j;

			j = 0;
			do {
968
				u32 irq_flags;
969
970
971

				happended = 0;

972
				wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
973
974
975
				tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);

				if (g_spi.nint > 5) {
976
977
					wilc_spi_read_reg(wilc, 0x1a94,
							  &irq_flags);
978
979
980
981
					tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
				}

				{
982
					u32 unkmown_mask;
983
984
985
986

					unkmown_mask = ~((1ul << g_spi.nint) - 1);

					if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
987
						dev_err(&spi->dev, "Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
						happended = 1;
					}
				}
				j++;
			} while (happended);
		}

		*int_status = tmp;

	}

_fail_:
	return ret;
}

1003
static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
1004
{
1005
	struct spi_device *spi = to_spi_device(wilc->dev);
1006
1007
1008
	int ret;

	if (g_spi.has_thrpt_enh) {
1009
1010
		ret = spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
					 val);
1011
	} else {
1012
		u32 flags;
1013

1014
		flags = val & (BIT(MAX_NUM_INT) - 1);
1015
1016
1017
1018
1019
1020
1021
		if (flags) {
			int i;

			ret = 1;
			for (i = 0; i < g_spi.nint; i++) {
				/* No matter what you write 1 or 0, it will clear interrupt. */
				if (flags & 1)
1022
					ret = wilc_spi_write_reg(wilc, 0x10c8 + i * 4, 1);
1023
1024
1025
1026
1027
				if (!ret)
					break;
				flags >>= 1;
			}
			if (!ret) {
1028
1029
1030
				dev_err(&spi->dev,
					"Failed wilc_spi_write_reg, set reg %x ...\n",
					0x10c8 + i * 4);
1031
1032
1033
1034
				goto _fail_;
			}
			for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
				if (flags & 1)
1035
1036
1037
					dev_err(&spi->dev,
						"Unexpected interrupt cleared %d...\n",
						i);
1038
1039
1040
1041
1042
				flags >>= 1;
			}
		}

		{
1043
			u32 tbl_ctl;
1044
1045
1046
1047

			tbl_ctl = 0;
			/* select VMM table 0 */
			if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1048
				tbl_ctl |= BIT(0);
1049
1050
			/* select VMM table 1 */
			if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1051
				tbl_ctl |= BIT(1);
1052

1053
1054
			ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL,
						 tbl_ctl);
1055
			if (!ret) {
1056
1057
				dev_err(&spi->dev,
					"fail write reg vmm_tbl_ctl...\n");
1058
1059
1060
1061
1062
1063
1064
				goto _fail_;
			}

			if ((val & EN_VMM) == EN_VMM) {
				/**
				 *      enable vmm transfer.
				 **/
1065
1066
				ret = wilc_spi_write_reg(wilc,
							 WILC_VMM_CORE_CTL, 1);
1067
				if (!ret) {
1068
					dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1069
1070
1071
1072
1073
1074
1075
1076
1077
					goto _fail_;
				}
			}
		}
	}
_fail_:
	return ret;
}

1078
static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1079
{
1080
	struct spi_device *spi = to_spi_device(wilc->dev);
1081
	u32 reg;
1082
1083
1084
	int ret, i;

	if (nint > MAX_NUM_INT) {
1085
		dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1086
1087
1088
1089
1090
1091
1092
1093
		return 0;
	}

	g_spi.nint = nint;

	/**
	 *      interrupt pin mux select
	 **/
1094
	ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1095
	if (!ret) {
1096
1097
		dev_err(&spi->dev, "Failed read reg (%08x)...\n",
			WILC_PIN_MUX_0);
1098
1099
		return 0;
	}
1100
	reg |= BIT(8);
1101
	ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1102
	if (!ret) {
1103
1104
		dev_err(&spi->dev, "Failed write reg (%08x)...\n",
			WILC_PIN_MUX_0);
1105
1106
1107
1108
1109
1110
		return 0;
	}

	/**
	 *      interrupt enable
	 **/
1111
	ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1112
	if (!ret) {
1113
1114
		dev_err(&spi->dev, "Failed read reg (%08x)...\n",
			WILC_INTR_ENABLE);
1115
1116
1117
		return 0;
	}

1118
	for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1119
		reg |= (BIT((27 + i)));
1120

1121
	ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1122
	if (!ret) {
1123
1124
		dev_err(&spi->dev, "Failed write reg (%08x)...\n",
			WILC_INTR_ENABLE);
1125
1126
1127
		return 0;
	}
	if (nint) {
1128
		ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1129
		if (!ret) {
1130
1131
			dev_err(&spi->dev, "Failed read reg (%08x)...\n",
				WILC_INTR2_ENABLE);
1132
1133
1134
			return 0;
		}

1135
		for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1136
			reg |= BIT(i);
1137

1138
		ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1139
		if (!ret) {
1140
1141
			dev_err(&spi->dev, "Failed write reg (%08x)...\n",
				WILC_INTR2_ENABLE);
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
			return 0;
		}
	}

	return 1;
}
/********************************************
 *
 *      Global spi HIF function table
 *
 ********************************************/
1153
const struct wilc_hif_func wilc_hif_spi = {
1154
	.hif_init = wilc_spi_init,
1155
1156
1157
	.hif_deinit = _wilc_spi_deinit,
	.hif_read_reg = wilc_spi_read_reg,
	.hif_write_reg = wilc_spi_write_reg,
1158
1159
	.hif_block_rx = wilc_spi_read,
	.hif_block_tx = wilc_spi_write,
1160
1161
1162
	.hif_read_int = wilc_spi_read_int,
	.hif_clear_int_ext = wilc_spi_clear_int_ext,
	.hif_read_size = wilc_spi_read_size,
1163
1164
	.hif_block_tx_ext = wilc_spi_write,
	.hif_block_rx_ext = wilc_spi_read,
1165
	.hif_sync_ext = wilc_spi_sync_ext,
1166
};