idle_book3s.S 22.2 KB
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/*
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 *  This file contains idle entry/exit functions for POWER7,
 *  POWER8 and POWER9 CPUs.
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 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ppc-opcode.h>
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#include <asm/hw_irq.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/opal.h>
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#include <asm/cpuidle.h>
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#include <asm/exception-64s.h>
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#include <asm/book3s/64/mmu-hash.h>
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#include <asm/mmu.h>
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#undef DEBUG

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/*
 * Use unused space in the interrupt stack to save and restore
 * registers for winkle support.
 */
#define _SDR1	GPR3
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#define _PTCR	GPR3
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#define _RPR	GPR4
#define _SPURR	GPR5
#define _PURR	GPR6
#define _TSCR	GPR7
#define _DSCR	GPR8
#define _AMOR	GPR9
#define _WORT	GPR10
#define _WORC	GPR11
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#define _LPCR	GPR12
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#define PSSCR_EC_ESL_MASK_SHIFTED          (PSSCR_EC | PSSCR_ESL) >> 16
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	.text

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/*
 * Used by threads before entering deep idle states. Saves SPRs
 * in interrupt stack frame
 */
save_sprs_to_stack:
	/*
	 * Note all register i.e per-core, per-subcore or per-thread is saved
	 * here since any thread in the core might wake up first
	 */
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BEGIN_FTR_SECTION
	/*
	 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
	 * SDR1 here
	 */
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	mfspr	r3,SPRN_PTCR
	std	r3,_PTCR(r1)
	mfspr	r3,SPRN_LPCR
	std	r3,_LPCR(r1)
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FTR_SECTION_ELSE
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	mfspr	r3,SPRN_SDR1
	std	r3,_SDR1(r1)
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
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	mfspr	r3,SPRN_RPR
	std	r3,_RPR(r1)
	mfspr	r3,SPRN_SPURR
	std	r3,_SPURR(r1)
	mfspr	r3,SPRN_PURR
	std	r3,_PURR(r1)
	mfspr	r3,SPRN_TSCR
	std	r3,_TSCR(r1)
	mfspr	r3,SPRN_DSCR
	std	r3,_DSCR(r1)
	mfspr	r3,SPRN_AMOR
	std	r3,_AMOR(r1)
	mfspr	r3,SPRN_WORT
	std	r3,_WORT(r1)
	mfspr	r3,SPRN_WORC
	std	r3,_WORC(r1)

	blr

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/*
 * Used by threads when the lock bit of core_idle_state is set.
 * Threads will spin in HMT_LOW until the lock bit is cleared.
 * r14 - pointer to core_idle_state
 * r15 - used to load contents of core_idle_state
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 * r9  - used as a temporary variable
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 */

core_idle_lock_held:
	HMT_LOW
3:	lwz	r15,0(r14)
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	andis.	r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
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	bne	3b
	HMT_MEDIUM
	lwarx	r15,0,r14
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	andis.	r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
	bne-	core_idle_lock_held
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	blr

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/*
 * Pass requested state in r3:
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 *	r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
 *	   - Requested STOP state in POWER9
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 *
 * To check IRQ_HAPPENED in r4
 * 	0 - don't check
 * 	1 - check
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 *
 * Address to 'rfid' to in r5
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 */
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pnv_powersave_common:
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	/* Use r3 to pass state nap/sleep/winkle */
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	/* NAP is a state loss, we create a regs frame on the
	 * stack, fill it up with the state we care about and
	 * stick a pointer to it in PACAR1. We really only
	 * need to save PC, some CR bits and the NV GPRs,
	 * but for now an interrupt frame will do.
	 */
	mflr	r0
	std	r0,16(r1)
	stdu	r1,-INT_FRAME_SIZE(r1)
	std	r0,_LINK(r1)
	std	r0,_NIP(r1)

	/* Hard disable interrupts */
	mfmsr	r9
	rldicl	r9,r9,48,1
	rotldi	r9,r9,16
	mtmsrd	r9,1			/* hard-disable interrupts */
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	/* Check if something happened while soft-disabled */
	lbz	r0,PACAIRQHAPPENED(r13)
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	andi.	r0,r0,~PACA_IRQ_HARD_DIS@l
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	beq	1f
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	cmpwi	cr0,r4,0
	beq	1f
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	addi	r1,r1,INT_FRAME_SIZE
	ld	r0,16(r1)
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	li	r3,0			/* Return 0 (no nap) */
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	mtlr	r0
	blr

1:	/* We mark irqs hard disabled as this is the state we'll
	 * be in when returning and we need to tell arch_local_irq_restore()
	 * about it
	 */
	li	r0,PACA_IRQ_HARD_DIS
	stb	r0,PACAIRQHAPPENED(r13)

	/* We haven't lost state ... yet */
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	li	r0,0
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	stb	r0,PACA_NAPSTATELOST(r13)
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	/* Continue saving state */
	SAVE_GPR(2, r1)
	SAVE_NVGPRS(r1)
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	mfcr	r4
	std	r4,_CCR(r1)
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	std	r9,_MSR(r1)
	std	r1,PACAR1(r13)

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	/*
	 * Go to real mode to do the nap, as required by the architecture.
	 * Also, we need to be in real mode before setting hwthread_state,
	 * because as soon as we do that, another thread can switch
	 * the MMU context to the guest.
	 */
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	LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
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	li	r6, MSR_RI
	andc	r6, r9, r6
	mtmsrd	r6, 1		/* clear RI before setting SRR0/1 */
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	mtspr	SPRN_SRR0, r5
	mtspr	SPRN_SRR1, r7
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	rfid

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	.globl pnv_enter_arch207_idle_mode
pnv_enter_arch207_idle_mode:
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	/* Tell KVM we're entering idle */
	li	r4,KVM_HWTHREAD_IN_IDLE
	/******************************************************/
	/*  N O T E   W E L L    ! ! !    N O T E   W E L L   */
	/* The following store to HSTATE_HWTHREAD_STATE(r13)  */
	/* MUST occur in real mode, i.e. with the MMU off,    */
	/* and the MMU must stay off until we clear this flag */
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	/* and test HSTATE_HWTHREAD_REQ(r13) in               */
	/* pnv_powersave_wakeup in this file.                 */
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	/* The reason is that another thread can switch the   */
	/* MMU to a guest context whenever this flag is set   */
	/* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on,    */
	/* that would potentially cause this thread to start  */
	/* executing instructions from guest memory in        */
	/* hypervisor mode, leading to a host crash or data   */
	/* corruption, or worse.                              */
	/******************************************************/
	stb	r4,HSTATE_HWTHREAD_STATE(r13)
#endif
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	stb	r3,PACA_THREAD_IDLE_STATE(r13)
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	cmpwi	cr3,r3,PNV_THREAD_SLEEP
	bge	cr3,2f
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	IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
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	/* No return */
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2:
	/* Sleep or winkle */
	lbz	r7,PACA_THREAD_MASK(r13)
	ld	r14,PACA_CORE_IDLE_STATE_PTR(r13)
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	li	r5,0
	beq	cr3,3f
	lis	r5,PNV_CORE_IDLE_WINKLE_COUNT@h
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lwarx_loop1:
	lwarx	r15,0,r14
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	andis.	r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
	bnel-	core_idle_lock_held
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	add	r15,r15,r5			/* Add if winkle */
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	andc	r15,r15,r7			/* Clear thread bit */

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	andi.	r9,r15,PNV_CORE_IDLE_THREAD_BITS
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/*
 * If cr0 = 0, then current thread is the last thread of the core entering
 * sleep. Last thread needs to execute the hardware bug workaround code if
 * required by the platform.
 * Make the workaround call unconditionally here. The below branch call is
 * patched out when the idle states are discovered if the platform does not
 * require it.
 */
.global pnv_fastsleep_workaround_at_entry
pnv_fastsleep_workaround_at_entry:
	beq	fastsleep_workaround_at_entry

	stwcx.	r15,0,r14
	bne-	lwarx_loop1
	isync

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common_enter: /* common code for all the threads entering sleep or winkle */
	bgt	cr3,enter_winkle
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	IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
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fastsleep_workaround_at_entry:
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	oris	r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
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	stwcx.	r15,0,r14
	bne-	lwarx_loop1
	isync

	/* Fast sleep workaround */
	li	r3,1
	li	r4,1
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	bl	opal_config_cpu_idle_state
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	/* Unlock */
	xoris	r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
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	lwsync
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	stw	r15,0(r14)
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	b	common_enter

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enter_winkle:
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	bl	save_sprs_to_stack

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	IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
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/*
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 * r3 - PSSCR value corresponding to the requested stop state.
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 */
power_enter_stop:
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	/* Tell KVM we're entering idle */
	li	r4,KVM_HWTHREAD_IN_IDLE
	/* DO THIS IN REAL MODE!  See comment above. */
	stb	r4,HSTATE_HWTHREAD_STATE(r13)
#endif
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/*
 * Check if we are executing the lite variant with ESL=EC=0
 */
	andis.   r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
	clrldi   r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
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	bne	 .Lhandle_esl_ec_set
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	IDLE_STATE_ENTER_SEQ(PPC_STOP)
	li	r3,0  /* Since we didn't lose state, return 0 */
	b 	pnv_wakeup_noloss
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.Lhandle_esl_ec_set:
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/*
 * Check if the requested state is a deep idle state.
 */
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	LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
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	ld	r4,ADDROFF(pnv_first_deep_stop_state)(r5)
	cmpd	r3,r4
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	bge	.Lhandle_deep_stop
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	IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
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.Lhandle_deep_stop:
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/*
 * Entering deep idle state.
 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
 * stack and enter stop
 */
	lbz     r7,PACA_THREAD_MASK(r13)
	ld      r14,PACA_CORE_IDLE_STATE_PTR(r13)

lwarx_loop_stop:
	lwarx   r15,0,r14
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	andis.	r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
	bnel-	core_idle_lock_held
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	andc    r15,r15,r7                      /* Clear thread bit */

	stwcx.  r15,0,r14
	bne-    lwarx_loop_stop
	isync

	bl	save_sprs_to_stack

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	IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP)
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_GLOBAL(power7_idle)
	/* Now check if user or arch enabled NAP mode */
	LOAD_REG_ADDRBASE(r3,powersave_nap)
	lwz	r4,ADDROFF(powersave_nap)(r3)
	cmpwi	0,r4,0
	beqlr
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	li	r3, 1
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	/* fall through */

_GLOBAL(power7_nap)
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	mr	r4,r3
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	li	r3,PNV_THREAD_NAP
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	LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
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	b	pnv_powersave_common
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	/* No return */

_GLOBAL(power7_sleep)
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	li	r3,PNV_THREAD_SLEEP
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	li	r4,1
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	LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
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	b	pnv_powersave_common
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	/* No return */
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_GLOBAL(power7_winkle)
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	li	r3,PNV_THREAD_WINKLE
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	li	r4,1
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	LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
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	b	pnv_powersave_common
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	/* No return */

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#define CHECK_HMI_INTERRUPT						\
	mfspr	r0,SPRN_SRR1;						\
BEGIN_FTR_SECTION_NESTED(66);						\
	rlwinm	r0,r0,45-31,0xf;  /* extract wake reason field (P8) */	\
FTR_SECTION_ELSE_NESTED(66);						\
	rlwinm	r0,r0,45-31,0xe;  /* P7 wake reason field is 3 bits */	\
ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66);		\
	cmpwi	r0,0xa;			/* Hypervisor maintenance ? */	\
	bne	20f;							\
	/* Invoke opal call to handle hmi */				\
	ld	r2,PACATOC(r13);					\
	ld	r1,PACAR1(r13);						\
	std	r3,ORIG_GPR3(r1);	/* Save original r3 */		\
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	li	r3,0;			/* NULL argument */		\
	bl	hmi_exception_realmode;					\
	nop;								\
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	ld	r3,ORIG_GPR3(r1);	/* Restore original r3 */	\
20:	nop;

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/*
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 * r3 - The PSSCR value corresponding to the stop state.
 * r4 - The PSSCR mask corrresonding to the stop state.
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 */
_GLOBAL(power9_idle_stop)
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	mfspr   r5,SPRN_PSSCR
	andc    r5,r5,r4
	or      r3,r3,r5
	mtspr 	SPRN_PSSCR,r3
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	LOAD_REG_ADDR(r5,power_enter_stop)
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	li	r4,1
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	b	pnv_powersave_common
	/* No return */
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/*
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 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
 * HSPRG0 will be set to the HSPRG0 value of one of the
 * threads in this core. Thus the value we have in r13
 * may not be this thread's paca pointer.
 *
 * Fortunately, the TIR remains invariant. Since this thread's
 * paca pointer is recorded in all its sibling's paca, we can
 * correctly recover this thread's paca pointer if we
 * know the index of this thread in the core.
 *
 * This index can be obtained from the TIR.
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 *
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 * i.e, thread's position in the core = TIR.
 * If this value is i, then this thread's paca is
 * paca->thread_sibling_pacas[i].
 */
power9_dd1_recover_paca:
	mfspr	r4, SPRN_TIR
	/*
	 * Since each entry in thread_sibling_pacas is 8 bytes
	 * we need to left-shift by 3 bits. Thus r4 = i * 8
	 */
	sldi	r4, r4, 3
	/* Get &paca->thread_sibling_pacas[0] in r5 */
	ld	r5, PACA_SIBLING_PACA_PTRS(r13)
	/* Load paca->thread_sibling_pacas[i] into r13 */
	ldx	r13, r4, r5
	SET_PACA(r13)
	/*
	 * Indicate that we have lost NVGPR state
	 * which needs to be restored from the stack.
	 */
	li	r3, 1
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	stb	r3,PACA_NAPSTATELOST(r13)
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	blr

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/*
 * Called from machine check handler for powersave wakeups.
 * Low level machine check processing has already been done. Now just
 * go through the wake up path to get everything in order.
 *
 * r3 - The original SRR1 value.
 * Original SRR[01] have been clobbered.
 * MSR_RI is clear.
 */
.global pnv_powersave_wakeup_mce
pnv_powersave_wakeup_mce:
	/* Set cr3 for pnv_powersave_wakeup */
	rlwinm	r11,r3,47-31,30,31
	cmpwi	cr3,r11,2

	/*
	 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
	 * reason into SRR1, which allows reuse of the system reset wakeup
	 * code without being mistaken for another type of wakeup.
	 */
	oris	r3,r3,SRR1_WAKEMCE_RESVD@h
	mtspr	SPRN_SRR1,r3

	b	pnv_powersave_wakeup

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/*
 * Called from reset vector for powersave wakeups.
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 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
 */
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.global pnv_powersave_wakeup
pnv_powersave_wakeup:
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	ld	r2, PACATOC(r13)

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BEGIN_FTR_SECTION
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BEGIN_FTR_SECTION_NESTED(70)
	bl	power9_dd1_recover_paca
END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
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	bl	pnv_restore_hyp_resource_arch300
FTR_SECTION_ELSE
	bl	pnv_restore_hyp_resource_arch207
ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
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	li	r0,PNV_THREAD_RUNNING
	stb	r0,PACA_THREAD_IDLE_STATE(r13)	/* Clear thread state */

#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	li	r0,KVM_HWTHREAD_IN_KERNEL
	stb	r0,HSTATE_HWTHREAD_STATE(r13)
	/* Order setting hwthread_state vs. testing hwthread_req */
	sync
	lbz	r0,HSTATE_HWTHREAD_REQ(r13)
	cmpwi	r0,0
	beq	1f
	b	kvm_start_guest
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#endif

	/* Return SRR1 from power7_nap() */
	mfspr	r3,SPRN_SRR1
	blt	cr3,pnv_wakeup_noloss
	b	pnv_wakeup_loss

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/*
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 * Check whether we have woken up with hypervisor state loss.
 * If yes, restore hypervisor state and return back to link.
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 *
 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
 */
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pnv_restore_hyp_resource_arch300:
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	/*
	 * POWER ISA 3. Use PSSCR to determine if we
	 * are waking up from deep idle state
	 */
	LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
	ld	r4,ADDROFF(pnv_first_deep_stop_state)(r5)

	mfspr	r5,SPRN_PSSCR
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	/*
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	 * 0-3 bits correspond to Power-Saving Level Status
	 * which indicates the idle state we are waking up from
	 */
	rldicl  r5,r5,4,60
	cmpd	cr4,r5,r4
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	bge	cr4,pnv_wakeup_tb_loss /* returns to caller */
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	blr	/* Waking up without hypervisor state loss. */
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/* Same calling convention as arch300 */
pnv_restore_hyp_resource_arch207:
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	/*
	 * POWER ISA 2.07 or less.
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	 * Check if we slept with sleep or winkle.
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	 */
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	lbz	r4,PACA_THREAD_IDLE_STATE(r13)
	cmpwi	cr2,r4,PNV_THREAD_NAP
	bgt	cr2,pnv_wakeup_tb_loss	/* Either sleep or Winkle */
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	/*
	 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
	 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
	 * indicates we are waking with hypervisor state loss from nap.
	 */
	bgt	cr3,.

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	blr	/* Waking up without hypervisor state loss */
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/*
 * Called if waking up from idle state which can cause either partial or
 * complete hyp state loss.
 * In POWER8, called if waking up from fastsleep or winkle
 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
 *
 * r13 - PACA
 * cr3 - gt if waking up with partial/complete hypervisor state loss
539
540
 *
 * If ISA300:
541
 * cr4 - gt or eq if waking up from complete hypervisor state loss.
542
543
544
 *
 * If ISA207:
 * r4 - PACA_THREAD_IDLE_STATE
545
 */
546
pnv_wakeup_tb_loss:
547
	ld	r1,PACAR1(r13)
548
	/*
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
	 * Before entering any idle state, the NVGPRs are saved in the stack.
	 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
	 * NVGPRs are restored. If we are here, it is likely that state is lost,
	 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
	 * here are the same as the test to restore NVGPRS:
	 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
	 * and SRR1 test for restoring NVGPRs.
	 *
	 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
	 * guarantee they will always be restored. This might be tightened
	 * with careful reading of specs (particularly for ISA300) but this
	 * is already a slow wakeup path and it's simpler to be safe.
	 */
	li	r0,1
	stb	r0,PACA_NAPSTATELOST(r13)

	/*
566
	 *
567
	 * Save SRR1 and LR in NVGPRs as they might be clobbered in
568
	 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
569
570
571
	 * to determine the wakeup reason if we branch to kvm_start_guest. LR
	 * is required to return back to reset vector after hypervisor state
	 * restore is complete.
572
	 */
573
	mr	r18,r4
574
	mflr	r17
575
	mfspr	r16,SPRN_SRR1
576
577
578
BEGIN_FTR_SECTION
	CHECK_HMI_INTERRUPT
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
579
580

	ld	r14,PACA_CORE_IDLE_STATE_PTR(r13)
581
582
	lbz	r7,PACA_THREAD_MASK(r13)

583
	/*
584
585
	 * Take the core lock to synchronize against other threads.
	 *
586
587
588
589
590
591
592
	 * Lock bit is set in one of the 2 cases-
	 * a. In the sleep/winkle enter path, the last thread is executing
	 * fastsleep workaround code.
	 * b. In the wake up path, another thread is executing fastsleep
	 * workaround undo code or resyncing timebase or restoring context
	 * In either case loop until the lock bit is cleared.
	 */
593
594
595
1:
	lwarx	r15,0,r14
	andis.	r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
596
	bnel-	core_idle_lock_held
597
598
599
600
	oris	r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
	stwcx.	r15,0,r14
	bne-	1b
	isync
601

602
603
	andi.	r9,r15,PNV_CORE_IDLE_THREAD_BITS
	cmpwi	cr2,r9,0
604
605
606

	/*
	 * At this stage
607
608
	 * cr2 - eq if first thread to wakeup in core
	 * cr3-  gt if waking up with partial/complete hypervisor state loss
609
	 * ISA300:
610
	 * cr4 - gt or eq if waking up from complete hypervisor state loss.
611
612
	 */

613
BEGIN_FTR_SECTION
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
	/*
	 * Were we in winkle?
	 * If yes, check if all threads were in winkle, decrement our
	 * winkle count, set all thread winkle bits if all were in winkle.
	 * Check if our thread has a winkle bit set, and set cr4 accordingly
	 * (to match ISA300, above). Pseudo-code for core idle state
	 * transitions for ISA207 is as follows (everything happens atomically
	 * due to store conditional and/or lock bit):
	 *
	 * nap_idle() { }
	 * nap_wake() { }
	 *
	 * sleep_idle()
	 * {
	 *	core_idle_state &= ~thread_in_core
	 * }
	 *
	 * sleep_wake()
	 * {
	 *     bool first_in_core, first_in_subcore;
	 *
	 *     first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
	 *     first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
	 *
	 *     core_idle_state |= thread_in_core;
	 * }
	 *
	 * winkle_idle()
	 * {
	 *	core_idle_state &= ~thread_in_core;
	 *	core_idle_state += 1 << WINKLE_COUNT_SHIFT;
	 * }
	 *
	 * winkle_wake()
	 * {
	 *     bool first_in_core, first_in_subcore, winkle_state_lost;
	 *
	 *     first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
	 *     first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
	 *
	 *     core_idle_state |= thread_in_core;
	 *
	 *     if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
	 *         core_idle_state |= THREAD_WINKLE_BITS;
	 *     core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
	 *
	 *     winkle_state_lost = core_idle_state &
	 *				(thread_in_core << WINKLE_THREAD_SHIFT);
	 *     core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
	 * }
	 *
	 */
	cmpwi	r18,PNV_THREAD_WINKLE
	bne	2f
	andis.	r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
	subis	r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
	beq	2f
	ori	r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
2:
	/* Shift thread bit to winkle mask, then test if this thread is set,
	 * and remove it from the winkle bits */
	slwi	r8,r7,8
	and	r8,r8,r15
	andc	r15,r15,r8
	cmpwi	cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */

680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
	lbz	r4,PACA_SUBCORE_SIBLING_MASK(r13)
	and	r4,r4,r15
	cmpwi	r4,0	/* Check if first in subcore */

	or	r15,r15,r7		/* Set thread bit */
	beq	first_thread_in_subcore
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)

	or	r15,r15,r7		/* Set thread bit */
	beq	cr2,first_thread_in_core

	/* Not first thread in core or subcore to wake up */
	b	clear_lock

first_thread_in_subcore:
695
696
697
698
	/*
	 * If waking up from sleep, subcore state is not lost. Hence
	 * skip subcore state restore
	 */
699
	blt	cr4,subcore_state_restored
700
701
702
703

	/* Restore per-subcore state */
	ld      r4,_SDR1(r1)
	mtspr   SPRN_SDR1,r4
704

705
706
707
708
709
710
711
712
713
714
715
716
717
718
	ld      r4,_RPR(r1)
	mtspr   SPRN_RPR,r4
	ld	r4,_AMOR(r1)
	mtspr	SPRN_AMOR,r4

subcore_state_restored:
	/*
	 * Check if the thread is also the first thread in the core. If not,
	 * skip to clear_lock.
	 */
	bne	cr2,clear_lock

first_thread_in_core:

719
	/*
720
721
	 * First thread in the core waking up from any state which can cause
	 * partial or complete hypervisor state loss. It needs to
722
723
	 * call the fastsleep workaround code if the platform requires it.
	 * Call it unconditionally here. The below branch instruction will
724
725
726
	 * be patched out if the platform does not have fastsleep or does not
	 * require the workaround. Patching will be performed during the
	 * discovery of idle-states.
727
728
729
730
731
732
	 */
.global pnv_fastsleep_workaround_at_exit
pnv_fastsleep_workaround_at_exit:
	b	fastsleep_workaround_at_exit

timebase_resync:
733
734
735
736
	/*
	 * Use cr3 which indicates that we are waking up with atleast partial
	 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
	 */
737
	ble	cr3,.Ltb_resynced
738
	/* Time base re-sync */
739
	bl	opal_resync_timebase;
740
	/*
741
742
	 * If waking up from sleep (POWER8), per core state
	 * is not lost, skip to clear_lock.
743
	 */
744
.Ltb_resynced:
745
	blt	cr4,clear_lock
746

747
748
749
750
751
752
753
754
755
756
757
758
	/*
	 * First thread in the core to wake up and its waking up with
	 * complete hypervisor state loss. Restore per core hypervisor
	 * state.
	 */
BEGIN_FTR_SECTION
	ld	r4,_PTCR(r1)
	mtspr	SPRN_PTCR,r4
	ld	r4,_RPR(r1)
	mtspr	SPRN_RPR,r4
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)

759
760
761
762
763
	ld	r4,_TSCR(r1)
	mtspr	SPRN_TSCR,r4
	ld	r4,_WORC(r1)
	mtspr	SPRN_WORC,r4

764
clear_lock:
765
	xoris	r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
766
767
768
769
	lwsync
	stw	r15,0(r14)

common_exit:
770
771
772
773
774
775
	/*
	 * Common to all threads.
	 *
	 * If waking up from sleep, hypervisor state is not lost. Hence
	 * skip hypervisor state restore.
	 */
776
	blt	cr4,hypervisor_state_restored
777
778
779

	/* Waking up from winkle */

780
781
BEGIN_MMU_FTR_SECTION
	b	no_segments
782
END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
783
784
785
786
787
788
789
790
791
792
793
794
795
	/* Restore SLB  from PACA */
	ld	r8,PACA_SLBSHADOWPTR(r13)

	.rept	SLB_NUM_BOLTED
	li	r3, SLBSHADOW_SAVEAREA
	LDX_BE	r5, r8, r3
	addi	r3, r3, 8
	LDX_BE	r6, r8, r3
	andis.	r7,r5,SLB_ESID_V@h
	beq	1f
	slbmte	r6,r5
1:	addi	r8,r8,16
	.endr
796
797
798
no_segments:

	/* Restore per thread state */
799
800
801
802
803
804
805
806
807
808

	ld	r4,_SPURR(r1)
	mtspr	SPRN_SPURR,r4
	ld	r4,_PURR(r1)
	mtspr	SPRN_PURR,r4
	ld	r4,_DSCR(r1)
	mtspr	SPRN_DSCR,r4
	ld	r4,_WORT(r1)
	mtspr	SPRN_WORT,r4

809
810
811
812
813
814
815
816
817
818
	/* Call cur_cpu_spec->cpu_restore() */
	LOAD_REG_ADDR(r4, cur_cpu_spec)
	ld	r4,0(r4)
	ld	r12,CPU_SPEC_RESTORE(r4)
#ifdef PPC64_ELF_ABI_v1
	ld	r12,0(r12)
#endif
	mtctr	r12
	bctrl

819
820
821
822
BEGIN_FTR_SECTION
	ld	r4,_LPCR(r1)
	mtspr	SPRN_LPCR,r4
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
823
824
hypervisor_state_restored:

825
	mtspr	SPRN_SRR1,r16
826
	mtlr	r17
827
	blr		/* return to pnv_powersave_wakeup */
828

829
830
831
fastsleep_workaround_at_exit:
	li	r3,1
	li	r4,0
832
	bl	opal_config_cpu_idle_state
833
834
	b	timebase_resync

835
836
837
838
/*
 * R3 here contains the value that will be returned to the caller
 * of power7_nap.
 */
839
840
.global pnv_wakeup_loss
pnv_wakeup_loss:
841
	ld	r1,PACAR1(r13)
842
843
844
BEGIN_FTR_SECTION
	CHECK_HMI_INTERRUPT
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
845
846
	REST_NVGPRS(r1)
	REST_GPR(2, r1)
847
	ld	r6,_CCR(r1)
848
849
850
	ld	r4,_MSR(r1)
	ld	r5,_NIP(r1)
	addi	r1,r1,INT_FRAME_SIZE
851
	mtcr	r6
852
853
854
855
	mtspr	SPRN_SRR1,r4
	mtspr	SPRN_SRR0,r5
	rfid

856
857
858
859
/*
 * R3 here contains the value that will be returned to the caller
 * of power7_nap.
 */
860
pnv_wakeup_noloss:
861
862
	lbz	r0,PACA_NAPSTATELOST(r13)
	cmpwi	r0,0
863
	bne	pnv_wakeup_loss
864
865
866
BEGIN_FTR_SECTION
	CHECK_HMI_INTERRUPT
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
867
	ld	r1,PACAR1(r13)
868
	ld	r6,_CCR(r1)
869
870
871
	ld	r4,_MSR(r1)
	ld	r5,_NIP(r1)
	addi	r1,r1,INT_FRAME_SIZE
872
	mtcr	r6
873
874
875
	mtspr	SPRN_SRR1,r4
	mtspr	SPRN_SRR0,r5
	rfid