Commit 19af5cdb authored by Martin Olsson's avatar Martin Olsson Committed by Jiri Kosina
Browse files

trivial: fix typo milisecond/millisecond for documentation and source comments.


Signed-off-by: default avatarMartin Olsson <martin@minimum.se>
Signed-off-by: default avatarJiri Kosina <jkosina@suse.cz>
parent 98a1708d
......@@ -698,8 +698,8 @@ very often is not. Abundant use of the inline keyword leads to a much bigger
kernel, which in turn slows the system as a whole down, due to a bigger
icache footprint for the CPU and simply because there is less memory
available for the pagecache. Just think about it; a pagecache miss causes a
disk seek, which easily takes 5 miliseconds. There are a LOT of cpu cycles
that can go into these 5 miliseconds.
disk seek, which easily takes 5 milliseconds. There are a LOT of cpu cycles
that can go into these 5 milliseconds.
A reasonable rule of thumb is to not put inline at functions that have more
than 3 lines of code in them. An exception to this rule are the cases where
......
......@@ -577,7 +577,7 @@ static ide_startstop_t ide_transfer_pc(ide_drive_t *drive)
/*
* If necessary schedule the packet transfer to occur 'timeout'
* miliseconds later in ide_delayed_transfer_pc() after the
* milliseconds later in ide_delayed_transfer_pc() after the
* device says it's ready for a packet.
*/
if (drive->atapi_flags & IDE_AFLAG_ZIP_DRIVE) {
......
......@@ -502,7 +502,7 @@ dsp_control_req(struct dsp *dsp, struct mISDNhead *hh, struct sk_buff *skb)
break;
}
dsp->cmx_delay = (*((int *)data)) << 3;
/* miliseconds to samples */
/* milliseconds to samples */
if (dsp->cmx_delay >= (CMX_BUFF_HALF>>1))
/* clip to half of maximum usable buffer
(half of half buffer) */
......
......@@ -514,7 +514,7 @@ enum ipg_regs {
#define IPG_DMALIST_ALIGN_PAD 0x07
#define IPG_MULTICAST_HASHTABLE_SIZE 0x40
/* Number of miliseconds to wait after issuing a software reset.
/* Number of milliseconds to wait after issuing a software reset.
* 0x05 <= IPG_AC_RESETWAIT to account for proper 10Mbps operation.
*/
#define IPG_AC_RESETWAIT 0x05
......
......@@ -116,7 +116,7 @@ static void zfcp_wka_port_put(struct zfcp_wka_port *wka_port)
{
if (atomic_dec_return(&wka_port->refcount) != 0)
return;
/* wait 10 miliseconds, other reqs might pop in */
/* wait 10 milliseconds, other reqs might pop in */
schedule_delayed_work(&wka_port->work, HZ / 100);
}
......
......@@ -342,7 +342,7 @@ uLONG osdGetThreadID(void);
/* wakes up the specifed thread */
void osdWakeThread(uLONG);
/* osd sleep for x miliseconds */
/* osd sleep for x milliseconds */
void osdSleep(uLONG);
#define DPT_THREAD_PRIORITY_LOWEST 0x00
......
......@@ -102,7 +102,7 @@ struct edgeport_port {
__u8 shadow_mcr;
__u8 shadow_lsr;
__u8 lsr_mask;
__u32 ump_read_timeout; /* Number of miliseconds the UMP will
__u32 ump_read_timeout; /* Number of milliseconds the UMP will
wait without data before completing
a read short */
int baud_rate;
......
......@@ -367,7 +367,7 @@ static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *x
unsigned int port;
const unsigned char *image;
/* XILINX reset (wait at least 1 milisecond between reset on and off). */
/* XILINX reset (wait at least 1 millisecond between reset on and off). */
vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK);
vx_inl(chip, CNTRL);
msleep(10);
......
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