Commit 6472f1a3 authored by Will Deacon's avatar Will Deacon Committed by Greg Kroah-Hartman
Browse files

arm64: entry: Hook up entry trampoline to exception vectors

Commit 4bf3286d


Hook up the entry trampoline to our exception vectors so that all
exceptions from and returns to EL0 go via the trampoline, which swizzles
the vector base register accordingly. Transitioning to and from the
kernel clobbers x30, so we use tpidrro_el0 and far_el1 as scratch
registers for native tasks.
Reviewed-by: default avatarMark Rutland <>
Tested-by: default avatarLaura Abbott <>
Tested-by: default avatarShanker Donthineni <>
Signed-off-by: default avatarWill Deacon <>
Signed-off-by: default avatarArd Biesheuvel <>
Signed-off-by: default avatarGreg Kroah-Hartman <>
parent 86200f21
......@@ -73,6 +73,17 @@
.macro kernel_ventry, el, label, regsize = 64
.align 7
.if \el == 0
.if \regsize == 64
mrs x30, tpidrro_el0
msr tpidrro_el0, xzr
mov x30, xzr
sub sp, sp, #S_FRAME_SIZE
......@@ -119,6 +130,11 @@
b el\()\el\()_\label
.macro tramp_alias, dst, sym
mov_q \dst, TRAMP_VALIAS
add \dst, \dst, #(\sym - .entry.tramp.text)
.macro kernel_entry, el, regsize = 64
.if \regsize == 32
mov w0, w0 // zero upper 32 bits of x0
......@@ -269,18 +285,20 @@ alternative_else_nop_endif
.if \el == 0
ldr x23, [sp, #S_SP] // load return stack pointer
msr sp_el0, x23
tst x22, #PSR_MODE32_BIT // native task?
b.eq 3f
#ifdef CONFIG_ARM64_ERRATUM_845719
alternative_if ARM64_WORKAROUND_845719
tbz x22, #4, 1f
mrs x29, contextidr_el1
msr contextidr_el1, x29
msr contextidr_el1, xzr
msr elr_el1, x21 // set up the return data
......@@ -302,7 +320,22 @@ alternative_else_nop_endif
ldp x28, x29, [sp, #16 * 14]
ldr lr, [sp, #S_LR]
add sp, sp, #S_FRAME_SIZE // restore sp
eret // return to kernel
.if \el == 0
bne 4f
msr far_el1, x30
tramp_alias x30, tramp_exit_native
br x30
tramp_alias x30, tramp_exit_compat
br x30
.macro irq_stack_entry
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