Commit d1ef2890 authored by Linus Walleij's avatar Linus Walleij Committed by Bjorn Helgaas
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PCI: faraday: Add clock bindings

The Faraday FTPCI100 controller has two clock ports, PCLK and PCICLK.  Add
bindings for these two clocks so we can assign them in the device tree.
Signed-off-by: default avatarLinus Walleij <>
Signed-off-by: default avatarBjorn Helgaas <>
Acked-by: default avatarRob Herring <>
parent 769b461f
......@@ -30,6 +30,13 @@ Mandatory properties:
128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
Optional properties:
- clocks: when present, this should contain the peripheral clock (PCLK) and the
PCI clock (PCICLK). If these are not present, they are assumed to be
hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
- clock-names: when present, this should contain "PCLK" for the peripheral
clock and "PCICLK" for the PCI-side clock.
Mandatory subnodes:
- For "faraday,ftpci100" a node representing the interrupt-controller inside the
host bridge is mandatory. It has the following mandatory properties:
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