Commit ef2c55e5 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'sh/for-2.6.33' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

* 'sh/for-2.6.33' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
  sh: Ensure all PG_dcache_dirty pages are written back.
  sh: mach-ecovec24: setup.c detailed correction
  serial: sh-sci: Convert tremaining ctrl_xxx I/O routines to __raw_xxx.
  serial: sh-sci: earlyprintk zero uartclk fix
  sh: Only use bl bit toggling for sleeping idle.
  sh: Restore bl bit toggling in idle loop.
  sh: Fix up MAX_DMA_CHANNELS definition when DMA is disabled.
  sh: dmaengine support for SH7785
  sh: dmaengine support for sh7724.
parents 43104716 f34548cb
......@@ -128,8 +128,6 @@ static struct platform_device nor_flash_device = {
/* SH Eth */
#define SH_ETH_ADDR (0xA4600000)
#define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
#define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
static struct resource sh_eth_resources[] = {
[0] = {
.start = SH_ETH_ADDR,
......@@ -509,6 +507,7 @@ static struct platform_device sdhi1_device = {
#else
/* MMC SPI */
static int mmc_spi_get_ro(struct device *dev)
{
return gpio_get_value(GPIO_PTY6);
......@@ -542,6 +541,7 @@ static struct spi_board_info spi_bus[] = {
},
};
/* MSIOF0 */
static struct sh_msiof_spi_info msiof0_data = {
.num_chipselect = 1,
};
......
......@@ -19,9 +19,11 @@
#include <asm-generic/dma.h>
#ifdef CONFIG_NR_DMA_CHANNELS
# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
#elif defined(CONFIG_NR_ONCHIP_DMA_CHANNELS)
# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
#else
# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
# define MAX_DMA_CHANNELS 0
#endif
/*
......
......@@ -19,10 +19,10 @@
#elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \
defined(CONFIG_CPU_SUBTYPE_SH7724)
#define DMTE0_IRQ 48 /* DMAC0A*/
#define DMTE4_IRQ 40 /* DMAC0B */
#define DMTE6_IRQ 42
#define DMTE8_IRQ 76 /* DMAC1A */
#define DMTE9_IRQ 77
#define DMTE4_IRQ 76 /* DMAC0B */
#define DMTE6_IRQ 40
#define DMTE8_IRQ 42 /* DMAC1A */
#define DMTE9_IRQ 43
#define DMTE10_IRQ 72 /* DMAC1B */
#define DMTE11_IRQ 73
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
......
......@@ -23,9 +23,23 @@
#include <linux/notifier.h>
#include <asm/suspend.h>
#include <asm/clock.h>
#include <asm/dma-sh.h>
#include <asm/mmzone.h>
#include <cpu/sh7724.h>
/* DMA */
static struct sh_dmae_pdata dma_platform_data = {
.mode = SHDMA_DMAOR1,
};
static struct platform_device dma_device = {
.name = "sh-dma-engine",
.id = -1,
.dev = {
.platform_data = &dma_platform_data,
},
};
/* Serial */
static struct plat_sci_port scif0_platform_data = {
.mapbase = 0xffe00000,
......@@ -649,6 +663,7 @@ static struct platform_device *sh7724_devices[] __initdata = {
&tmu3_device,
&tmu4_device,
&tmu5_device,
&dma_device,
&rtc_device,
&iic0_device,
&iic1_device,
......
......@@ -14,6 +14,7 @@
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/sh_timer.h>
#include <asm/dma-sh.h>
#include <asm/mmzone.h>
static struct plat_sci_port scif0_platform_data = {
......@@ -294,6 +295,18 @@ static struct platform_device tmu5_device = {
.num_resources = ARRAY_SIZE(tmu5_resources),
};
static struct sh_dmae_pdata dma_platform_data = {
.mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1),
};
static struct platform_device dma_device = {
.name = "sh-dma-engine",
.id = -1,
.dev = {
.platform_data = &dma_platform_data,
},
};
static struct platform_device *sh7785_devices[] __initdata = {
&scif0_device,
&scif1_device,
......@@ -307,6 +320,7 @@ static struct platform_device *sh7785_devices[] __initdata = {
&tmu3_device,
&tmu4_device,
&tmu5_device,
&dma_device,
};
static int __init sh7785_devices_setup(void)
......
......@@ -62,6 +62,7 @@ void default_idle(void)
clear_thread_flag(TIF_POLLING_NRFLAG);
smp_mb__after_clear_bit();
set_bl_bit();
if (!need_resched()) {
local_irq_enable();
cpu_sleep();
......@@ -69,6 +70,7 @@ void default_idle(void)
local_irq_enable();
set_thread_flag(TIF_POLLING_NRFLAG);
clear_bl_bit();
} else
poll_idle();
}
......
......@@ -133,12 +133,8 @@ void __update_cache(struct vm_area_struct *vma,
page = pfn_to_page(pfn);
if (pfn_valid(pfn)) {
int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
if (dirty) {
unsigned long addr = (unsigned long)page_address(page);
if (pages_do_alias(addr, address & PAGE_MASK))
__flush_purge_region((void *)addr, PAGE_SIZE);
}
if (dirty)
__flush_purge_region(page_address(page), PAGE_SIZE);
}
}
......
......@@ -222,9 +222,9 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
Set SCP6MD1,0 = {01} (output) */
__raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
data = ctrl_inb(SCPDR);
data = __raw_readb(SCPDR);
/* Set /RTS2 (bit6) = 0 */
ctrl_outb(data & 0xbf, SCPDR);
__raw_writeb(data & 0xbf, SCPDR);
}
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
......@@ -897,11 +897,21 @@ static void sci_shutdown(struct uart_port *port)
static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
struct ktermios *old)
{
unsigned int status, baud, smr_val;
unsigned int status, baud, smr_val, max_baud;
int t = -1;
baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
if (likely(baud))
/*
* earlyprintk comes here early on with port->uartclk set to zero.
* the clock framework is not up and running at this point so here
* we assume that 115200 is the maximum baud rate. please note that
* the baud rate is not programmed during earlyprintk - it is assumed
* that the previous boot loader has enabled required clocks and
* setup the baud rate generator hardware for us already.
*/
max_baud = port->uartclk ? port->uartclk / 16 : 115200;
baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
if (likely(baud && port->uartclk))
t = SCBRR_VALUE(baud, port->uartclk);
do {
......
......@@ -517,20 +517,20 @@ static const struct __attribute__((packed)) {
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xfffffe80)
return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
if (port->mapbase == 0xa4000150)
return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xa4000140)
return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == SCIF0)
return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
if (port->mapbase == SCIF2)
return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
......@@ -557,68 +557,68 @@ static inline int sci_rxd_in(struct uart_port *port)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
if (port->mapbase == 0xffe80000)
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe80000)
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xfe4b0000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0;
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0;
if (port->mapbase == 0xfe4c0000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0;
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0;
if (port->mapbase == 0xfe4d0000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0;
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xfe600000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xfe610000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xfe620000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffe10000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffe20000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffe30000)
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
return __raw_readb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
return __raw_readb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
if (port->mapbase == 0xffe10000)
return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
return __raw_readb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
if (port->mapbase == 0xffe20000)
return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
return __raw_readb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
return 1;
}
......@@ -626,17 +626,17 @@ static inline int sci_rxd_in(struct uart_port *port)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
return __raw_readb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
if (port->mapbase == 0xffe10000)
return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
return __raw_readb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
if (port->mapbase == 0xffe20000)
return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
return __raw_readb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
if (port->mapbase == 0xa4e30000)
return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
return __raw_readb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
if (port->mapbase == 0xa4e40000)
return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
return __raw_readb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
if (port->mapbase == 0xa4e50000)
return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
return __raw_readb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
......@@ -645,9 +645,9 @@ static inline int sci_rxd_in(struct uart_port *port)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->type == PORT_SCIF)
return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0;
return __raw_readw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0;
if (port->type == PORT_SCIFA)
return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
return __raw_readw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
......@@ -665,11 +665,11 @@ static inline int sci_rxd_in(struct uart_port *port)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffe08000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffe10000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
return 1;
}
......@@ -677,20 +677,20 @@ static inline int sci_rxd_in(struct uart_port *port)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xff923000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xff924000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xff925000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffe10000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
......@@ -698,17 +698,17 @@ static inline int sci_rxd_in(struct uart_port *port)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffea0000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffeb0000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffec0000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffed0000)
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffee0000)
return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffef0000)
return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
......@@ -718,22 +718,22 @@ static inline int sci_rxd_in(struct uart_port *port)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xfffe8000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xfffe8800)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xfffe9000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xfffe9800)
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
#if defined(CONFIG_CPU_SUBTYPE_SH7201)
if (port->mapbase == 0xfffeA000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xfffeA800)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xfffeB000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xfffeB800)
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
#endif
return 1;
}
......@@ -741,24 +741,24 @@ static inline int sci_rxd_in(struct uart_port *port)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xf8400000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xf8410000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xf8420000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffc30000)
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffc40000)
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffc50000)
return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
if (port->mapbase == 0xffc60000)
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
return 1;
}
#endif
......
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