1. 20 Jun, 2016 4 commits
    • Mahesh Salgaonkar's avatar
      KVM: PPC: Book3S HV: Fix TB corruption in guest exit path on HMI interrupt · fd7bacbc
      Mahesh Salgaonkar authored
      
      
      When a guest is assigned to a core it converts the host Timebase (TB)
      into guest TB by adding guest timebase offset before entering into
      guest. During guest exit it restores the guest TB to host TB. This means
      under certain conditions (Guest migration) host TB and guest TB can differ.
      
      When we get an HMI for TB related issues the opal HMI handler would
      try fixing errors and restore the correct host TB value. With no guest
      running, we don't have any issues. But with guest running on the core
      we run into TB corruption issues.
      
      If we get an HMI while in the guest, the current HMI handler invokes opal
      hmi handler before forcing guest to exit. The guest exit path subtracts
      the guest TB offset from the current TB value which may have already
      been restored with host value by opal hmi handler. This leads to incorrect
      host and guest TB values.
      
      With split-core, things become more complex. With split-core, TB also gets
      split and each subcore gets its own TB register. When a hmi handler fixes
      a TB error and restores the TB value, it affects all the TB values of
      sibling subcores on the same core. On TB errors all the thread in the core
      gets HMI. With existing code, the individual threads call opal hmi handle
      independently which can easily throw TB out of sync if we have guest
      running on subcores. Hence we will need to co-ordinate with all the
      threads before making opal hmi handler call followed by TB resync.
      
      This patch introduces a sibling subcore state structure (shared by all
      threads in the core) in paca which holds information about whether sibling
      subcores are in Guest mode or host mode. An array in_guest[] of size
      MAX_SUBCORE_PER_CORE=4 is used to maintain the state of each subcore.
      The subcore id is used as index into in_guest[] array. Only primary
      thread entering/exiting the guest is responsible to set/unset its
      designated array element.
      
      On TB error, we get HMI interrupt on every thread on the core. Upon HMI,
      this patch will now force guest to vacate the core/subcore. Primary
      thread from each subcore will then turn off its respective bit
      from the above bitmap during the guest exit path just after the
      guest->host partition switch is complete.
      
      All other threads that have just exited the guest OR were already in host
      will wait until all other subcores clears their respective bit.
      Once all the subcores turn off their respective bit, all threads will
      will make call to opal hmi handler.
      
      It is not necessary that opal hmi handler would resync the TB value for
      every HMI interrupts. It would do so only for the HMI caused due to
      TB errors. For rest, it would not touch TB value. Hence to make things
      simpler, primary thread would call TB resync explicitly once for each
      core immediately after opal hmi handler instead of subtracting guest
      offset from TB. TB resync call will restore the TB with host value.
      Thus we can be sure about the TB state.
      
      One of the primary threads exiting the guest will take up the
      responsibility of calling TB resync. It will use one of the top bits
      (bit 63) from subcore state flags bitmap to make the decision. The first
      primary thread (among the subcores) that is able to set the bit will
      have to call the TB resync. Rest all other threads will wait until TB
      resync is complete.  Once TB resync is complete all threads will then
      proceed.
      Signed-off-by: default avatarMahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
      fd7bacbc
    • Mahesh Salgaonkar's avatar
      powerpc/powernv: Remove the usage of PACAR1 from opal wrappers · 6dd06d15
      Mahesh Salgaonkar authored
      
      
      OPAL_CALL wrapper code sticks the r1 (stack pointer) into PACAR1 purely
      for debugging purpose only. The power7_wakeup* functions relies on stack
      pointer saved in PACAR1. Any opal call made using opal wrapper (directly
      or in-directly) before we fall through power7_wakeup*, then it ends up
      replacing r1 in PACAR1(r13) leading to kernel panic. So far we don't see
      any issues because we have never made any opal calls using OPAL wrapper
      before power7_wakeup*. But the subsequent HMI patch would need to invoke
      C calls during cpu wakeup/idle path that in-directly makes opal call using
      opal wrapper. This patch facilitates the subsequent HMI patch by removing
      usage of PACAR1 from opal call wrapper.
      Signed-off-by: default avatarMahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
      Acked-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
      Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
      6dd06d15
    • Thomas Huth's avatar
      KVM: PPC: Book3S PR: Fix contents of SRR1 when injecting a program exception · b69890d1
      Thomas Huth authored
      
      
      vcpu->arch.shadow_srr1 only contains usable values for injecting
      a program exception into the guest if we entered the function
      kvmppc_handle_exit_pr() with exit_nr == BOOK3S_INTERRUPT_PROGRAM.
      In other cases, the shadow_srr1 bits are zero. Since we want to
      pass an illegal-instruction program check to the guest, set
      "flags" to SRR1_PROGILL for these other cases.
      Signed-off-by: default avatarThomas Huth <thuth@redhat.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
      b69890d1
    • Thomas Huth's avatar
      KVM: PPC: Book3S PR: Fix illegal opcode emulation · 708e75a3
      Thomas Huth authored
      
      
      If kvmppc_handle_exit_pr() calls kvmppc_emulate_instruction() to emulate
      one instruction (in the BOOK3S_INTERRUPT_H_EMUL_ASSIST case), it calls
      kvmppc_core_queue_program() afterwards if kvmppc_emulate_instruction()
      returned EMULATE_FAIL, so the guest gets an program interrupt for the
      illegal opcode.
      However, the kvmppc_emulate_instruction() also tried to inject a
      program exception for this already, so the program interrupt gets
      injected twice and the return address in srr0 gets destroyed.
      All other callers of kvmppc_emulate_instruction() are also injecting
      a program interrupt, and since the callers have the right knowledge
      about the srr1 flags that should be used, it is the function
      kvmppc_emulate_instruction() that should _not_ inject program
      interrupts, so remove the kvmppc_core_queue_program() here.
      
      This fixes the issue discovered by Laurent Vivier with kvm-unit-tests
      where the logs are filled with these messages when the test tries
      to execute an illegal instruction:
      
           Couldn't emulate instruction 0x00000000 (op 0 xop 0)
           kvmppc_handle_exit_pr: emulation at 700 failed (00000000)
      Signed-off-by: default avatarThomas Huth <thuth@redhat.com>
      Reviewed-by: default avatarAlexander Graf <agraf@suse.de>
      Tested-by: default avatarLaurent Vivier <lvivier@redhat.com>
      Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
      708e75a3
  2. 16 Jun, 2016 5 commits
  3. 15 Jun, 2016 21 commits
    • Paolo Bonzini's avatar
      KVM: remove kvm_vcpu_compatible · 557abc40
      Paolo Bonzini authored
      
      
      The new created_vcpus field makes it possible to avoid the race between
      irqchip and VCPU creation in a much nicer way; just check under kvm->lock
      whether a VCPU has already been created.
      
      We can then remove KVM_APIC_ARCHITECTURE too, because at this point the
      symbol is only governing the default definition of kvm_vcpu_compatible.
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      557abc40
    • Paolo Bonzini's avatar
      KVM: introduce kvm->created_vcpus · 6c7caebc
      Paolo Bonzini authored
      
      
      The race between creating the irqchip and the first VCPU is
      currently fixed by checking the presence of an irqchip before
      updating kvm->online_vcpus, and undoing the whole VCPU creation
      if someone created the irqchip in the meanwhile.
      
      Instead, introduce a new field in struct kvm that will count VCPUs
      under a mutex, without the atomic access and memory ordering that we
      need elsewhere to protect the vcpus array.  This also plugs the race
      and is more easily applicable in all similar circumstances.
      Reviewed-by: default avatarCornelia Huck <cornelia.huck@de.ibm.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      6c7caebc
    • Borislav Petkov's avatar
      x86/kvm/svm: Simplify cpu_has_svm() · 682a8108
      Borislav Petkov authored
      
      
      Use already cached CPUID information instead of querying CPUID again.
      
      No functionality change.
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      Cc: Joerg Roedel <joro@8bytes.org>
      Cc: kvm@vger.kernel.org
      Cc: x86@kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      682a8108
    • James Hogan's avatar
      MIPS: KVM: Use mipsregs.h defs for config registers · 4e10b764
      James Hogan authored
      
      
      Convert MIPS KVM guest register state initialisation to use the standard
      <asm/mipsregs.h> register field definitions for Config registers, and
      drop the custom definitions in kvm_host.h which it was using before.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      4e10b764
    • James Hogan's avatar
      MIPS: KVM: Report more accurate CP0_Config fields to guest · e342925f
      James Hogan authored
      
      
      Initialise the guest's CP0_Config register with a few more bits of
      information from the host. The BE bit should be set on big endian
      machines, the VI bit should be set on machines with a virtually tagged
      instruction cache, and the reported architecture revision should match
      that of the host (since we won't support emulating pre-r6 instruction
      encodings on r6 or vice versa).
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      e342925f
    • James Hogan's avatar
      MIPS: Add define for Config.VI (virtual icache) bit · 4b34bca0
      James Hogan authored
      
      
      The Config.VI bit specifies that the instruction cache is virtually
      tagged, which is checked in c-r4k.c's probe_pcache(). Add a proper
      definition for it in mipsregs.h and make use of it.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      4b34bca0
    • James Hogan's avatar
      MIPS: KVM: Use host CCA for TLB mappings · 7414d2f6
      James Hogan authored
      
      
      KVM TLB mappings for the guest were being created with a cache coherency
      attribute (CCA) of 3, which is cached incoherent. Create them instead
      with the default host CCA, which should be the correct one for coherency
      on SMP systems.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      7414d2f6
    • James Hogan's avatar
      MIPS: KVM: Move commpage so 0x0 is unmapped · 42aa12e7
      James Hogan authored
      
      
      The comm page which is mapped into the guest kernel address space at
      0x0 has the unfortunate side effect of allowing guest kernel NULL
      pointer dereferences to succeed. The only constraint on this address is
      that it must be within 32KiB of 0x0, so that single lw/sw instructions
      (which have 16-bit signed offset fields) can be used to access it, using
      the zero register as a base.
      
      So lets move the comm page as high as possible within that constraint so
      that 0x0 can be left unmapped, at least for page sizes < 32KiB.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      42aa12e7
    • James Hogan's avatar
      MIPS: KVM: Add KScratch registers · 05108709
      James Hogan authored
      
      
      Allow up to 6 KVM guest KScratch registers to be enabled and accessed
      via the KVM guest register API and from the guest itself (the fallback
      reading and writing of commpage registers is sufficient for KScratch
      registers to work as expected).
      
      User mode can expose the registers by setting the appropriate bits of
      the guest Config4.KScrExist field. KScratch registers that aren't usable
      won't be writeable via the KVM Ioctl API.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      05108709
    • James Hogan's avatar
      MIPS: KVM: Emulate RDHWR CPUNum register · cf1fb0f2
      James Hogan authored
      
      
      Actually provide the VCPU number when emulating the RDHWR CPUNum
      register, so that it will match the CPUNum field of CP0_EBase register,
      rather than always returning 0.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      cf1fb0f2
    • James Hogan's avatar
      MIPS: KVM: Allow ULRI to restrict UserLocal register · cef061d0
      James Hogan authored
      
      
      The ULRI bit in Config3 specifies whether the UserLocal register is
      implemented, but it is assumed to always be set. Now that the Config
      registers can be modified by userland, allow Config3.ULRI to be cleared
      and check ULRI before allowing the corresponding bit to be set in
      HWREna.
      
      In fact any HWREna bits corresponding to unimplemented RDHWR registers
      should read as zero and be ignored on write, so we actually prevent
      other unimplemented bits being set too.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      cef061d0
    • James Hogan's avatar
      MIPS: KVM: Don't hardcode restored HWREna · b937ff62
      James Hogan authored
      
      
      KVM modifies CP0_HWREna during guest execution so it can trap and
      emulate RDHWR instructions, however it always restores the hardcoded
      value 0x2000000F. This assumes the presence of the UserLocal register,
      and the absence of any implementation dependent or future HW registers.
      
      Fix by exporting the value that traps.c write into CP0_HWREna, and
      loading from there instead of hard coding.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      b937ff62
    • James Hogan's avatar
      MIPS: Clean up RDHWR handling · aff565aa
      James Hogan authored
      
      
      No preprocessor definitions are used in the handling of the registers
      accessible with the RDHWR instruction, nor the corresponding bits in the
      CP0 HWREna register.
      
      Add definitions for both the register numbers (MIPS_HWR_*) and HWREna
      bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the
      initialisation of HWREna and emulation of the RDHWR instruction.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      aff565aa
    • James Hogan's avatar
      MIPS: KVM: List FPU/MSA registers · e5775930
      James Hogan authored
      
      
      Make KVM_GET_REG_LIST list FPU & MSA registers. Specifically we list all
      32 vector registers when MSA can be enabled, 32 single-precision FP
      registers when FPU can be enabled, and either 16 or 32 double-precision
      FP registers when FPU can be enabled depending on whether FR mode is
      supported (which provides 32 doubles instead of 16 even doubles).
      
      Note, these registers may still be inaccessible depending on the current
      FP mode of the guest.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      e5775930
    • James Hogan's avatar
      MIPS: KVM: Use raw_cpu_has_fpu in kvm_mips_guest_can_have_fpu() · 19451e51
      James Hogan authored
      
      
      We need to use kvm_mips_guest_can_have_fpu() when deciding which
      registers to list with KVM_GET_REG_LIST, however it causes warnings with
      preemption since it uses cpu_has_fpu. KVM is only really supported on
      CPUs which have symmetric FPUs, so switch to raw_cpu_has_fpu to avoid
      the warning.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      19451e51
    • James Hogan's avatar
      MIPS: KVM: Make KVM_GET_REG_LIST dynamic · f5c43bd4
      James Hogan authored
      
      
      Make the implementation of KVM_GET_REG_LIST more dynamic so that only
      the subset of registers actually available can be exposed to user mode.
      This is important for VZ where some of the guest register state may not
      be possible to prevent the guest from accessing, therefore the user
      process may need to be aware of the state even if it doesn't understand
      what the state is for.
      
      This also allows different MIPS KVM implementations to provide different
      registers to one another, by way of new num_regs(vcpu) and
      copy_reg_indices(vcpu, indices) callback functions, currently just
      stubbed for trap & emulate.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      f5c43bd4
    • James Hogan's avatar
      MIPS: KVM: Pass all unknown registers to callbacks · cc68d22f
      James Hogan authored
      
      
      Pass all unrecognised register IDs through to the set_one_reg() and
      get_one_reg() callbacks, not just select ones. This allows
      implementation specific registers to be more easily added without having
      to modify arch/mips/kvm/mips.c.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      cc68d22f
    • James Hogan's avatar
      MIPS: KVM: Convert emulation to use asm/inst.h · 258f3a2e
      James Hogan authored
      
      
      Convert various MIPS KVM guest instruction emulation functions to decode
      instructions (and encode translations) using the union mips_instruction
      and related enumerations in asm/inst.h rather than #defines and
      hardcoded values.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      258f3a2e
    • James Hogan's avatar
      MIPS: KVM: Factor writing of translated guest instructions · d5cd26bc
      James Hogan authored
      
      
      The code in kvm_mips_dyntrans.c to write a translated guest instruction
      to guest memory depending on the segment is duplicated between each of
      the functions. Additionally the cache op translation functions assume
      the instruction is in the KSEG0/1 segment rather than KSEG2/3, which is
      generally true but isn't guaranteed.
      
      Factor that code into a new kvm_mips_trans_replace() which handles both
      KSEG0/1 and KSEG2/3.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      d5cd26bc
    • James Hogan's avatar
      MIPS: KVM: Fix translation of MFC0 ErrCtl · 66ffc50c
      James Hogan authored
      The MIPS KVM dynamic translation is meant to translate "MFC0 rt, ErrCtl"
      instructions into "ADD rt, zero, zero" to zero the destination register,
      however the rt register number was copied into rt of the ADD instruction
      encoding, which is the 2nd source operand. This results in "ADD zero,
      zero, rt" which is a no-op, so only the first execution of each such
      MFC0 from ErrCtl will actually read 0.
      
      Fix the shift to put the rt from the MFC0 encoding into the rd field of
      the ADD.
      
      Fixes: 50c83085
      
       ("KVM/MIPS32: Binary patching of select privileged instructions.")
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      66ffc50c
    • Paolo Bonzini's avatar
      Merge tag 'kvm-s390-next-4.8-1' of... · f26ed983
      Paolo Bonzini authored
      Merge tag 'kvm-s390-next-4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD
      
      KVM: s390: Features and fixes for 4.8 part1
      
      Four bigger things:
      1. The implementation of the STHYI opcode in the kernel. This is used
         in libraries like qclib [1] to provide enough information for a
         capacity and usage based software licence pricing. The STHYI content
         is defined by the related z/VM documentation [2]. Its data can be
         composed by accessing several other interfaces provided by LPAR or
         the machine. This information is partially sensitive or root-only
         so the kernel does the necessary filtering.
      2. Preparation for nested virtualization (VSIE). KVM should query the
         proper sclp interfaces for the availability of some features before
         using it. In the past we have been sloppy and simply assumed that
         several features are available. With this we should be able to handle
         most cases of a missing feature.
      3. CPU model interfaces extended by some additional features that are
         not covered by a facility bit in STFLE. For example all the crypto
         instructions of the coprocessor provide a query function. As reality
         tends to be more complex (e.g. export regulations might block some
         algorithms) we have to provide additional interfaces to query or
         set these non-stfle features.
      4. Several fixes and changes detected and fixed when doing 1-3.
      
      All features change base s390 code. All relevant patches have an ACK
      from the s390 or component maintainers.
      
      The next pull request for 4.8 (part2) will contain the implementation
      of VSIE.
      
      [1] http://www.ibm.com/developerworks/linux/linux390/qclib.html
      [2] https://www.ibm.com/support/knowledgecenter/SSB27U_6.3.0/com.ibm.zvm.v630.hcpb4/hcpb4sth.htm
      f26ed983
  4. 14 Jun, 2016 10 commits