pinctrl-intel.c 42.2 KB
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// SPDX-License-Identifier: GPL-2.0
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/*
 * Intel pinctrl/GPIO core driver.
 *
 * Copyright (C) 2015, Intel Corporation
 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
 *          Mika Westerberg <mika.westerberg@linux.intel.com>
 */

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#include <linux/acpi.h>
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#include <linux/interrupt.h>
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#include <linux/gpio/driver.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/time.h>
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#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>

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#include "../core.h"
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#include "pinctrl-intel.h"

/* Offset from regs */
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#define REVID				0x000
#define REVID_SHIFT			16
#define REVID_MASK			GENMASK(31, 16)

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#define PADBAR				0x00c

#define PADOWN_BITS			4
#define PADOWN_SHIFT(p)			((p) % 8 * PADOWN_BITS)
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#define PADOWN_MASK(p)			(GENMASK(3, 0) << PADOWN_SHIFT(p))
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#define PADOWN_GPP(p)			((p) / 8)
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/* Offset from pad_regs */
#define PADCFG0				0x000
#define PADCFG0_RXEVCFG_SHIFT		25
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#define PADCFG0_RXEVCFG_MASK		GENMASK(26, 25)
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#define PADCFG0_RXEVCFG_LEVEL		0
#define PADCFG0_RXEVCFG_EDGE		1
#define PADCFG0_RXEVCFG_DISABLED	2
#define PADCFG0_RXEVCFG_EDGE_BOTH	3
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#define PADCFG0_PREGFRXSEL		BIT(24)
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#define PADCFG0_RXINV			BIT(23)
#define PADCFG0_GPIROUTIOXAPIC		BIT(20)
#define PADCFG0_GPIROUTSCI		BIT(19)
#define PADCFG0_GPIROUTSMI		BIT(18)
#define PADCFG0_GPIROUTNMI		BIT(17)
#define PADCFG0_PMODE_SHIFT		10
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#define PADCFG0_PMODE_MASK		GENMASK(13, 10)
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#define PADCFG0_PMODE_GPIO		0
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#define PADCFG0_GPIORXDIS		BIT(9)
#define PADCFG0_GPIOTXDIS		BIT(8)
#define PADCFG0_GPIORXSTATE		BIT(1)
#define PADCFG0_GPIOTXSTATE		BIT(0)

#define PADCFG1				0x004
#define PADCFG1_TERM_UP			BIT(13)
#define PADCFG1_TERM_SHIFT		10
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#define PADCFG1_TERM_MASK		GENMASK(12, 10)
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#define PADCFG1_TERM_20K		4
#define PADCFG1_TERM_2K			3
#define PADCFG1_TERM_5K			2
#define PADCFG1_TERM_1K			1

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#define PADCFG2				0x008
#define PADCFG2_DEBEN			BIT(0)
#define PADCFG2_DEBOUNCE_SHIFT		1
#define PADCFG2_DEBOUNCE_MASK		GENMASK(4, 1)

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#define DEBOUNCE_PERIOD_NSEC		31250
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struct intel_pad_context {
	u32 padcfg0;
	u32 padcfg1;
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	u32 padcfg2;
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};

struct intel_community_context {
	u32 *intmask;
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	u32 *hostown;
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};

struct intel_pinctrl_context {
	struct intel_pad_context *pads;
	struct intel_community_context *communities;
};

/**
 * struct intel_pinctrl - Intel pinctrl private structure
 * @dev: Pointer to the device structure
 * @lock: Lock to serialize register access
 * @pctldesc: Pin controller description
 * @pctldev: Pointer to the pin controller device
 * @chip: GPIO chip in this pin controller
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 * @irqchip: IRQ chip in this pin controller
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 * @soc: SoC/PCH specific pin configuration data
 * @communities: All communities in this pin controller
 * @ncommunities: Number of communities in this pin controller
 * @context: Configuration saved over system sleep
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 * @irq: pinctrl/GPIO chip irq number
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 */
struct intel_pinctrl {
	struct device *dev;
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	raw_spinlock_t lock;
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	struct pinctrl_desc pctldesc;
	struct pinctrl_dev *pctldev;
	struct gpio_chip chip;
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	struct irq_chip irqchip;
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	const struct intel_pinctrl_soc_data *soc;
	struct intel_community *communities;
	size_t ncommunities;
	struct intel_pinctrl_context context;
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	int irq;
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};

#define pin_to_padno(c, p)	((p) - (c)->pin_base)
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#define padgroup_offset(g, p)	((p) - (g)->base)
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static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
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						   unsigned int pin)
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{
	struct intel_community *community;
	int i;

	for (i = 0; i < pctrl->ncommunities; i++) {
		community = &pctrl->communities[i];
		if (pin >= community->pin_base &&
		    pin < community->pin_base + community->npins)
			return community;
	}

	dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
	return NULL;
}

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static const struct intel_padgroup *
intel_community_get_padgroup(const struct intel_community *community,
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			     unsigned int pin)
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{
	int i;

	for (i = 0; i < community->ngpps; i++) {
		const struct intel_padgroup *padgrp = &community->gpps[i];

		if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
			return padgrp;
	}

	return NULL;
}

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static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
				      unsigned int pin, unsigned int reg)
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{
	const struct intel_community *community;
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	unsigned int padno;
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	size_t nregs;
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	community = intel_get_community(pctrl, pin);
	if (!community)
		return NULL;

	padno = pin_to_padno(community, pin);
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	nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;

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	if (reg >= nregs * 4)
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		return NULL;

	return community->pad_regs + reg + padno * nregs * 4;
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}

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static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
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{
	const struct intel_community *community;
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	const struct intel_padgroup *padgrp;
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	unsigned int gpp, offset, gpp_offset;
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	void __iomem *padown;

	community = intel_get_community(pctrl, pin);
	if (!community)
		return false;
	if (!community->padown_offset)
		return true;

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	padgrp = intel_community_get_padgroup(community, pin);
	if (!padgrp)
		return false;

	gpp_offset = padgroup_offset(padgrp, pin);
	gpp = PADOWN_GPP(gpp_offset);
	offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
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	padown = community->regs + offset;

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	return !(readl(padown) & PADOWN_MASK(gpp_offset));
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}

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static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
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{
	const struct intel_community *community;
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	const struct intel_padgroup *padgrp;
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	unsigned int offset, gpp_offset;
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	void __iomem *hostown;

	community = intel_get_community(pctrl, pin);
	if (!community)
		return true;
	if (!community->hostown_offset)
		return false;

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	padgrp = intel_community_get_padgroup(community, pin);
	if (!padgrp)
		return true;

	gpp_offset = padgroup_offset(padgrp, pin);
	offset = community->hostown_offset + padgrp->reg_num * 4;
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	hostown = community->regs + offset;

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	return !(readl(hostown) & BIT(gpp_offset));
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}

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/**
 * enum - Locking variants of the pad configuration
 *
 * @PAD_UNLOCKED:	pad is fully controlled by the configuration registers
 * @PAD_LOCKED:		pad configuration registers, except TX state, are locked
 * @PAD_LOCKED_TX:	pad configuration TX state is locked
 * @PAD_LOCKED_FULL:	pad configuration registers are locked completely
 *
 * Locking is considered as read-only mode for corresponding registers and
 * their respective fields. That said, TX state bit is locked separately from
 * the main locking scheme.
 */
enum {
	PAD_UNLOCKED	= 0,
	PAD_LOCKED	= 1,
	PAD_LOCKED_TX	= 2,
	PAD_LOCKED_FULL	= PAD_LOCKED | PAD_LOCKED_TX,
};

static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
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{
	struct intel_community *community;
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	const struct intel_padgroup *padgrp;
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	unsigned int offset, gpp_offset;
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	u32 value;
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	int ret = PAD_UNLOCKED;
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	community = intel_get_community(pctrl, pin);
	if (!community)
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		return PAD_LOCKED_FULL;
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	if (!community->padcfglock_offset)
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		return PAD_UNLOCKED;
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	padgrp = intel_community_get_padgroup(community, pin);
	if (!padgrp)
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		return PAD_LOCKED_FULL;
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	gpp_offset = padgroup_offset(padgrp, pin);
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	/*
	 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
	 * the pad is considered unlocked. Any other case means that it is
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	 * either fully or partially locked.
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	 */
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	offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
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	value = readl(community->regs + offset);
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	if (value & BIT(gpp_offset))
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		ret |= PAD_LOCKED;
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	offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
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	value = readl(community->regs + offset);
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	if (value & BIT(gpp_offset))
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		ret |= PAD_LOCKED_TX;
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	return ret;
}

static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
{
	return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
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}

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static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
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{
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	return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
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}

static int intel_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	return pctrl->soc->ngroups;
}

static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
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				      unsigned int group)
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{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	return pctrl->soc->groups[group].name;
}

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static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
			      const unsigned int **pins, unsigned int *npins)
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{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	*pins = pctrl->soc->groups[group].pins;
	*npins = pctrl->soc->groups[group].npins;
	return 0;
}

static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
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			       unsigned int pin)
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{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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	void __iomem *padcfg;
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	u32 cfg0, cfg1, mode;
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	int locked;
	bool acpi;
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	if (!intel_pad_owned_by_host(pctrl, pin)) {
		seq_puts(s, "not available");
		return;
	}

	cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
	cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));

	mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
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	if (mode == PADCFG0_PMODE_GPIO)
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		seq_puts(s, "GPIO ");
	else
		seq_printf(s, "mode %d ", mode);

	seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);

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	/* Dump the additional PADCFG registers if available */
	padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
	if (padcfg)
		seq_printf(s, " 0x%08x", readl(padcfg));

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	locked = intel_pad_locked(pctrl, pin);
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	acpi = intel_pad_acpi_mode(pctrl, pin);
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	if (locked || acpi) {
		seq_puts(s, " [");
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		if (locked)
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			seq_puts(s, "LOCKED");
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		if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
			seq_puts(s, " tx");
		else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
			seq_puts(s, " full");

		if (locked && acpi)
			seq_puts(s, ", ");

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		if (acpi)
			seq_puts(s, "ACPI");
		seq_puts(s, "]");
	}
}

static const struct pinctrl_ops intel_pinctrl_ops = {
	.get_groups_count = intel_get_groups_count,
	.get_group_name = intel_get_group_name,
	.get_group_pins = intel_get_group_pins,
	.pin_dbg_show = intel_pin_dbg_show,
};

static int intel_get_functions_count(struct pinctrl_dev *pctldev)
{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	return pctrl->soc->nfunctions;
}

static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
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					   unsigned int function)
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{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	return pctrl->soc->functions[function].name;
}

static int intel_get_function_groups(struct pinctrl_dev *pctldev,
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				     unsigned int function,
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				     const char * const **groups,
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				     unsigned int * const ngroups)
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{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

	*groups = pctrl->soc->functions[function].groups;
	*ngroups = pctrl->soc->functions[function].ngroups;
	return 0;
}

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static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
				unsigned int function, unsigned int group)
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{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
	const struct intel_pingroup *grp = &pctrl->soc->groups[group];
	unsigned long flags;
	int i;

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	raw_spin_lock_irqsave(&pctrl->lock, flags);
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	/*
	 * All pins in the groups needs to be accessible and writable
	 * before we can enable the mux for this group.
	 */
	for (i = 0; i < grp->npins; i++) {
		if (!intel_pad_usable(pctrl, grp->pins[i])) {
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			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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			return -EBUSY;
		}
	}

	/* Now enable the mux setting for each pin in the group */
	for (i = 0; i < grp->npins; i++) {
		void __iomem *padcfg0;
		u32 value;

		padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
		value = readl(padcfg0);

		value &= ~PADCFG0_PMODE_MASK;
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		if (grp->modes)
			value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
		else
			value |= grp->mode << PADCFG0_PMODE_SHIFT;
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		writel(value, padcfg0);
	}

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	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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	return 0;
}

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static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
{
	u32 value;

	value = readl(padcfg0);
	if (input) {
		value &= ~PADCFG0_GPIORXDIS;
		value |= PADCFG0_GPIOTXDIS;
	} else {
		value &= ~PADCFG0_GPIOTXDIS;
		value |= PADCFG0_GPIORXDIS;
	}
	writel(value, padcfg0);
}

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static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
{
	return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
}

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static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
{
	u32 value;

	/* Put the pad into GPIO mode */
	value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
	/* Disable SCI/SMI/NMI generation */
	value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
	value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
	writel(value, padcfg0);
}

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static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
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				     unsigned int pin)
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{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
	void __iomem *padcfg0;
	unsigned long flags;

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	raw_spin_lock_irqsave(&pctrl->lock, flags);
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	if (!intel_pad_owned_by_host(pctrl, pin)) {
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		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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		return -EBUSY;
	}

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	if (!intel_pad_is_unlocked(pctrl, pin)) {
		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
		return 0;
	}

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	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
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	/*
	 * If pin is already configured in GPIO mode, we assume that
	 * firmware provides correct settings. In such case we avoid
	 * potential glitches on the pin. Otherwise, for the pin in
	 * alternative mode, consumer has to supply respective flags.
	 */
	if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
		return 0;
	}

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	intel_gpio_set_gpio_mode(padcfg0);
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	/* Disable TX buffer and enable RX (this will be input) */
	__intel_gpio_set_direction(padcfg0, true);

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	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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	return 0;
}

static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
				    struct pinctrl_gpio_range *range,
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				    unsigned int pin, bool input)
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{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
	void __iomem *padcfg0;
	unsigned long flags;

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	raw_spin_lock_irqsave(&pctrl->lock, flags);
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	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
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	__intel_gpio_set_direction(padcfg0, input);
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	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
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	return 0;
}

static const struct pinmux_ops intel_pinmux_ops = {
	.get_functions_count = intel_get_functions_count,
	.get_function_name = intel_get_function_name,
	.get_function_groups = intel_get_function_groups,
	.set_mux = intel_pinmux_set_mux,
	.gpio_request_enable = intel_gpio_request_enable,
	.gpio_set_direction = intel_gpio_set_direction,
};

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static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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			    unsigned long *config)
{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
	enum pin_config_param param = pinconf_to_config_param(*config);
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	const struct intel_community *community;
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	u32 value, term;
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	u32 arg = 0;
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	if (!intel_pad_owned_by_host(pctrl, pin))
		return -ENOTSUPP;

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	community = intel_get_community(pctrl, pin);
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	value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
	term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
		if (term)
			return -EINVAL;
		break;

	case PIN_CONFIG_BIAS_PULL_UP:
		if (!term || !(value & PADCFG1_TERM_UP))
			return -EINVAL;

		switch (term) {
		case PADCFG1_TERM_1K:
			arg = 1000;
			break;
		case PADCFG1_TERM_2K:
			arg = 2000;
			break;
		case PADCFG1_TERM_5K:
			arg = 5000;
			break;
		case PADCFG1_TERM_20K:
			arg = 20000;
			break;
		}

		break;

	case PIN_CONFIG_BIAS_PULL_DOWN:
		if (!term || value & PADCFG1_TERM_UP)
			return -EINVAL;

		switch (term) {
597
598
599
600
601
		case PADCFG1_TERM_1K:
			if (!(community->features & PINCTRL_FEATURE_1K_PD))
				return -EINVAL;
			arg = 1000;
			break;
602
603
604
605
606
607
608
609
610
611
		case PADCFG1_TERM_5K:
			arg = 5000;
			break;
		case PADCFG1_TERM_20K:
			arg = 20000;
			break;
		}

		break;

612
613
614
615
616
617
618
619
620
621
622
623
624
	case PIN_CONFIG_INPUT_DEBOUNCE: {
		void __iomem *padcfg2;
		u32 v;

		padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
		if (!padcfg2)
			return -ENOTSUPP;

		v = readl(padcfg2);
		if (!(v & PADCFG2_DEBEN))
			return -EINVAL;

		v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
625
		arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
626
627
628
629

		break;
	}

630
631
632
633
634
635
636
637
	default:
		return -ENOTSUPP;
	}

	*config = pinconf_to_config_packed(param, arg);
	return 0;
}

638
static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
639
640
				 unsigned long config)
{
641
642
	unsigned int param = pinconf_to_config_param(config);
	unsigned int arg = pinconf_to_config_argument(config);
643
	const struct intel_community *community;
644
645
646
647
648
	void __iomem *padcfg1;
	unsigned long flags;
	int ret = 0;
	u32 value;

649
	raw_spin_lock_irqsave(&pctrl->lock, flags);
650

651
	community = intel_get_community(pctrl, pin);
652
653
654
655
656
657
658
659
660
661
662
663
664
	padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
	value = readl(padcfg1);

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
		value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
		break;

	case PIN_CONFIG_BIAS_PULL_UP:
		value &= ~PADCFG1_TERM_MASK;

		value |= PADCFG1_TERM_UP;

665
666
667
668
		/* Set default strength value in case none is given */
		if (arg == 1)
			arg = 5000;

669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
		switch (arg) {
		case 20000:
			value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
			break;
		case 5000:
			value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
			break;
		case 2000:
			value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
			break;
		case 1000:
			value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
			break;
		default:
			ret = -EINVAL;
		}

		break;

	case PIN_CONFIG_BIAS_PULL_DOWN:
		value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);

691
692
693
694
		/* Set default strength value in case none is given */
		if (arg == 1)
			arg = 5000;

695
696
697
698
699
700
701
		switch (arg) {
		case 20000:
			value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
			break;
		case 5000:
			value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
			break;
702
		case 1000:
703
704
705
706
			if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
				ret = -EINVAL;
				break;
			}
707
708
			value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
			break;
709
710
711
712
713
714
715
716
717
718
		default:
			ret = -EINVAL;
		}

		break;
	}

	if (!ret)
		writel(value, padcfg1);

719
	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
720
721
722
723

	return ret;
}

724
725
static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
				     unsigned int pin, unsigned int debounce)
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
{
	void __iomem *padcfg0, *padcfg2;
	unsigned long flags;
	u32 value0, value2;
	int ret = 0;

	padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
	if (!padcfg2)
		return -ENOTSUPP;

	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);

	raw_spin_lock_irqsave(&pctrl->lock, flags);

	value0 = readl(padcfg0);
	value2 = readl(padcfg2);

	/* Disable glitch filter and debouncer */
	value0 &= ~PADCFG0_PREGFRXSEL;
	value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);

	if (debounce) {
		unsigned long v;

750
		v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
		if (v < 3 || v > 15) {
			ret = -EINVAL;
			goto exit_unlock;
		} else {
			/* Enable glitch filter and debouncer */
			value0 |= PADCFG0_PREGFRXSEL;
			value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
			value2 |= PADCFG2_DEBEN;
		}
	}

	writel(value0, padcfg0);
	writel(value2, padcfg2);

exit_unlock:
	raw_spin_unlock_irqrestore(&pctrl->lock, flags);

	return ret;
}

771
772
static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
			  unsigned long *configs, unsigned int nconfigs)
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
{
	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
	int i, ret;

	if (!intel_pad_usable(pctrl, pin))
		return -ENOTSUPP;

	for (i = 0; i < nconfigs; i++) {
		switch (pinconf_to_config_param(configs[i])) {
		case PIN_CONFIG_BIAS_DISABLE:
		case PIN_CONFIG_BIAS_PULL_UP:
		case PIN_CONFIG_BIAS_PULL_DOWN:
			ret = intel_config_set_pull(pctrl, pin, configs[i]);
			if (ret)
				return ret;
			break;

790
791
792
793
794
795
796
		case PIN_CONFIG_INPUT_DEBOUNCE:
			ret = intel_config_set_debounce(pctrl, pin,
				pinconf_to_config_argument(configs[i]));
			if (ret)
				return ret;
			break;

797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
		default:
			return -ENOTSUPP;
		}
	}

	return 0;
}

static const struct pinconf_ops intel_pinconf_ops = {
	.is_generic = true,
	.pin_config_get = intel_config_get,
	.pin_config_set = intel_config_set,
};

static const struct pinctrl_desc intel_pinctrl_desc = {
	.pctlops = &intel_pinctrl_ops,
	.pmxops = &intel_pinmux_ops,
	.confops = &intel_pinconf_ops,
	.owner = THIS_MODULE,
};

818
819
820
821
/**
 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 * @pctrl: Pinctrl structure
 * @offset: GPIO offset from gpiolib
822
 * @community: Community is filled here if not %NULL
823
824
825
826
827
828
 * @padgrp: Pad group is filled here if not %NULL
 *
 * When coming through gpiolib irqchip, the GPIO offset is not
 * automatically translated to pinctrl pin number. This function can be
 * used to find out the corresponding pinctrl pin.
 */
829
static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
			     const struct intel_community **community,
			     const struct intel_padgroup **padgrp)
{
	int i;

	for (i = 0; i < pctrl->ncommunities; i++) {
		const struct intel_community *comm = &pctrl->communities[i];
		int j;

		for (j = 0; j < comm->ngpps; j++) {
			const struct intel_padgroup *pgrp = &comm->gpps[j];

			if (pgrp->gpio_base < 0)
				continue;

			if (offset >= pgrp->gpio_base &&
			    offset < pgrp->gpio_base + pgrp->size) {
				int pin;

				pin = pgrp->base + offset - pgrp->gpio_base;
				if (community)
					*community = comm;
				if (padgrp)
					*padgrp = pgrp;

				return pin;
			}
		}
	}

	return -EINVAL;
}

863
864
865
866
867
868
869
/**
 * intel_pin_to_gpio() - Translate from pin number to GPIO offset
 * @pctrl: Pinctrl structure
 * @pin: pin number
 *
 * Translate the pin number of pinctrl to GPIO offset
 */
870
static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
{
	const struct intel_community *community;
	const struct intel_padgroup *padgrp;

	community = intel_get_community(pctrl, pin);
	if (!community)
		return -EINVAL;

	padgrp = intel_community_get_padgroup(community, pin);
	if (!padgrp)
		return -EINVAL;

	return pin - padgrp->base + padgrp->gpio_base;
}

886
static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
887
{
888
	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
889
	void __iomem *reg;
890
	u32 padcfg0;
891
	int pin;
892

893
894
895
	pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
	if (pin < 0)
		return -EINVAL;
896

897
	reg = intel_get_padcfg(pctrl, pin, PADCFG0);
898
899
900
	if (!reg)
		return -EINVAL;

901
902
903
904
905
	padcfg0 = readl(reg);
	if (!(padcfg0 & PADCFG0_GPIOTXDIS))
		return !!(padcfg0 & PADCFG0_GPIOTXSTATE);

	return !!(padcfg0 & PADCFG0_GPIORXSTATE);
906
907
}

908
909
static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
			   int value)
910
{
911
	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
912
	unsigned long flags;
913
	void __iomem *reg;
914
	u32 padcfg0;
915
	int pin;
916

917
918
919
920
921
	pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
	if (pin < 0)
		return;

	reg = intel_get_padcfg(pctrl, pin, PADCFG0);
922
923
924
925
926
927
928
929
930
931
932
	if (!reg)
		return;

	raw_spin_lock_irqsave(&pctrl->lock, flags);
	padcfg0 = readl(reg);
	if (value)
		padcfg0 |= PADCFG0_GPIOTXSTATE;
	else
		padcfg0 &= ~PADCFG0_GPIOTXSTATE;
	writel(padcfg0, reg);
	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
933
934
}

935
936
937
938
939
static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
{
	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
	void __iomem *reg;
	u32 padcfg0;
940
941
942
943
944
	int pin;

	pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
	if (pin < 0)
		return -EINVAL;
945

946
	reg = intel_get_padcfg(pctrl, pin, PADCFG0);
947
948
949
950
951
952
953
954
955
956
957
	if (!reg)
		return -EINVAL;

	padcfg0 = readl(reg);

	if (padcfg0 & PADCFG0_PMODE_MASK)
		return -EINVAL;

	return !!(padcfg0 & PADCFG0_GPIOTXDIS);
}

958
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
959
960
961
962
{
	return pinctrl_gpio_direction_input(chip->base + offset);
}

963
static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
964
965
966
967
968
969
970
971
				       int value)
{
	intel_gpio_set(chip, offset, value);
	return pinctrl_gpio_direction_output(chip->base + offset);
}

static const struct gpio_chip intel_gpio_chip = {
	.owner = THIS_MODULE,
972
973
	.request = gpiochip_generic_request,
	.free = gpiochip_generic_free,
974
	.get_direction = intel_gpio_get_direction,
975
976
977
978
	.direction_input = intel_gpio_direction_input,
	.direction_output = intel_gpio_direction_output,
	.get = intel_gpio_get,
	.set = intel_gpio_set,
979
	.set_config = gpiochip_generic_config,
980
981
982
983
984
};

static void intel_gpio_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
985
	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
986
	const struct intel_community *community;
987
988
	const struct intel_padgroup *padgrp;
	int pin;
989

990
991
	pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
	if (pin >= 0) {
992
		unsigned int gpp, gpp_offset, is_offset;
993
994
995

		gpp = padgrp->reg_num;
		gpp_offset = padgroup_offset(padgrp, pin);
996
		is_offset = community->is_offset + gpp * 4;
997

998
		raw_spin_lock(&pctrl->lock);
999
		writel(BIT(gpp_offset), community->regs + is_offset);
1000
		raw_spin_unlock(&pctrl->lock);
1001
1002
1003
1004
1005
1006
	}
}

static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1007
	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1008
	const struct intel_community *community;
1009
1010
	const struct intel_padgroup *padgrp;
	int pin;
1011

1012
1013
	pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
	if (pin >= 0) {
1014
		unsigned int gpp, gpp_offset;
1015
		unsigned long flags;
1016
		void __iomem *reg, *is;
1017
1018
		u32 value;

1019
1020
1021
		gpp = padgrp->reg_num;
		gpp_offset = padgroup_offset(padgrp, pin);

1022
		reg = community->regs + community->ie_offset + gpp * 4;
1023
		is = community->regs + community->is_offset + gpp * 4;
1024
1025

		raw_spin_lock_irqsave(&pctrl->lock, flags);
1026
1027
1028
1029

		/* Clear interrupt status first to avoid unexpected interrupt */
		writel(BIT(gpp_offset), is);

1030
1031
1032
1033
1034
1035
		value = readl(reg);
		if (mask)
			value &= ~BIT(gpp_offset);
		else
			value |= BIT(gpp_offset);
		writel(value, reg);
1036
		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
	}
}

static void intel_gpio_irq_mask(struct irq_data *d)
{
	intel_gpio_irq_mask_unmask(d, true);
}

static void intel_gpio_irq_unmask(struct irq_data *d)
{
	intel_gpio_irq_mask_unmask(d, false);
}

1050
static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1051
1052
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1053
	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1054
	unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1055
1056
1057
1058
1059
1060
1061
1062
	unsigned long flags;
	void __iomem *reg;
	u32 value;

	reg = intel_get_padcfg(pctrl, pin, PADCFG0);
	if (!reg)
		return -EINVAL;

1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
	/*
	 * If the pin is in ACPI mode it is still usable as a GPIO but it
	 * cannot be used as IRQ because GPI_IS status bit will not be
	 * updated by the host controller hardware.
	 */
	if (intel_pad_acpi_mode(pctrl, pin)) {
		dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
		return -EPERM;
	}

1073
	raw_spin_lock_irqsave(&pctrl->lock, flags);
1074

1075
1076
	intel_gpio_set_gpio_mode(reg);

1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
	value = readl(reg);

	value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);

	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
	} else if (type & IRQ_TYPE_EDGE_FALLING) {
		value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
		value |= PADCFG0_RXINV;
	} else if (type & IRQ_TYPE_EDGE_RISING) {
		value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1088
1089
1090
	} else if (type & IRQ_TYPE_LEVEL_MASK) {
		if (type & IRQ_TYPE_LEVEL_LOW)
			value |= PADCFG0_RXINV;
1091
1092
1093
1094
1095
1096
1097
	} else {
		value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
	}

	writel(value, reg);

	if (type & IRQ_TYPE_EDGE_BOTH)
1098
		irq_set_handler_locked(d, handle_edge_irq);
1099
	else if (type & IRQ_TYPE_LEVEL_MASK)
1100
		irq_set_handler_locked(d, handle_level_irq);
1101

1102
	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1103
1104
1105
1106
1107
1108
1109

	return 0;
}

static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1110
	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1111
	unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1112

1113
	if (on)
1114
		enable_irq_wake(pctrl->irq);
1115
	else
1116
		disable_irq_wake(pctrl->irq);
1117

1118
1119
1120
1121
	dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
	return 0;
}

1122
static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1123
1124
	const struct intel_community *community)
{
1125
1126
	struct gpio_chip *gc = &pctrl->chip;
	irqreturn_t ret = IRQ_NONE;
1127
1128
1129
	int gpp;

	for (gpp = 0; gpp < community->ngpps; gpp++) {
1130
		const struct intel_padgroup *padgrp = &community->gpps[gpp];
1131
1132
		unsigned long pending, enabled, gpp_offset;

1133
1134
		pending = readl(community->regs + community->is_offset +
				padgrp->reg_num * 4);
1135
		enabled = readl(community->regs + community->ie_offset +
1136
				padgrp->reg_num * 4);
1137
1138
1139
1140

		/* Only interrupts that are enabled */
		pending &= enabled;

1141
		for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1142
			unsigned irq;
1143

1144
			irq = irq_find_mapping(gc->irq.domain,
1145
					       padgrp->gpio_base + gpp_offset);
1146
1147
1148
			hard_cond_local_irq_disable();
			ipipe_handle_demuxed_irq(irq);
			hard_cond_local_irq_enable();
1149
1150

			ret |= IRQ_HANDLED;
1151
1152
		}
	}
1153
1154

	return ret;
1155
1156
}

1157
static irqreturn_t intel_gpio_irq(int irq, void *data)
1158
{
1159
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1161
	const struct intel_community *community;
	struct intel_pinctrl *pctrl = data;
	irqreturn_t ret = IRQ_NONE;
1162
1163
1164
	int i;

	/* Need to check all communities for pending interrupts */
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1168
	for (i = 0; i < pctrl->ncommunities; i++) {
		community = &pctrl->communities[i];
		ret |= intel_gpio_community_irq_handler(pctrl, community);
	}
1169

1170
	return ret;
1171
1172
}

1173
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1175
static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
				     const struct intel_community *community)
{
1176
	int ret = 0, i;
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1185
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1196

	for (i = 0; i < community->ngpps; i++) {
		const struct intel_padgroup *gpp = &community->gpps[i];

		if (gpp->gpio_base < 0)
			continue;

		ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
					     gpp->gpio_base, gpp->base,
					     gpp->size);
		if (ret)
			return ret;
	}

	return ret;
}

static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
{
	const struct intel_community *community;
1197
	unsigned int ngpio = 0;
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	int i, j;

	for (i = 0; i < pctrl->ncommunities; i++) {
		community = &pctrl->communities[i];
		for (j = 0; j < community->ngpps; j++) {
			const struct intel_padgroup *gpp = &community->gpps[j];

			if (gpp->gpio_base < 0)
				continue;

			if (gpp->gpio_base + gpp->size > ngpio)
				ngpio = gpp->gpio_base + gpp->size;
		}
	}

	return ngpio;
}

1216
1217
static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
{
1218
	int ret, i;
1219
1220
1221

	pctrl->chip = intel_gpio_chip;

1222
	/* Setup GPIO chip */
1223
	pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1224
	pctrl->chip.label = dev_name(pctrl->dev);
1225
	pctrl->chip.parent = pctrl->dev;
1226
	pctrl->chip.base = -1;
1227
	pctrl->irq = irq;
1228

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1235
	/* Setup IRQ chip */
	pctrl->irqchip.name = dev_name(pctrl->dev);
	pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
	pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
	pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
	pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
	pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
1236
	pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_PIPELINE_SAFE;
1237

1238
	ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
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	if (ret) {
		dev_err(pctrl->dev, "failed to register gpiochip\n");
		return ret;
	}

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	for (i = 0; i < pctrl->ncommunities; i++) {
		struct intel_community *community = &pctrl->communities[i];

		ret = intel_gpio_add_pin_ranges(pctrl, community);
		if (ret) {
			dev_err(pctrl->dev, "failed to add GPIO pin range\n");
			return ret;
		}
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1258
	}

	/*
	 * We need to request the interrupt here (instead of providing chip
	 * to the irq directly) because on some platforms several GPIO
	 * controllers share the same interrupt line.
	 */
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	ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
			       IRQF_SHARED | IRQF_NO_THREAD,
1261
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			       dev_name(pctrl->dev), pctrl);
	if (ret) {
		dev_err(pctrl->dev, "failed to request interrupt\n");
1264
		return ret;
1265
1266
	}

1267
	ret = gpiochip_irqchip_add(&pctrl->chip, &pctrl->irqchip, 0,
1268
				   handle_bad_irq, IRQ_TYPE_NONE);
1269
1270
	if (ret) {
		dev_err(pctrl->dev, "failed to add irqchip\n");
1271
		return ret;
1272
1273
	}

1274
	gpiochip_set_chained_irqchip(&pctrl->chip, &pctrl->irqchip, irq, NULL);
1275
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1277
	return 0;
}

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1281
static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
				       struct intel_community *community)
{
	struct intel_padgroup *gpps;
1282
1283
	unsigned int npins = community->npins;
	unsigned int padown_num = 0;
1284
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1286
1287
1288
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1290
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1298
	size_t ngpps, i;

	if (community->gpps)