intel_cacheinfo.c 31.4 KB
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/*
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 *	Routines to indentify caches on Intel CPU.
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 *
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 *	Changes:
 *	Venkatesh Pallipadi	: Adding cache identification through cpuid(4)
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 *	Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
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 *	Andi Kleen / Andreas Herrmann	: CPUID4 emulation on AMD.
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 */

#include <linux/init.h>
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/compiler.h>
#include <linux/cpu.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <asm/processor.h>
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#include <linux/smp.h>
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#include <asm/amd_nb.h>
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#include <asm/smp.h>
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#define LVL_1_INST	1
#define LVL_1_DATA	2
#define LVL_2		3
#define LVL_3		4
#define LVL_TRACE	5

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struct _cache_table {
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	unsigned char descriptor;
	char cache_type;
	short size;
};

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#define MB(x)	((x) * 1024)

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/* All the cache descriptor types we care about (no TLB or
   trace cache entries) */

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static const struct _cache_table __cpuinitconst cache_table[] =
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{
	{ 0x06, LVL_1_INST, 8 },	/* 4-way set assoc, 32 byte line size */
	{ 0x08, LVL_1_INST, 16 },	/* 4-way set assoc, 32 byte line size */
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	{ 0x09, LVL_1_INST, 32 },	/* 4-way set assoc, 64 byte line size */
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	{ 0x0a, LVL_1_DATA, 8 },	/* 2 way set assoc, 32 byte line size */
	{ 0x0c, LVL_1_DATA, 16 },	/* 4-way set assoc, 32 byte line size */
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	{ 0x0d, LVL_1_DATA, 16 },	/* 4-way set assoc, 64 byte line size */
	{ 0x21, LVL_2,      256 },	/* 8-way set assoc, 64 byte line size */
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	{ 0x22, LVL_3,      512 },	/* 4-way set assoc, sectored cache, 64 byte line size */
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	{ 0x23, LVL_3,      MB(1) },	/* 8-way set assoc, sectored cache, 64 byte line size */
	{ 0x25, LVL_3,      MB(2) },	/* 8-way set assoc, sectored cache, 64 byte line size */
	{ 0x29, LVL_3,      MB(4) },	/* 8-way set assoc, sectored cache, 64 byte line size */
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	{ 0x2c, LVL_1_DATA, 32 },	/* 8-way set assoc, 64 byte line size */
	{ 0x30, LVL_1_INST, 32 },	/* 8-way set assoc, 64 byte line size */
	{ 0x39, LVL_2,      128 },	/* 4-way set assoc, sectored cache, 64 byte line size */
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	{ 0x3a, LVL_2,      192 },	/* 6-way set assoc, sectored cache, 64 byte line size */
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	{ 0x3b, LVL_2,      128 },	/* 2-way set assoc, sectored cache, 64 byte line size */
	{ 0x3c, LVL_2,      256 },	/* 4-way set assoc, sectored cache, 64 byte line size */
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	{ 0x3d, LVL_2,      384 },	/* 6-way set assoc, sectored cache, 64 byte line size */
	{ 0x3e, LVL_2,      512 },	/* 4-way set assoc, sectored cache, 64 byte line size */
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	{ 0x3f, LVL_2,      256 },	/* 2-way set assoc, 64 byte line size */
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	{ 0x41, LVL_2,      128 },	/* 4-way set assoc, 32 byte line size */
	{ 0x42, LVL_2,      256 },	/* 4-way set assoc, 32 byte line size */
	{ 0x43, LVL_2,      512 },	/* 4-way set assoc, 32 byte line size */
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	{ 0x44, LVL_2,      MB(1) },	/* 4-way set assoc, 32 byte line size */
	{ 0x45, LVL_2,      MB(2) },	/* 4-way set assoc, 32 byte line size */
	{ 0x46, LVL_3,      MB(4) },	/* 4-way set assoc, 64 byte line size */
	{ 0x47, LVL_3,      MB(8) },	/* 8-way set assoc, 64 byte line size */
	{ 0x49, LVL_3,      MB(4) },	/* 16-way set assoc, 64 byte line size */
	{ 0x4a, LVL_3,      MB(6) },	/* 12-way set assoc, 64 byte line size */
	{ 0x4b, LVL_3,      MB(8) },	/* 16-way set assoc, 64 byte line size */
	{ 0x4c, LVL_3,      MB(12) },	/* 12-way set assoc, 64 byte line size */
	{ 0x4d, LVL_3,      MB(16) },	/* 16-way set assoc, 64 byte line size */
	{ 0x4e, LVL_2,      MB(6) },	/* 24-way set assoc, 64 byte line size */
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	{ 0x60, LVL_1_DATA, 16 },	/* 8-way set assoc, sectored cache, 64 byte line size */
	{ 0x66, LVL_1_DATA, 8 },	/* 4-way set assoc, sectored cache, 64 byte line size */
	{ 0x67, LVL_1_DATA, 16 },	/* 4-way set assoc, sectored cache, 64 byte line size */
	{ 0x68, LVL_1_DATA, 32 },	/* 4-way set assoc, sectored cache, 64 byte line size */
	{ 0x70, LVL_TRACE,  12 },	/* 8-way set assoc */
	{ 0x71, LVL_TRACE,  16 },	/* 8-way set assoc */
	{ 0x72, LVL_TRACE,  32 },	/* 8-way set assoc */
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	{ 0x73, LVL_TRACE,  64 },	/* 8-way set assoc */
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	{ 0x78, LVL_2,      MB(1) },	/* 4-way set assoc, 64 byte line size */
	{ 0x79, LVL_2,      128 },	/* 8-way set assoc, sectored cache, 64 byte line size */
	{ 0x7a, LVL_2,      256 },	/* 8-way set assoc, sectored cache, 64 byte line size */
	{ 0x7b, LVL_2,      512 },	/* 8-way set assoc, sectored cache, 64 byte line size */
	{ 0x7c, LVL_2,      MB(1) },	/* 8-way set assoc, sectored cache, 64 byte line size */
	{ 0x7d, LVL_2,      MB(2) },	/* 8-way set assoc, 64 byte line size */
	{ 0x7f, LVL_2,      512 },	/* 2-way set assoc, 64 byte line size */
	{ 0x82, LVL_2,      256 },	/* 8-way set assoc, 32 byte line size */
	{ 0x83, LVL_2,      512 },	/* 8-way set assoc, 32 byte line size */
	{ 0x84, LVL_2,      MB(1) },	/* 8-way set assoc, 32 byte line size */
	{ 0x85, LVL_2,      MB(2) },	/* 8-way set assoc, 32 byte line size */
	{ 0x86, LVL_2,      512 },	/* 4-way set assoc, 64 byte line size */
	{ 0x87, LVL_2,      MB(1) },	/* 8-way set assoc, 64 byte line size */
	{ 0xd0, LVL_3,      512 },	/* 4-way set assoc, 64 byte line size */
	{ 0xd1, LVL_3,      MB(1) },	/* 4-way set assoc, 64 byte line size */
	{ 0xd2, LVL_3,      MB(2) },	/* 4-way set assoc, 64 byte line size */
	{ 0xd6, LVL_3,      MB(1) },	/* 8-way set assoc, 64 byte line size */
	{ 0xd7, LVL_3,      MB(2) },	/* 8-way set assoc, 64 byte line size */
	{ 0xd8, LVL_3,      MB(4) },	/* 12-way set assoc, 64 byte line size */
	{ 0xdc, LVL_3,      MB(2) },	/* 12-way set assoc, 64 byte line size */
	{ 0xdd, LVL_3,      MB(4) },	/* 12-way set assoc, 64 byte line size */
	{ 0xde, LVL_3,      MB(8) },	/* 12-way set assoc, 64 byte line size */
	{ 0xe2, LVL_3,      MB(2) },	/* 16-way set assoc, 64 byte line size */
	{ 0xe3, LVL_3,      MB(4) },	/* 16-way set assoc, 64 byte line size */
	{ 0xe4, LVL_3,      MB(8) },	/* 16-way set assoc, 64 byte line size */
	{ 0xea, LVL_3,      MB(12) },	/* 24-way set assoc, 64 byte line size */
	{ 0xeb, LVL_3,      MB(18) },	/* 24-way set assoc, 64 byte line size */
	{ 0xec, LVL_3,      MB(24) },	/* 24-way set assoc, 64 byte line size */
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	{ 0x00, 0, 0}
};


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enum _cache_type {
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	CACHE_TYPE_NULL	= 0,
	CACHE_TYPE_DATA = 1,
	CACHE_TYPE_INST = 2,
	CACHE_TYPE_UNIFIED = 3
};

union _cpuid4_leaf_eax {
	struct {
		enum _cache_type	type:5;
		unsigned int		level:3;
		unsigned int		is_self_initializing:1;
		unsigned int		is_fully_associative:1;
		unsigned int		reserved:4;
		unsigned int		num_threads_sharing:12;
		unsigned int		num_cores_on_die:6;
	} split;
	u32 full;
};

union _cpuid4_leaf_ebx {
	struct {
		unsigned int		coherency_line_size:12;
		unsigned int		physical_line_partition:10;
		unsigned int		ways_of_associativity:10;
	} split;
	u32 full;
};

union _cpuid4_leaf_ecx {
	struct {
		unsigned int		number_of_sets:32;
	} split;
	u32 full;
};

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struct amd_l3_cache {
	struct	 pci_dev *dev;
	bool	 can_disable;
	unsigned indices;
	u8	 subcaches[4];
};

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struct _cpuid4_info {
	union _cpuid4_leaf_eax eax;
	union _cpuid4_leaf_ebx ebx;
	union _cpuid4_leaf_ecx ecx;
	unsigned long size;
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	struct amd_l3_cache *l3;
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	DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
};

/* subset of above _cpuid4_info w/o shared_cpu_map */
struct _cpuid4_info_regs {
	union _cpuid4_leaf_eax eax;
	union _cpuid4_leaf_ebx ebx;
	union _cpuid4_leaf_ecx ecx;
	unsigned long size;
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	struct amd_l3_cache *l3;
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};

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unsigned short			num_cache_leaves;

/* AMD doesn't have CPUID4. Emulate it here to report the same
   information to the user.  This makes some assumptions about the machine:
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   L2 not shared, no SMT etc. that is currently true on AMD CPUs.
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   In theory the TLBs could be reported as fake type (they are in "dummy").
   Maybe later */
union l1_cache {
	struct {
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		unsigned line_size:8;
		unsigned lines_per_tag:8;
		unsigned assoc:8;
		unsigned size_in_kb:8;
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	};
	unsigned val;
};

union l2_cache {
	struct {
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		unsigned line_size:8;
		unsigned lines_per_tag:4;
		unsigned assoc:4;
		unsigned size_in_kb:16;
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	};
	unsigned val;
};

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union l3_cache {
	struct {
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		unsigned line_size:8;
		unsigned lines_per_tag:4;
		unsigned assoc:4;
		unsigned res:2;
		unsigned size_encoded:14;
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	};
	unsigned val;
};

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static const unsigned short __cpuinitconst assocs[] = {
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	[1] = 1,
	[2] = 2,
	[4] = 4,
	[6] = 8,
	[8] = 16,
	[0xa] = 32,
	[0xb] = 48,
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	[0xc] = 64,
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	[0xd] = 96,
	[0xe] = 128,
	[0xf] = 0xffff /* fully associative - no way to show this currently */
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};

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static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
static const unsigned char __cpuinitconst types[] = { 1, 2, 3, 3 };
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static void __cpuinit
amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
		     union _cpuid4_leaf_ebx *ebx,
		     union _cpuid4_leaf_ecx *ecx)
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{
	unsigned dummy;
	unsigned line_size, lines_per_tag, assoc, size_in_kb;
	union l1_cache l1i, l1d;
	union l2_cache l2;
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	union l3_cache l3;
	union l1_cache *l1 = &l1d;
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	eax->full = 0;
	ebx->full = 0;
	ecx->full = 0;

	cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
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	cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
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	switch (leaf) {
	case 1:
		l1 = &l1i;
	case 0:
		if (!l1->val)
			return;
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		assoc = assocs[l1->assoc];
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		line_size = l1->line_size;
		lines_per_tag = l1->lines_per_tag;
		size_in_kb = l1->size_in_kb;
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		break;
	case 2:
		if (!l2.val)
			return;
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		assoc = assocs[l2.assoc];
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		line_size = l2.line_size;
		lines_per_tag = l2.lines_per_tag;
		/* cpu_data has errata corrections for K7 applied */
		size_in_kb = current_cpu_data.x86_cache_size;
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		break;
	case 3:
		if (!l3.val)
			return;
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		assoc = assocs[l3.assoc];
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		line_size = l3.line_size;
		lines_per_tag = l3.lines_per_tag;
		size_in_kb = l3.size_encoded * 512;
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		if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
			size_in_kb = size_in_kb >> 1;
			assoc = assoc >> 1;
		}
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		break;
	default:
		return;
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	}

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	eax->split.is_self_initializing = 1;
	eax->split.type = types[leaf];
	eax->split.level = levels[leaf];
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	eax->split.num_threads_sharing = 0;
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	eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;


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	if (assoc == 0xffff)
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		eax->split.is_fully_associative = 1;
	ebx->split.coherency_line_size = line_size - 1;
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	ebx->split.ways_of_associativity = assoc - 1;
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	ebx->split.physical_line_partition = lines_per_tag - 1;
	ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
		(ebx->split.ways_of_associativity + 1) - 1;
}
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struct _cache_attr {
	struct attribute attr;
	ssize_t (*show)(struct _cpuid4_info *, char *);
	ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
};

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#ifdef CONFIG_AMD_NB
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/*
 * L3 cache descriptors
 */
static struct amd_l3_cache **__cpuinitdata l3_caches;

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static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
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{
	unsigned int sc0, sc1, sc2, sc3;
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	u32 val = 0;
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	pci_read_config_dword(l3->dev, 0x1C4, &val);
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	/* calculate subcache sizes */
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	l3->subcaches[0] = sc0 = !(val & BIT(0));
	l3->subcaches[1] = sc1 = !(val & BIT(4));
	l3->subcaches[2] = sc2 = !(val & BIT(8))  + !(val & BIT(9));
	l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));

	l3->indices = (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
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	l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
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}

static struct amd_l3_cache * __cpuinit amd_init_l3_cache(int node)
{
	struct amd_l3_cache *l3;
	struct pci_dev *dev = node_to_k8_nb_misc(node);

	l3 = kzalloc(sizeof(struct amd_l3_cache), GFP_ATOMIC);
	if (!l3) {
		printk(KERN_WARNING "Error allocating L3 struct\n");
		return NULL;
	}
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	l3->dev = dev;
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	amd_calc_l3_indices(l3);

	return l3;
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}

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static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
					   int index)
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{
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	int node;

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	if (boot_cpu_data.x86 != 0x10)
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		return;
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	if (index < 3)
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		return;

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	/* see errata #382 and #388 */
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	if (boot_cpu_data.x86_model < 0x8)
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		return;

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	if ((boot_cpu_data.x86_model == 0x8 ||
	     boot_cpu_data.x86_model == 0x9)
		&&
	     boot_cpu_data.x86_mask < 0x1)
			return;

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	/* not in virtualized environments */
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	if (k8_northbridges.num == 0)
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		return;

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	/*
	 * Strictly speaking, the amount in @size below is leaked since it is
	 * never freed but this is done only on shutdown so it doesn't matter.
	 */
	if (!l3_caches) {
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		int size = k8_northbridges.num * sizeof(struct amd_l3_cache *);
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		l3_caches = kzalloc(size, GFP_ATOMIC);
		if (!l3_caches)
			return;
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	}

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	node = amd_get_nb_id(smp_processor_id());

	if (!l3_caches[node]) {
		l3_caches[node] = amd_init_l3_cache(node);
		l3_caches[node]->can_disable = true;
	}

	WARN_ON(!l3_caches[node]);

	this_leaf->l3 = l3_caches[node];
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}

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/*
 * check whether a slot used for disabling an L3 index is occupied.
 * @l3: L3 cache descriptor
 * @slot: slot number (0..1)
 *
 * @returns: the disabled index if used or negative value if slot free.
 */
int amd_get_l3_disable_slot(struct amd_l3_cache *l3, unsigned slot)
{
	unsigned int reg = 0;

	pci_read_config_dword(l3->dev, 0x1BC + slot * 4, &reg);

	/* check whether this slot is activated already */
	if (reg & (3UL << 30))
		return reg & 0xfff;

	return -1;
}

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static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
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				  unsigned int slot)
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{
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	int index;
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	if (!this_leaf->l3 || !this_leaf->l3->can_disable)
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		return -EINVAL;

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	index = amd_get_l3_disable_slot(this_leaf->l3, slot);
	if (index >= 0)
		return sprintf(buf, "%d\n", index);
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	return sprintf(buf, "FREE\n");
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}

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#define SHOW_CACHE_DISABLE(slot)					\
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static ssize_t								\
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show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf)	\
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{									\
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	return show_cache_disable(this_leaf, buf, slot);		\
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}
SHOW_CACHE_DISABLE(0)
SHOW_CACHE_DISABLE(1)

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static void amd_l3_disable_index(struct amd_l3_cache *l3, int cpu,
				 unsigned slot, unsigned long idx)
{
	int i;

	idx |= BIT(30);

	/*
	 *  disable index in all 4 subcaches
	 */
	for (i = 0; i < 4; i++) {
		u32 reg = idx | (i << 20);

		if (!l3->subcaches[i])
			continue;

		pci_write_config_dword(l3->dev, 0x1BC + slot * 4, reg);

		/*
		 * We need to WBINVD on a core on the node containing the L3
		 * cache which indices we disable therefore a simple wbinvd()
		 * is not sufficient.
		 */
		wbinvd_on_cpu(cpu);

		reg |= BIT(31);
		pci_write_config_dword(l3->dev, 0x1BC + slot * 4, reg);
	}
}

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/*
 * disable a L3 cache index by using a disable-slot
 *
 * @l3:    L3 cache descriptor
 * @cpu:   A CPU on the node containing the L3 cache
 * @slot:  slot number (0..1)
 * @index: index to disable
 *
 * @return: 0 on success, error status on failure
 */
int amd_set_l3_disable_slot(struct amd_l3_cache *l3, int cpu, unsigned slot,
			    unsigned long index)
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{
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	int ret = 0;
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#define SUBCACHE_MASK	(3UL << 20)
#define SUBCACHE_INDEX	0xfff

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	/*
	 * check whether this slot is already used or
	 * the index is already disabled
	 */
	ret = amd_get_l3_disable_slot(l3, slot);
	if (ret >= 0)
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		return -EINVAL;

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	/*
	 * check whether the other slot has disabled the
	 * same index already
	 */
	if (index == amd_get_l3_disable_slot(l3, !slot))
		return -EINVAL;

	/* do not allow writes outside of allowed bits */
	if ((index & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
	    ((index & SUBCACHE_INDEX) > l3->indices))
		return -EINVAL;

	amd_l3_disable_index(l3, cpu, slot, index);

	return 0;
}

static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
				  const char *buf, size_t count,
				  unsigned int slot)
{
	unsigned long val = 0;
	int cpu, err = 0;

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	if (!capable(CAP_SYS_ADMIN))
		return -EPERM;

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	if (!this_leaf->l3 || !this_leaf->l3->can_disable)
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		return -EINVAL;

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	cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
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	if (strict_strtoul(buf, 10, &val) < 0)
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		return -EINVAL;

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	err = amd_set_l3_disable_slot(this_leaf->l3, cpu, slot, val);
	if (err) {
		if (err == -EEXIST)
			printk(KERN_WARNING "L3 disable slot %d in use!\n",
					    slot);
		return err;
	}
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	return count;
}

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#define STORE_CACHE_DISABLE(slot)					\
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static ssize_t								\
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store_cache_disable_##slot(struct _cpuid4_info *this_leaf,		\
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			    const char *buf, size_t count)		\
{									\
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	return store_cache_disable(this_leaf, buf, count, slot);	\
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}
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STORE_CACHE_DISABLE(0)
STORE_CACHE_DISABLE(1)

static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
		show_cache_disable_0, store_cache_disable_0);
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
		show_cache_disable_1, store_cache_disable_1);

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#else	/* CONFIG_AMD_NB */
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static void __cpuinit
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amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)
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{
};
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#endif /* CONFIG_AMD_NB */
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static int
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__cpuinit cpuid4_cache_lookup_regs(int index,
				   struct _cpuid4_info_regs *this_leaf)
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{
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	union _cpuid4_leaf_eax 	eax;
	union _cpuid4_leaf_ebx 	ebx;
	union _cpuid4_leaf_ecx 	ecx;
	unsigned		edx;
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	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
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		amd_cpuid4(index, &eax, &ebx, &ecx);
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		amd_check_l3_disable(this_leaf, index);
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	} else {
		cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
	}

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	if (eax.split.type == CACHE_TYPE_NULL)
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		return -EIO; /* better error ? */
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	this_leaf->eax = eax;
	this_leaf->ebx = ebx;
	this_leaf->ecx = ecx;
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	this_leaf->size = (ecx.split.number_of_sets          + 1) *
			  (ebx.split.coherency_line_size     + 1) *
			  (ebx.split.physical_line_partition + 1) *
			  (ebx.split.ways_of_associativity   + 1);
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	return 0;
}

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static int __cpuinit find_num_cache_leaves(void)
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{
	unsigned int		eax, ebx, ecx, edx;
	union _cpuid4_leaf_eax	cache_eax;
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	int 			i = -1;
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	do {
		++i;
		/* Do cpuid(4) loop to find out num_cache_leaves */
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		cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
		cache_eax.full = eax;
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	} while (cache_eax.split.type != CACHE_TYPE_NULL);
	return i;
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}

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unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
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{
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	/* Cache sizes */
	unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
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	unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
	unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
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	unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
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#ifdef CONFIG_X86_HT
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	unsigned int cpu = c->cpu_index;
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#endif
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	if (c->cpuid_level > 3) {
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		static int is_initialized;

		if (is_initialized == 0) {
			/* Init num_cache_leaves from boot CPU */
			num_cache_leaves = find_num_cache_leaves();
			is_initialized++;
		}

		/*
		 * Whenever possible use cpuid(4), deterministic cache
		 * parameters cpuid leaf to find the cache details
		 */
		for (i = 0; i < num_cache_leaves; i++) {
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			struct _cpuid4_info_regs this_leaf;
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			int retval;

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			retval = cpuid4_cache_lookup_regs(i, &this_leaf);
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			if (retval >= 0) {
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				switch (this_leaf.eax.split.level) {
				case 1:
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					if (this_leaf.eax.split.type ==
							CACHE_TYPE_DATA)
						new_l1d = this_leaf.size/1024;
					else if (this_leaf.eax.split.type ==
							CACHE_TYPE_INST)
						new_l1i = this_leaf.size/1024;
					break;
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				case 2:
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					new_l2 = this_leaf.size/1024;
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					num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
					index_msb = get_count_order(num_threads_sharing);
					l2_id = c->apicid >> index_msb;
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					break;
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				case 3:
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					new_l3 = this_leaf.size/1024;
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					num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
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					index_msb = get_count_order(
							num_threads_sharing);
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					l3_id = c->apicid >> index_msb;
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					break;
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				default:
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					break;
				}
			}
		}
	}
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	/*
	 * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
	 * trace cache
	 */
	if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
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		/* supports eax=2  call */
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		int j, n;
		unsigned int regs[4];
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		unsigned char *dp = (unsigned char *)regs;
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		int only_trace = 0;

		if (num_cache_leaves != 0 && c->x86 == 15)
			only_trace = 1;
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		/* Number of times to iterate */
		n = cpuid_eax(2) & 0xFF;

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		for (i = 0 ; i < n ; i++) {
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			cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);

			/* If bit 31 is set, this is an unknown format */
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			for (j = 0 ; j < 3 ; j++)
				if (regs[j] & (1 << 31))
					regs[j] = 0;
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			/* Byte 0 is level count, not a descriptor */
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			for (j = 1 ; j < 16 ; j++) {
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				unsigned char des = dp[j];
				unsigned char k = 0;

				/* look up this descriptor in the table */
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				while (cache_table[k].descriptor != 0) {
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					if (cache_table[k].descriptor == des) {
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						if (only_trace && cache_table[k].cache_type != LVL_TRACE)
							break;
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						switch (cache_table[k].cache_type) {
						case LVL_1_INST:
							l1i += cache_table[k].size;
							break;
						case LVL_1_DATA:
							l1d += cache_table[k].size;
							break;
						case LVL_2:
							l2 += cache_table[k].size;
							break;
						case LVL_3:
							l3 += cache_table[k].size;
							break;
						case LVL_TRACE:
							trace += cache_table[k].size;
							break;
						}

						break;
					}

					k++;
				}
			}
		}
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	}
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	if (new_l1d)
		l1d = new_l1d;
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	if (new_l1i)
		l1i = new_l1i;
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	if (new_l2) {
		l2 = new_l2;
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#ifdef CONFIG_X86_HT
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		per_cpu(cpu_llc_id, cpu) = l2_id;
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#endif
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	}
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	if (new_l3) {
		l3 = new_l3;
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#ifdef CONFIG_X86_HT
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		per_cpu(cpu_llc_id, cpu) = l3_id;
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#endif
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	}

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	c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));

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	return l2;
}

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#ifdef CONFIG_SYSFS

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/* pointer to _cpuid4_info array (for each cache leaf) */
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static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
#define CPUID4_INFO_IDX(x, y)	(&((per_cpu(ici_cpuid4_info, x))[y]))
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#ifdef CONFIG_SMP
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static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
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{
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	struct _cpuid4_info	*this_leaf, *sibling_leaf;
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	unsigned long num_threads_sharing;
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	int index_msb, i, sibling;
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	struct cpuinfo_x86 *c = &cpu_data(cpu);
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	if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
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		for_each_cpu(i, c->llc_shared_map) {
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			if (!per_cpu(ici_cpuid4_info, i))
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				continue;
			this_leaf = CPUID4_INFO_IDX(i, index);
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			for_each_cpu(sibling, c->llc_shared_map) {
				if (!cpu_online(sibling))
					continue;
				set_bit(sibling, this_leaf->shared_cpu_map);
			}
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		}
		return;
	}
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	this_leaf = CPUID4_INFO_IDX(cpu, index);
	num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;

	if (num_threads_sharing == 1)
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		cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
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	else {
		index_msb = get_count_order(num_threads_sharing);

		for_each_online_cpu(i) {
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			if (cpu_data(i).apicid >> index_msb ==
			    c->apicid >> index_msb) {
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				cpumask_set_cpu(i,
					to_cpumask(this_leaf->shared_cpu_map));
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				if (i != cpu && per_cpu(ici_cpuid4_info, i))  {
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					sibling_leaf =
						CPUID4_INFO_IDX(i, index);
					cpumask_set_cpu(cpu, to_cpumask(
						sibling_leaf->shared_cpu_map));
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				}
			}
		}
	}
}
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static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
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{
	struct _cpuid4_info	*this_leaf, *sibling_leaf;
	int sibling;

	this_leaf = CPUID4_INFO_IDX(cpu, index);
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	for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
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		sibling_leaf = CPUID4_INFO_IDX(sibling, index);
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		cpumask_clear_cpu(cpu,
				  to_cpumask(sibling_leaf->shared_cpu_map));
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	}
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}
#else
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static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
{
}

static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
{
}
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#endif

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static void __cpuinit free_cache_attributes(unsigned int cpu)
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{
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	int i;

	for (i = 0; i < num_cache_leaves; i++)
		cache_remove_shared_cpu_map(cpu, i);

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	kfree(per_cpu(ici_cpuid4_info, cpu)->l3);
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	kfree(per_cpu(ici_cpuid4_info, cpu));
	per_cpu(ici_cpuid4_info, cpu) = NULL;
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}

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static int
__cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
{
	struct _cpuid4_info_regs *leaf_regs =
		(struct _cpuid4_info_regs *)this_leaf;

	return cpuid4_cache_lookup_regs(index, leaf_regs);
}

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static void __cpuinit get_cpu_leaves(void *_retval)
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{
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	int j, *retval = _retval, cpu = smp_processor_id();
852

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	/* Do cpuid and store the results */
	for (j = 0; j < num_cache_leaves; j++) {
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		struct _cpuid4_info *this_leaf;
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		this_leaf = CPUID4_INFO_IDX(cpu, j);
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		*retval = cpuid4_cache_lookup(j, this_leaf);
		if (unlikely(*retval < 0)) {
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			int i;

			for (i = 0; i < j; i++)
				cache_remove_shared_cpu_map(cpu, i);
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			break;
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		}
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		cache_shared_cpu_map_setup(cpu, j);
	}
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}

static int __cpuinit detect_cache_attributes(unsigned int cpu)
{
	int			retval;

	if (num_cache_leaves == 0)
		return -ENOENT;

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	per_cpu(ici_cpuid4_info, cpu) = kzalloc(
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	    sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
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	if (per_cpu(ici_cpuid4_info, cpu) == NULL)
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		return -ENOMEM;
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	smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
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	if (retval) {
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		kfree(per_cpu(ici_cpuid4_info, cpu));
		per_cpu(ici_cpuid4_info, cpu) = NULL;
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	}

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	return retval;
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}

#include <linux/kobject.h>
#include <linux/sysfs.h>

extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */

/* pointer to kobject for cpuX/cache */
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static DEFINE_PER_CPU(struct kobject *, ici_cache_kobject);
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struct _index_kobject {
	struct kobject kobj;
	unsigned int cpu;
	unsigned short index;
};

/* pointer to array of kobjects for cpuX/cache/indexY */
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static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject);
#define INDEX_KOBJECT_PTR(x, y)		(&((per_cpu(ici_index_kobject, x))[y]))
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#define show_one_plus(file_name, object, val)				\
static ssize_t show_##file_name						\
			(struct _cpuid4_info *this_leaf, char *buf)	\
{									\
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	return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
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}

show_one_plus(level, eax.split.level, 0);
show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);

static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
{
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	return sprintf(buf, "%luK\n", this_leaf->size / 1024);
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}

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static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
					int type, char *buf)
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{
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	ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
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	int n = 0;

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	if (len > 1) {
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		const struct cpumask *mask;
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		mask = to_cpumask(this_leaf->shared_cpu_map);
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		n = type ?
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			cpulist_scnprintf(buf, len-2, mask) :
			cpumask_scnprintf(buf, len-2, mask);
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		buf[n++] = '\n';
		buf[n] = '\0';
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	}
	return n;
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}

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static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
{
	return show_shared_cpu_map_func(leaf, 0, buf);
}

static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
{
	return show_shared_cpu_map_func(leaf, 1, buf);
}

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static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
{
	switch (this_leaf->eax.split.type) {
	case CACHE_TYPE_DATA:
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		return sprintf(buf, "Data\n");
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	case CACHE_TYPE_INST:
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		return sprintf(buf, "Instruction\n");
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	case CACHE_TYPE_UNIFIED:
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		return sprintf(buf, "Unified\n");
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	default:
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		return sprintf(buf, "Unknown\n");
	}
}

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#define to_object(k)	container_of(k, struct _index_kobject, kobj)
#define to_attr(a)	container_of(a, struct _cache_attr, attr)
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#define define_one_ro(_name) \
static struct _cache_attr _name = \
	__ATTR(_name, 0444, show_##_name, NULL)

define_one_ro(level);
define_one_ro(type);
define_one_ro(coherency_line_size);
define_one_ro(physical_line_partition);
define_one_ro(ways_of_associativity);
define_one_ro(number_of_sets);
define_one_ro(size);
define_one_ro(shared_cpu_map);
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define_one_ro(shared_cpu_list);
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#define DEFAULT_SYSFS_CACHE_ATTRS	\
	&type.attr,			\
	&level.attr,			\
	&coherency_line_size.attr,	\
	&physical_line_partition.attr,	\
	&ways_of_associativity.attr,	\
	&number_of_sets.attr,		\
	&size.attr,			\
	&shared_cpu_map.attr,		\
	&shared_cpu_list.attr
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static struct attribute *default_attrs[] = {
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	DEFAULT_SYSFS_CACHE_ATTRS,
	NULL
};

static struct attribute *default_l3_attrs[] = {
	DEFAULT_SYSFS_CACHE_ATTRS,
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#ifdef CONFIG_AMD_NB
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	&cache_disable_0.attr,
	&cache_disable_1.attr,
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#endif
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	NULL
};

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static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
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{
	struct _cache_attr *fattr = to_attr(attr);
	struct _index_kobject *this_leaf = to_object(kobj);
	ssize_t ret;

	ret = fattr->show ?
		fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
			buf) :
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		0;
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	return ret;
}

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static ssize_t store(struct kobject *kobj, struct attribute *attr,
		     const char *buf, size_t count)
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{
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	struct _cache_attr *fattr = to_attr(attr);
	struct _index_kobject *this_leaf = to_object(kobj);
	ssize_t ret;

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	ret = fattr->store ?
		fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
			buf, count) :
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		0;
	return ret;
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}

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static const struct sysfs_ops sysfs_ops = {
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	.show   = show,
	.store  = store,
};

static struct kobj_type ktype_cache = {
	.sysfs_ops	= &sysfs_ops,
	.default_attrs	= default_attrs,
};

static struct kobj_type ktype_percpu_entry = {
	.sysfs_ops	= &sysfs_ops,
};

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static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
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{
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	kfree(per_cpu(ici_cache_kobject, cpu));
	kfree(per_cpu(ici_index_kobject, cpu));
	per_cpu(ici_cache_kobject, cpu) = NULL;
	per_cpu(ici_index_kobject, cpu) = NULL;
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	free_cache_attributes(