• Andrew Waterman's avatar
    RISC-V: Flush I$ when making a dirty page executable · 08f051ed
    Andrew Waterman authored
    The RISC-V ISA allows for instruction caches that are not coherent WRT
    stores, even on a single hart.  As a result, we need to explicitly flush
    the instruction cache whenever marking a dirty page as executable in
    order to preserve the correct system behavior.
    Local instruction caches aren't that scary (our implementations actually
    flush the cache, but RISC-V is defined to allow higher-performance
    implementations to exist), but RISC-V defines no way to perform an
    instruction cache shootdown.  When explicitly asked to do so we can
    shoot down remote instruction caches via an IPI, but this is a bit on
    the slow side.
    Instead of requiring an IPI to all harts whenever marking a page as
    executable, we simply flush the currently running harts.  In order to
    maintain correct behavior, we additionally mark every other hart as
    needing a deferred instruction cache which will be taken before anything
    runs on it.
    Signed-off-by: default avatarAndrew Waterman <andrew@sifive.com>
    Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
mmu.h 829 Bytes