Commit 5c7b0c4e authored by Linus Walleij's avatar Linus Walleij

gpio: grgpio: Do not use gc->pin2mask()

The pin2mask() accessor only shuffles BIT ORDER in big endian systems,
i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or
bit 15 or bit 31 or so.

The grgpio only uses big endian BYTE ORDER which will be taken car of
by the ->write_reg() callback.

Just use BIT(offset) to assign the bit.
Acked-by: default avatarAndreas Larsson <andreas@gaisler.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent fe29416b
......@@ -35,6 +35,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/bitops.h>
#define GRGPIO_MAX_NGPIO 32
......@@ -96,12 +97,11 @@ static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
int val)
{
struct gpio_chip *gc = &priv->gc;
unsigned long mask = gc->pin2mask(gc, offset);
if (val)
priv->imask |= mask;
priv->imask |= BIT(offset);
else
priv->imask &= ~mask;
priv->imask &= ~BIT(offset);
gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
}
......
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