Commit b595076a authored by Uwe Kleine-König's avatar Uwe Kleine-König Committed by Jiri Kosina
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tree-wide: fix comment/printk typos



"gadget", "through", "command", "maintain", "maintain", "controller", "address",
"between", "initiali[zs]e", "instead", "function", "select", "already",
"equal", "access", "management", "hierarchy", "registration", "interest",
"relative", "memory", "offset", "already",
Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: default avatarJiri Kosina <jkosina@suse.cz>
parent 6aaccece
......@@ -250,7 +250,7 @@ static void board_hwcontrol(struct mtd_info *mtd, int cmd)
<title>Device ready function</title>
<para>
If the hardware interface has the ready busy pin of the NAND chip connected to a
GPIO or other accesible I/O pin, this function is used to read back the state of the
GPIO or other accessible I/O pin, this function is used to read back the state of the
pin. The function has no arguments and should return 0, if the device is busy (R/B pin
is low) and 1, if the device is ready (R/B pin is high).
If the hardware interface does not give access to the ready busy pin, then
......
......@@ -91,7 +91,7 @@ int main(int argc, char **argv)
if (ret == -1) {
perror("cgroup.event_control "
"is not accessable any more");
"is not accessible any more");
break;
}
......
......@@ -398,7 +398,7 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y.
written to move_charge_at_immigrate.
9.10 Memory thresholds
Memory controler implements memory thresholds using cgroups notification
Memory controller implements memory thresholds using cgroups notification
API. You can use Documentation/cgroups/cgroup_event_listener.c to test
it.
......
......@@ -598,7 +598,7 @@ a 5-byte jump instruction. So there are several limitations.
a) The instructions in DCR must be relocatable.
b) The instructions in DCR must not include a call instruction.
c) JTPR must not be targeted by any jump or call instruction.
d) DCR must not straddle the border betweeen functions.
d) DCR must not straddle the border between functions.
Anyway, these limitations are checked by the in-kernel instruction
decoder, so you don't need to worry about that.
......
......@@ -874,7 +874,7 @@ Possible values are:
- KVM_MP_STATE_HALTED: the vcpu has executed a HLT instruction and
is waiting for an interrupt
- KVM_MP_STATE_SIPI_RECEIVED: the vcpu has just received a SIPI (vector
accesible via KVM_GET_VCPU_EVENTS)
accessible via KVM_GET_VCPU_EVENTS)
This ioctl is only useful after KVM_CREATE_IRQCHIP. Without an in-kernel
irqchip, the multiprocessing state must be maintained by userspace.
......
......@@ -32,7 +32,7 @@ the physical hardware, both with regard to SPI and to GPIOs.
This function is called by the CAIF SPI interface to give
you a chance to set up your hardware to be ready to receive
a stream of data from the master. The xfer structure contains
both physical and logical adresses, as well as the total length
both physical and logical addresses, as well as the total length
of the transfer in both directions.The dev parameter can be used
to map to different CAIF SPI slave devices.
......
......@@ -1098,7 +1098,7 @@ supported currently at the toplevel.
* an arbitrary array of bytes
*/
childnode@addresss { /* define a child node named "childnode"
childnode@address { /* define a child node named "childnode"
* whose unit name is "childnode at
* address"
*/
......
......@@ -573,7 +573,7 @@ Changes from 20041018 to 20041123
* Backround nodev_timeout processing to DPC This enables us to
unblock (stop dev_loss_tmo) when appopriate.
* Fix array discovery with multiple luns. The max_luns was 0 at
the time the host structure was intialized. lpfc_cfg_params
the time the host structure was initialized. lpfc_cfg_params
then set the max_luns to the correct value afterwards.
* Remove unused define LPFC_MAX_LUN and set the default value of
lpfc_max_lun parameter to 512.
......
......@@ -19,7 +19,7 @@ Linux system over a sample period:
- the pid of the task(process) which initialized the timer
- the name of the process which initialized the timer
- the function where the timer was intialized
- the function where the timer was initialized
- the callback function which is associated to the timer
- the number of events (callbacks)
......
......@@ -236,7 +236,7 @@ static struct resource it8152_mem = {
/*
* The following functions are needed for DMA bouncing.
* ITE8152 chip can addrees up to 64MByte, so all the devices
* ITE8152 chip can address up to 64MByte, so all the devices
* connected to ITE8152 (PCI and USB) should have limited DMA window
*/
......
......@@ -70,7 +70,7 @@ static inline struct vic_device *to_vic(struct sys_device *sys)
* vic_init2 - common initialisation code
* @base: Base of the VIC.
*
* Common initialisation code for registeration
* Common initialisation code for registration
* and resume.
*/
static void vic_init2(void __iomem *base)
......
......@@ -128,17 +128,17 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
.platform_data = &my_flash0_platform,
#endif
},
{ /* User accessable spi - cs1 (250KHz) */
{ /* User accessible spi - cs1 (250KHz) */
.modalias = "spi-cs1",
.chip_select = 1,
.max_speed_hz = 250 * 1000,
},
{ /* User accessable spi - cs2 (1MHz) */
{ /* User accessible spi - cs2 (1MHz) */
.modalias = "spi-cs2",
.chip_select = 2,
.max_speed_hz = 1 * 1000 * 1000,
},
{ /* User accessable spi - cs3 (10MHz) */
{ /* User accessible spi - cs3 (10MHz) */
.modalias = "spi-cs3",
.chip_select = 3,
.max_speed_hz = 10 * 1000 * 1000,
......
......@@ -757,7 +757,7 @@ static int chipcHw_divide(int num, int denom)
t = t << 1;
}
/* Intialize the result */
/* Initialize the result */
r = 0;
do {
......
......@@ -893,7 +893,7 @@ int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration
*/
/****************************************************************************/
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
) {
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
......
......@@ -316,7 +316,7 @@ static void DisplayDescRing(void *pDescriptor, /* [ IN ] Descriptor buffer */
/**
* @brief Check if DMA channel is the flow controller
*
* @return 1 : If DMA is a flow controler
* @return 1 : If DMA is a flow controller
* 0 : Peripheral is the flow controller
*
* @note
......
......@@ -558,7 +558,7 @@ static int tmrHw_divide(int num, int denom)
t = t << 1;
}
/* Intialize the result */
/* Initialize the result */
r = 0;
do {
......
......@@ -671,7 +671,7 @@ static int ConfigChannel(DMA_Handle_t handle)
/****************************************************************************/
/**
* Intializes all of the data structures associated with the DMA.
* Initializes all of the data structures associated with the DMA.
* @return
* >= 0 - Initialization was successfull.
*
......
......@@ -590,7 +590,7 @@ void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle
*/
/****************************************************************************/
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controller attribute of type dmacHw_CONTROLLER_ATTRIB_e */
);
#endif /* _DMACHW_H */
......@@ -28,7 +28,7 @@
/* Data type for DMA Link List Item */
typedef struct {
uint32_t sar; /* Source Adress Register.
uint32_t sar; /* Source Address Register.
Address must be aligned to CTLx.SRC_TR_WIDTH. */
uint32_t dar; /* Destination Address Register.
Address must be aligned to CTLx.DST_TR_WIDTH. */
......
......@@ -35,7 +35,7 @@ typedef struct {
/* Data type representing DMA channel registers */
typedef struct {
dmacHw_REG64_t ChannelSar; /* Source Adress Register. 64 bits (upper 32 bits are reserved)
dmacHw_REG64_t ChannelSar; /* Source Address Register. 64 bits (upper 32 bits are reserved)
Address must be aligned to CTLx.SRC_TR_WIDTH.
*/
dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)
......
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