Commit f6dc1576 authored by Scott Wood's avatar Scott Wood Committed by Will Deacon
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arm64: arch_timer: Work around QorIQ Erratum A-008585

Erratum A-008585 says that the ARM generic timer counter "has the
potential to contain an erroneous value for a small number of core
clock cycles every time the timer value changes".  Accesses to TVAL
(both read and write) are also affected due to the implicit counter
read.  Accesses to CVAL are not affected.

The workaround is to reread TVAL and count registers until successive
reads return the same value.  Writes to TVAL are replaced with an
equivalent write to CVAL.

The workaround is to reread TVAL and count registers until successive reads
return the same value, and when writing TVAL to retry until counter
reads before and after the write return the same value.

The workaround is enabled if the fsl,erratum-a008585 property is found in
the timer node in the device tree.  This can be overridden with the
clocksource.arm_arch_timer.fsl-a008585 boot parameter, which allows KVM
users to enable the workaround until a mechanism is implemented to
automatically communicate this information.

This erratum can be found on LS1043A and LS2080A.
Acked-by: default avatarMarc Zyngier <>
Signed-off-by: default avatarScott Wood <>
[will: renamed read macro to reflect that it's not usually unstable]
Signed-off-by: default avatarWill Deacon <>
parent 22e43390
......@@ -60,3 +60,5 @@ stable kernels.
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
| Cavium | ThunderX SMMUv2 | #27704 | N/A |
| | | | |
| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
......@@ -698,6 +698,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
loops can be debugged more effectively on production
Format: <bool>
Enable/disable the workaround of Freescale/NXP
erratum A-008585. This can be useful for KVM
guests, if the guest device tree doesn't show the
erratum. If unspecified, the workaround is
enabled based on the device tree.
clearcpuid=BITNUM [X86]
Disable CPUID feature X for the kernel. See
arch/x86/include/asm/cpufeatures.h for the valid bit
......@@ -24,10 +24,51 @@
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/jump_label.h>
#include <linux/types.h>
#include <clocksource/arm_arch_timer.h>
extern struct static_key_false arch_timer_read_ool_enabled;
#define needs_fsl_a008585_workaround() \
#define needs_fsl_a008585_workaround() false
u32 __fsl_a008585_read_cntp_tval_el0(void);
u32 __fsl_a008585_read_cntv_tval_el0(void);
u64 __fsl_a008585_read_cntvct_el0(void);
* The number of retries is an arbitrary value well beyond the highest number
* of iterations the loop has been observed to take.
#define __fsl_a008585_read_reg(reg) ({ \
u64 _old, _new; \
int _retries = 200; \
do { \
_old = read_sysreg(reg); \
_new = read_sysreg(reg); \
_retries--; \
} while (unlikely(_old != _new) && _retries); \
WARN_ON_ONCE(!_retries); \
_new; \
#define arch_timer_reg_read_stable(reg) \
({ \
u64 _val; \
if (needs_fsl_a008585_workaround()) \
_val = __fsl_a008585_read_##reg(); \
else \
_val = read_sysreg(reg); \
_val; \
* These register accessors are marked inline so the compiler can
* nicely work out which register we want, and chuck away the rest of
......@@ -67,14 +108,14 @@ u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
return read_sysreg(cntp_ctl_el0);
return read_sysreg(cntp_tval_el0);
return arch_timer_reg_read_stable(cntp_tval_el0);
} else if (access == ARCH_TIMER_VIRT_ACCESS) {
switch (reg) {
return read_sysreg(cntv_ctl_el0);
return read_sysreg(cntv_tval_el0);
return arch_timer_reg_read_stable(cntv_tval_el0);
......@@ -108,7 +149,7 @@ static inline u64 arch_counter_get_cntpct(void)
static inline u64 arch_counter_get_cntvct(void)
return read_sysreg(cntvct_el0);
return arch_timer_reg_read_stable(cntvct_el0);
static inline int arch_timer_arch_init(void)
......@@ -305,6 +305,16 @@ config ARM_ARCH_TIMER_EVTSTREAM
This must be disabled for hardware validation purposes to detect any
hardware anomalies of missing events.
config FSL_ERRATUM_A008585
bool "Workaround for Freescale/NXP Erratum A-008585"
default y
depends on ARM_ARCH_TIMER && ARM64
This option enables a workaround for Freescale/NXP Erratum
A-008585 ("ARM generic timer may contain an erroneous
value"). The workaround will only be active if the
fsl,erratum-a008585 property is found in the timer node.
bool "Support for the ARM global timer" if COMPILE_TEST
select CLKSRC_OF if OF
......@@ -94,6 +94,43 @@ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
* Architected system timer support.
static int fsl_a008585_enable = -1;
static int __init early_fsl_a008585_cfg(char *buf)
int ret;
bool val;
ret = strtobool(buf, &val);
if (ret)
return ret;
fsl_a008585_enable = val;
return 0;
early_param("clocksource.arm_arch_timer.fsl-a008585", early_fsl_a008585_cfg);
u32 __fsl_a008585_read_cntp_tval_el0(void)
return __fsl_a008585_read_reg(cntp_tval_el0);
u32 __fsl_a008585_read_cntv_tval_el0(void)
return __fsl_a008585_read_reg(cntv_tval_el0);
u64 __fsl_a008585_read_cntvct_el0(void)
return __fsl_a008585_read_reg(cntvct_el0);
#endif /* CONFIG_FSL_ERRATUM_A008585 */
static __always_inline
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
struct clock_event_device *clk)
......@@ -243,6 +280,40 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
static __always_inline void fsl_a008585_set_next_event(const int access,
unsigned long evt, struct clock_event_device *clk)
unsigned long ctrl;
u64 cval = evt + arch_counter_get_cntvct();
ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
write_sysreg(cval, cntp_cval_el0);
else if (access == ARCH_TIMER_VIRT_ACCESS)
write_sysreg(cval, cntv_cval_el0);
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
static int fsl_a008585_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
fsl_a008585_set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
return 0;
static int fsl_a008585_set_next_event_phys(unsigned long evt,
struct clock_event_device *clk)
fsl_a008585_set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
return 0;
#endif /* CONFIG_FSL_ERRATUM_A008585 */
static int arch_timer_set_next_event_virt(unsigned long evt,
struct clock_event_device *clk)
......@@ -271,6 +342,19 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
return 0;
static void fsl_a008585_set_sne(struct clock_event_device *clk)
if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
if (arch_timer_uses_ppi == VIRT_PPI)
clk->set_next_event = fsl_a008585_set_next_event_virt;
clk->set_next_event = fsl_a008585_set_next_event_phys;
static void __arch_timer_setup(unsigned type,
struct clock_event_device *clk)
......@@ -299,6 +383,8 @@ static void __arch_timer_setup(unsigned type,
} else {
clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
clk->name = "arch_mem_timer";
......@@ -515,6 +601,15 @@ static void __init arch_counter_register(unsigned type)
arch_timer_read_counter = arch_counter_get_cntvct;
arch_timer_read_counter = arch_counter_get_cntpct;
* Don't use the vdso fastpath if errata require using
* the out-of-line counter accessor.
if (static_branch_unlikely(&arch_timer_read_ool_enabled)) = "arch_sys_counter_ool";
} else {
arch_timer_read_counter = arch_counter_get_cntvct_mem;
......@@ -800,6 +895,15 @@ static int __init arch_timer_of_init(struct device_node *np)
arch_timer_c3stop = !of_property_read_bool(np, "always-on");
if (fsl_a008585_enable < 0)
fsl_a008585_enable = of_property_read_bool(np, "fsl,erratum-a008585");
if (fsl_a008585_enable) {
pr_info("Enabling workaround for FSL erratum A-008585\n");
* If we cannot rely on firmware initializing the timer registers then
* we should use the physical timers instead.
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