1. 26 Oct, 2010 1 commit
  2. 20 Sep, 2010 1 commit
  3. 17 Sep, 2010 2 commits
  4. 09 Jun, 2010 1 commit
    • Borislav Petkov's avatar
      x86, cacheinfo: Carve out L3 cache slot accessors · 8cc1176e
      Borislav Petkov authored
      This is in preparation for disabling L3 cache indices after having
      received correctable ECCs in the L3 cache. Now we allow for initial
      setting of a disabled index slot (write once) and deny writing new
      indices to it after it has been disabled. Also, we deny using both slots
      to disable one and the same index.
      
      Userspace can restore the previously disabled indices by rewriting those
      sysfs entries when booting.
      
      Cleanup and reorganize code while at it.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <20100602161840.GI18327@aftab>
      Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
      8cc1176e
  5. 14 May, 2010 1 commit
    • Frank Arnold's avatar
      x86, cacheinfo: Turn off L3 cache index disable feature in virtualized environments · 7f284d3c
      Frank Arnold authored
      When running a quest kernel on xen we get:
      
      BUG: unable to handle kernel NULL pointer dereference at 0000000000000038
      IP: [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df
      PGD 0
      Oops: 0000 [#1] SMP
      last sysfs file:
      CPU 0
      Modules linked in:
      
      Pid: 0, comm: swapper Tainted: G        W  2.6.34-rc3 #1 /HVM domU
      RIP: 0010:[<ffffffff8142f2fb>]  [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x
      2ca/0x3df
      RSP: 0018:ffff880002203e08  EFLAGS: 00010046
      RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000060
      RDX: 0000000000000000 RSI: 0000000000000040 RDI: 0000000000000000
      RBP: ffff880002203ed8 R08: 00000000000017c0 R09: ffff880002203e38
      R10: ffff8800023d5d40 R11: ffffffff81a01e28 R12: ffff880187e6f5c0
      R13: ffff880002203e34 R14: ffff880002203e58 R15: ffff880002203e68
      FS:  0000000000000000(0000) GS:ffff880002200000(0000) knlGS:0000000000000000
      CS:  0010 DS: 0000 ES: 0000 CR0: 000000008005003b
      CR2: 0000000000000038 CR3: 0000000001a3c000 CR4: 00000000000006f0
      DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
      DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
      Process swapper (pid: 0, threadinfo ffffffff81a00000, task ffffffff81a44020)
      Stack:
       ffffffff810d7ecb ffff880002203e20 ffffffff81059140 ffff880002203e30
      <0> ffffffff810d7ec9 0000000002203e40 000000000050d140 ffff880002203e70
      <0> 0000000002008140 0000000000000086 ffff880040020140 ffffffff81068b8b
      Call Trace:
       <IRQ>
       [<ffffffff810d7ecb>] ? sync_supers_timer_fn+0x0/0x1c
       [<ffffffff81059140>] ? mod_timer+0x23/0x25
       [<ffffffff810d7ec9>] ? arm_supers_timer+0x34/0x36
       [<ffffffff81068b8b>] ? hrtimer_get_next_event+0xa7/0xc3
       [<ffffffff81058e85>] ? get_next_timer_interrupt+0x19a/0x20d
       [<ffffffff8142fa23>] get_cpu_leaves+0x5c/0x232
       [<ffffffff8106a7b1>] ? sched_clock_local+0x1c/0x82
       [<ffffffff8106a9a0>] ? sched_clock_tick+0x75/0x7a
       [<ffffffff8107748c>] generic_smp_call_function_single_interrupt+0xae/0xd0
       [<ffffffff8101f6ef>] smp_call_function_single_interrupt+0x18/0x27
       [<ffffffff8100a773>] call_function_single_interrupt+0x13/0x20
       <EOI>
       [<ffffffff8143c468>] ? notifier_call_chain+0x14/0x63
       [<ffffffff810295c6>] ? native_safe_halt+0xc/0xd
       [<ffffffff810114eb>] ? default_idle+0x36/0x53
       [<ffffffff81008c22>] cpu_idle+0xaa/0xe4
       [<ffffffff81423a9a>] rest_init+0x7e/0x80
       [<ffffffff81b10dd2>] start_kernel+0x40e/0x419
       [<ffffffff81b102c8>] x86_64_start_reservations+0xb3/0xb7
       [<ffffffff81b103c4>] x86_64_start_kernel+0xf8/0x107
      Code: 14 d5 40 ff ae 81 8b 14 02 31 c0 3b 15 47 1c 8b 00 7d 0e 48 8b 05 36 1c 8b
       00 48 63 d2 48 8b 04 d0 c7 85 5c ff ff ff 00 00 00 00 <8b> 70 38 48 8d 8d 5c ff
       ff ff 48 8b 78 10 ba c4 01 00 00 e8 eb
      RIP  [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df
       RSP <ffff880002203e08>
      CR2: 0000000000000038
      ---[ end trace a7919e7f17c0a726 ]---
      
      The L3 cache index disable feature of AMD CPUs has to be disabled if the
      kernel is running as guest on top of a hypervisor because northbridge
      devices are not available to the guest. Currently, this fixes a boot
      crash on top of Xen. In the future this will become an issue on KVM as
      well.
      
      Check if northbridge devices are present and do not enable the feature
      if there are none.
      
      [ hpa: backported to 2.6.34 ]
      Signed-off-by: default avatarFrank Arnold <frank.arnold@amd.com>
      LKML-Reference: <1271945222-5283-3-git-send-email-bp@amd64.org>
      Acked-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      Cc: <stable@kernel.org>
      7f284d3c
  6. 23 Apr, 2010 5 commits
    • Borislav Petkov's avatar
      x86, cacheinfo: Disable index in all four subcaches · 59d3b388
      Borislav Petkov authored
      When disabling an L3 cache index, make sure we disable that index in
      all four subcaches of the L3. Clarify nomenclature while at it, wrt to
      disable slots versus disable index and rename accordingly.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <1271945222-5283-6-git-send-email-bp@amd64.org>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      59d3b388
    • Borislav Petkov's avatar
      x86, cacheinfo: Make L3 cache info per node · ba06edb6
      Borislav Petkov authored
      Currently, we're allocating L3 cache info and calculating indices for
      each online cpu which is clearly superfluous. Instead, we need to do
      this per-node as is each L3 cache.
      
      No functional change, only per-cpu memory savings.
      
      -v2: Allocate L3 cache descriptors array dynamically.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <1271945222-5283-5-git-send-email-bp@amd64.org>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      ba06edb6
    • Borislav Petkov's avatar
      x86, cacheinfo: Reorganize AMD L3 cache structure · 9350f982
      Borislav Petkov authored
      Add a struct representing L3 cache attributes (subcache sizes and
      indices count) and move the respective members out of _cpuid4_info.
      Also, stash the struct pci_dev ptr into the struct simplifying the code
      even more.
      
      There should be no functionality change resulting from this patch except
      slightly slimming the _cpuid4_info per-cpu vars.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <1271945222-5283-4-git-send-email-bp@amd64.org>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      9350f982
    • Frank Arnold's avatar
      x86, cacheinfo: Turn off L3 cache index disable feature in virtualized environments · f2b20e41
      Frank Arnold authored
      When running a quest kernel on xen we get:
      
      BUG: unable to handle kernel NULL pointer dereference at 0000000000000038
      IP: [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df
      PGD 0
      Oops: 0000 [#1] SMP
      last sysfs file:
      CPU 0
      Modules linked in:
      
      Pid: 0, comm: swapper Tainted: G        W  2.6.34-rc3 #1 /HVM domU
      RIP: 0010:[<ffffffff8142f2fb>]  [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x
      2ca/0x3df
      RSP: 0018:ffff880002203e08  EFLAGS: 00010046
      RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000060
      RDX: 0000000000000000 RSI: 0000000000000040 RDI: 0000000000000000
      RBP: ffff880002203ed8 R08: 00000000000017c0 R09: ffff880002203e38
      R10: ffff8800023d5d40 R11: ffffffff81a01e28 R12: ffff880187e6f5c0
      R13: ffff880002203e34 R14: ffff880002203e58 R15: ffff880002203e68
      FS:  0000000000000000(0000) GS:ffff880002200000(0000) knlGS:0000000000000000
      CS:  0010 DS: 0000 ES: 0000 CR0: 000000008005003b
      CR2: 0000000000000038 CR3: 0000000001a3c000 CR4: 00000000000006f0
      DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
      DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
      Process swapper (pid: 0, threadinfo ffffffff81a00000, task ffffffff81a44020)
      Stack:
       ffffffff810d7ecb ffff880002203e20 ffffffff81059140 ffff880002203e30
      <0> ffffffff810d7ec9 0000000002203e40 000000000050d140 ffff880002203e70
      <0> 0000000002008140 0000000000000086 ffff880040020140 ffffffff81068b8b
      Call Trace:
       <IRQ>
       [<ffffffff810d7ecb>] ? sync_supers_timer_fn+0x0/0x1c
       [<ffffffff81059140>] ? mod_timer+0x23/0x25
       [<ffffffff810d7ec9>] ? arm_supers_timer+0x34/0x36
       [<ffffffff81068b8b>] ? hrtimer_get_next_event+0xa7/0xc3
       [<ffffffff81058e85>] ? get_next_timer_interrupt+0x19a/0x20d
       [<ffffffff8142fa23>] get_cpu_leaves+0x5c/0x232
       [<ffffffff8106a7b1>] ? sched_clock_local+0x1c/0x82
       [<ffffffff8106a9a0>] ? sched_clock_tick+0x75/0x7a
       [<ffffffff8107748c>] generic_smp_call_function_single_interrupt+0xae/0xd0
       [<ffffffff8101f6ef>] smp_call_function_single_interrupt+0x18/0x27
       [<ffffffff8100a773>] call_function_single_interrupt+0x13/0x20
       <EOI>
       [<ffffffff8143c468>] ? notifier_call_chain+0x14/0x63
       [<ffffffff810295c6>] ? native_safe_halt+0xc/0xd
       [<ffffffff810114eb>] ? default_idle+0x36/0x53
       [<ffffffff81008c22>] cpu_idle+0xaa/0xe4
       [<ffffffff81423a9a>] rest_init+0x7e/0x80
       [<ffffffff81b10dd2>] start_kernel+0x40e/0x419
       [<ffffffff81b102c8>] x86_64_start_reservations+0xb3/0xb7
       [<ffffffff81b103c4>] x86_64_start_kernel+0xf8/0x107
      Code: 14 d5 40 ff ae 81 8b 14 02 31 c0 3b 15 47 1c 8b 00 7d 0e 48 8b 05 36 1c 8b
       00 48 63 d2 48 8b 04 d0 c7 85 5c ff ff ff 00 00 00 00 <8b> 70 38 48 8d 8d 5c ff
       ff ff 48 8b 78 10 ba c4 01 00 00 e8 eb
      RIP  [<ffffffff8142f2fb>] cpuid4_cache_lookup_regs+0x2ca/0x3df
       RSP <ffff880002203e08>
      CR2: 0000000000000038
      ---[ end trace a7919e7f17c0a726 ]---
      
      The L3 cache index disable feature of AMD CPUs has to be disabled if the
      kernel is running as guest on top of a hypervisor because northbridge
      devices are not available to the guest. Currently, this fixes a boot
      crash on top of Xen. In the future this will become an issue on KVM as
      well.
      
      Check if northbridge devices are present and do not enable the feature
      if there are none.
      Signed-off-by: default avatarFrank Arnold <frank.arnold@amd.com>
      LKML-Reference: <1271945222-5283-3-git-send-email-bp@amd64.org>
      Acked-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      f2b20e41
    • Borislav Petkov's avatar
      x86, cacheinfo: Unify AMD L3 cache index disable checking · b1ab1b4d
      Borislav Petkov authored
      All F10h CPUs starting with model 8 resp. 9, stepping 1, support L3
      cache index disable. Concentrate the family, model, stepping checking at
      one place and enable the feature implicitly on upcoming Fam10h models.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <1271945222-5283-2-git-send-email-bp@amd64.org>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      b1ab1b4d
  7. 08 Mar, 2010 1 commit
  8. 19 Feb, 2010 2 commits
    • Borislav Petkov's avatar
      x86, cacheinfo: Enable L3 CID only on AMD · cb19060a
      Borislav Petkov authored
      Final stage linking can fail with
      
       arch/x86/built-in.o: In function `store_cache_disable':
       intel_cacheinfo.c:(.text+0xc509): undefined reference to `amd_get_nb_id'
       arch/x86/built-in.o: In function `show_cache_disable':
       intel_cacheinfo.c:(.text+0xc7d3): undefined reference to `amd_get_nb_id'
      
      when CONFIG_CPU_SUP_AMD is not enabled because the amd_get_nb_id
      helper is defined in AMD-specific code but also used in generic code
      (intel_cacheinfo.c). Reorganize the L3 cache index disable code under
      CONFIG_CPU_SUP_AMD since it is AMD-only anyway.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <20100218184210.GF20473@aftab>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      cb19060a
    • Borislav Petkov's avatar
      x86, cacheinfo: Remove NUMA dependency, fix for AMD Fam10h rev D1 · f619b3d8
      Borislav Petkov authored
      The show/store_cache_disable routines depend unnecessarily on NUMA's
      cpu_to_node and the disabling of cache indices broke when !CONFIG_NUMA.
      Remove that dependency by using a helper which is always correct.
      
      While at it, enable L3 Cache Index disable on rev D1 Istanbuls which
      sport the feature too.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      LKML-Reference: <20100218184339.GG20473@aftab>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      f619b3d8
  9. 23 Jan, 2010 3 commits
  10. 13 Jan, 2010 1 commit
  11. 11 Dec, 2009 1 commit
    • Prarit Bhargava's avatar
      x86, AMD: Fix stale cpuid4_info shared_map data in shared_cpu_map cpumasks · ebb682f5
      Prarit Bhargava authored
      The per_cpu cpuid4_info shared_map can contain stale data when CPUs are added
      and removed.
      
      The stale data can lead to a NULL pointer derefernce panic on a remove of a
      CPU that has had siblings previously removed.
      
      This patch resolves the panic by verifying a cpu is actually online before
      adding it to the shared_cpu_map, only examining cpus that are part of
      the same lower level cache, and by updating other siblings lowest level cache
      maps when a cpu is added.
      Signed-off-by: default avatarPrarit Bhargava <prarit@redhat.com>
      LKML-Reference: <20091209183336.17855.98708.sendpatchset@prarit.bos.redhat.com>
      Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
      ebb682f5
  12. 13 Nov, 2009 1 commit
    • Dave Jones's avatar
      x86: Remove the CPU cache size printk's · 15cd8812
      Dave Jones authored
      They aren't really useful, and they pollute the dmesg output a lot
      (especially on machines with many cores).
      
      Also the same information can be trivially found out from
      userspace.
      Reported-by: default avatarMike Travis <travis@sgi.com>
      Signed-off-by: default avatarDave Jones <davej@redhat.com>
      Acked-by: default avatarH. Peter Anvin <hpa@zytor.com>
      Cc: Andi Kleen <ak@linux.intel.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Roland Dreier <rdreier@cisco.com>
      Cc: Randy Dunlap <rdunlap@xenotime.net>
      Cc: Tejun Heo <tj@kernel.org>
      Cc: Greg Kroah-Hartman <gregkh@suse.de>
      Cc: Yinghai Lu <yinghai@kernel.org>
      Cc: David Rientjes <rientjes@google.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Cc: Jack Steiner <steiner@sgi.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      LKML-Reference: <20091112231542.GA7129@redhat.com>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      15cd8812
  13. 10 Nov, 2009 2 commits
  14. 29 Oct, 2009 1 commit
    • Tejun Heo's avatar
      percpu: make percpu symbols in x86 unique · 0fe1e009
      Tejun Heo authored
      This patch updates percpu related symbols in x86 such that percpu
      symbols are unique and don't clash with local symbols.  This serves
      two purposes of decreasing the possibility of global percpu symbol
      collision and allowing dropping per_cpu__ prefix from percpu symbols.
      
      * arch/x86/kernel/cpu/common.c: rename local variable to avoid collision
      
      * arch/x86/kvm/svm.c: s/svm_data/sd/ for local variables to avoid collision
      
      * arch/x86/kernel/cpu/cpu_debug.c: s/cpu_arr/cpud_arr/
        				   s/priv_arr/cpud_priv_arr/
      				   s/cpu_priv_count/cpud_priv_count/
      
      * arch/x86/kernel/cpu/intel_cacheinfo.c: s/cpuid4_info/ici_cpuid4_info/
        					 s/cache_kobject/ici_cache_kobject/
      					 s/index_kobject/ici_index_kobject/
      
      * arch/x86/kernel/ds.c: s/cpu_context/cpu_ds_context/
      
      Partly based on Rusty Russell's "alloc_percpu: rename percpu vars
      which cause name clashes" patch.
      Signed-off-by: default avatarTejun Heo <tj@kernel.org>
      Acked-by: default avatar(kvm) Avi Kivity <avi@redhat.com>
      Cc: Rusty Russell <rusty@rustcorp.com.au>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Marcelo Tosatti <mtosatti@redhat.com>
      Cc: x86@kernel.org
      0fe1e009
  15. 03 Sep, 2009 1 commit
  16. 11 Jul, 2009 1 commit
  17. 10 Apr, 2009 6 commits
  18. 12 Mar, 2009 1 commit
  19. 26 Feb, 2009 1 commit
    • Ingo Molnar's avatar
      fix warning in arch/x86/kernel/cpu/intel_cacheinfo.c · ba1d755a
      Ingo Molnar authored
      fix this warning:
      
        arch/x86/kernel/cpu/intel_cacheinfo.c:139: warning: ‘k8_nb_id’ defined but not used
        arch/x86/kernel/cpu/intel_cacheinfo.c:527: warning: ‘free_cache_attributes’ defined but not used
        arch/x86/kernel/cpu/intel_cacheinfo.c:538: warning: ‘detect_cache_attributes’ defined but not used
      
      Unused variables in the !CONFIG_SYSCTL case.
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      ba1d755a
  20. 01 Feb, 2009 1 commit
  21. 27 Jan, 2009 1 commit
  22. 11 Jan, 2009 1 commit
  23. 29 Dec, 2008 1 commit
  24. 17 Dec, 2008 1 commit
  25. 13 Dec, 2008 1 commit
    • Rusty Russell's avatar
      cpumask: change cpumask_scnprintf, cpumask_parse_user, cpulist_parse, and... · 29c0177e
      Rusty Russell authored
      cpumask: change cpumask_scnprintf, cpumask_parse_user, cpulist_parse, and cpulist_scnprintf to take pointers.
      
      Impact: change calling convention of existing cpumask APIs
      
      Most cpumask functions started with cpus_: these have been replaced by
      cpumask_ ones which take struct cpumask pointers as expected.
      
      These four functions don't have good replacement names; fortunately
      they're rarely used, so we just change them over.
      Signed-off-by: default avatarRusty Russell <rusty@rustcorp.com.au>
      Signed-off-by: default avatarMike Travis <travis@sgi.com>
      Acked-by: default avatarIngo Molnar <mingo@elte.hu>
      Cc: paulus@samba.org
      Cc: mingo@redhat.com
      Cc: tony.luck@intel.com
      Cc: ralf@linux-mips.org
      Cc: Greg Kroah-Hartman <gregkh@suse.de>
      Cc: cl@linux-foundation.org
      Cc: srostedt@redhat.com
      29c0177e
  26. 30 Nov, 2008 1 commit