1. 01 Apr, 2015 20 commits
  2. 31 Mar, 2015 20 commits
    • Markos Chandras's avatar
      MIPS: Malta: malta-time: Ensure GIC counter is running · be37a990
      Markos Chandras authored
      
      
      Start the GIC counter before we try to determine its frequency.
      Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9596/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      be37a990
    • Markos Chandras's avatar
      CLOCKSOURCE: mips-gic-timer: Ensure GIC counter is running · 7d9cd1f5
      Markos Chandras authored
      
      
      Start the GIC counter after configuring the clocksource since there
      are no guarantees the counter will be running after a CPU reset.
      Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9595/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      7d9cd1f5
    • Markos Chandras's avatar
      IRQCHIP: irq-mips-gic: Add new functions to start/stop the GIC counter · 8fa4b930
      Markos Chandras authored
      
      
      We add new functions to start and stop the GIC counter since there are no
      guarantees the counter will be running after a CPU reset. The GIC counter
      is stopped by setting the 29th bit on the GIC Config register and it is
      started by clearing that bit.
      Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: Qais Yousef <qais.yousef@imgtec.com>
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/9594/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      8fa4b930
    • James Hogan's avatar
      ttyFDC: Implement KGDB IO operations. · c2d7ef51
      James Hogan authored
      
      
      Implement KGDB IO operations for MIPS Fast Debug Channel (FDC). This can
      be enabled via Kconfig, which also allows the channel number to be
      chosen.
      
      The magic sysrq hack is implemented in the TTY driver, detecting just ^C
      for the KGDB channel, and ^O followed by a letter for the FDC console
      channel.
      
      The KGDB operations are reasonably efficient thanks to the flush
      callback, with a 4 byte buffer being used in both directions to allow up
      to 4 bytes to be encoded per FDC word. Reading of data for KGDB will
      discard any data received on other channels, which clearly isn't ideal,
      but given that there is a single FIFO shared between channels we can't
      do much better.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.cz>
      Cc: Jason Wessel <jason.wessel@windriver.com>
      Cc: linux-mips@linux-mips.org
      Cc: kgdb-bugreport@lists.sourceforge.net
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9147/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      c2d7ef51
    • James Hogan's avatar
      MIPS, ttyFDC: Add early FDC console support · e934945d
      James Hogan authored
      
      
      Add support for early console of MIPS Fast Debug Channel (FDC) on
      channel 1 with a call very early from the MIPS setup_arch().
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.cz>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9145/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e934945d
    • James Hogan's avatar
      TTY: Add MIPS EJTAG Fast Debug Channel TTY driver · 4cebec60
      James Hogan authored
      
      
      Add TTY driver and consoles for the MIPS EJTAG Fast Debug Channel (FDC),
      which is found on the per-CPU MIPS Common Device Mapped Memory (CDMM)
      bus.
      
      The FDC is a per-CPU device which is used to communicate with an EJTAG
      probe. RX and TX FIFOs exist, containing 32-bits of data and 4-bit
      channel numbers. 16 general data streams are implemented on this for TTY
      and console use by encoding up to 4 bytes on each 32-bit FDC word.
      
      The TTY devices are named e.g. /dev/ttyFDC3c2 for channel 2 of the FDC
      attached to logical CPU 3.
      
      These can be used for getting the kernel log, a login prompt, or as a
      GDB remote transport, all over EJTAG and without needing a serial port.
      
      It can have an interrupt to notify of when incoming data is available in
      the RX FIFO or when the TX FIFO is no longer full. The detection of this
      interrupt occurs in architecture / platform code, but it may be shared
      with the timer and/or performance counter interrupt.
      
      Due to the per-CPU nature of the hardware, all outgoing TTY data is
      written out from a kthread which is pinned to the appropriate CPU.
      
      The console is not bound to a specific CPU, so output will appear on the
      chosen channel on whichever CPU the code is executing on. Enable with
      e.g. console=fdc1 in kernel arguments. /dev/console is bound to the same
      channel on the boot CPU's FDC if it exists.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Jiri Slaby <jslaby@suse.cz>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9146/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      4cebec60
    • James Hogan's avatar
      MIPS: idle: Workaround wait + FDC problems · e38df288
      James Hogan authored
      
      
      On certain cores (namely proAptiv and P5600) incoming data via a Fast
      Debug Channel (FDC) while the core is blocked on a wait instruction will
      cause the wait not to wake up even when another interrupt is received.
      This makes an idle target stop as soon as you send FDC data to it, until
      the debug probe interrupts it and restarts the wait instruction.
      
      This is worked around by avoiding using r4k_wait on these cores if
      CONFIG_MIPS_EJTAG_FDC_TTY is enabled (which would imply the user intends
      to use the FDC).
      
      [ralf@linux-mips.org: Fix conflict.]
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9144/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e38df288
    • James Hogan's avatar
      MIPS: Malta: Implement get_c0_fdc_int() · 602e8a34
      James Hogan authored
      
      
      Implement the weak get_c0_fdc_int() function for Malta. The Fast Debug
      Channel (FDC) interrupt is obtained mainly depending on whether a GIC is
      present. Vectored external interrupt mode isn't yet supported.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9143/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      602e8a34
    • James Hogan's avatar
      IRQCHIP: mips-gic: Add function for retrieving FDC IRQ · 6429e2b6
      James Hogan authored
      
      
      Add a function to the MIPS GIC driver for retrieving the Fast Debug
      Channel (FDC) interrupt number, similar to the existing ones for the
      timer and perf counter interrupts. This will be used by platform
      implementations of get_c0_fdc_int() if a GIC is present.
      
      A workaround exists for interAptiv and proAptiv which claim to be able
      to route the FDC interrupt but don't seem to be able to in practice (at
      least on Malta).
      
      [ralf@linux-mips.org: Fix conflict.]
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9142/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      6429e2b6
    • James Hogan's avatar
      irqchip: mips-gic: Don't treat FDC IRQ as percpu devid · b720fd8b
      James Hogan authored
      
      
      Treat the Fast Debug Channel (FDC) interrupt the same as the timer and
      performance counter interrupts. Like them, the FDC IRQ is also per-VPE,
      and also doesn't use a per-CPU device ID yet. Per-CPU device IDs don't
      seem to work with IRQF_SHARED which is needed for compatibility with
      cores which don't route the FDC IRQ through the GIC. For hardware which
      routes FDC IRQs through the GIC this is something that could be added
      later.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Andrew Bresticker <abrestic@chromium.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9141/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      b720fd8b
    • James Hogan's avatar
      MIPS: Read CPU IRQ line that FDC to routed to · 8f7ff027
      James Hogan authored
      
      
      Read the CPU IRQ line reportedly used for the Fast Debug Channel (FDC)
      interrupt from the IntCtl register and store it in cp0_fdc_irq where
      platform implementations of the new weak platform function
      get_c0_fdc_int() can refer to it.
      
      [ralf@linux-mips.org: Fixed conflict.]
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: James Hogan <james.hogan@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/9140/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      8f7ff027
    • James Hogan's avatar
      MIPS: Add architectural FDC IRQ fields · 9323f84f
      James Hogan authored
      
      
      Add architectural field definitions relating to the Fast Debug Channel
      (FDC) interrupt, namely the pending bit in Cause and the field in
      IntCtl to specify which CPU IRQ line the FDC interrupt is routed to.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Cc: James Hogan <james.hogan@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/9139/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      9323f84f
    • James Hogan's avatar
      MIPS: Malta: Implement mips_cdmm_phys_base() · 296b7c68
      James Hogan authored
      
      
      Implement mips_cdmm_phys_base() for Malta, returning the physical base
      address 0x1fc10000 which is "typically unused".
      
      This allows the Common Device Memory Map (CDMM) region to be mapped, and
      devices in that region (such as the Fast Debug Channel (FDC) hardware
      for communication over EJTAG) to be discovered.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9177/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      296b7c68
    • James Hogan's avatar
      MIPS: Add CDMM bus support · 8286ae03
      James Hogan authored
      
      
      Add MIPS Common Device Memory Map (CDMM) support in the form of a bus in
      the standard Linux device model. Each device attached via CDMM is
      discoverable via an 8-bit type identifier and may contain a number of
      blocks of memory mapped registers in the CDMM region. IRQs are expected
      to be handled separately.
      
      Due to the per-cpu (per-VPE for MT cores) nature of the CDMM devices,
      all the driver callbacks take place from workqueues which are run on the
      right CPU for the device in question, so that the driver doesn't need to
      be as concerned about which CPU it is running on. Callbacks also exist
      for when CPUs are taken offline, so that any per-CPU resources used by
      the driver can be disabled so they don't get forcefully migrated. CDMM
      devices are created as children of the CPU device they are attached to.
      
      Any existing CDMM configuration by the bootloader will be inherited,
      however platforms wishing to enable CDMM should implement the weak
      mips_cdmm_phys_base() function (see asm/cdmm.h) so that the bus driver
      knows where it should put the CDMM region in the physical address space
      if the bootloader hasn't already enabled it.
      
      A mips_cdmm_early_probe() function is also provided to allow early boot
      or particularly low level code to set up the CDMM region and probe for a
      specific device type, for example early console or KGDB IO drivers for
      the EJTAG Fast Debug Channel (FDC) CDMM device.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9599/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      8286ae03
    • James Hogan's avatar
      MIPS: Add arch CDMM definitions and probing · 9b3274bd
      James Hogan authored
      
      
      Add architectural definitions and probing for the MIPS Common Device
      Memory Map (CDMM) region. When supported and enabled at a particular
      physical address, this region allows some number of per-CPU devices to
      be discovered and controlled via MMIO.
      
      A bit exists in Config3 to determine whether the feature is present, and
      a CDMMBase CP0 register allows the region to be enabled at a particular
      physical address.
      
      [ralf@linux-mips.org: Sort conflict with other patches.]
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9178/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      9b3274bd
    • James Hogan's avatar
      MIPS: Allow shared IRQ for timer & perf counter · 4a91d8fb
      James Hogan authored
      
      
      Before release 2 of the architecture there weren't separate interrupt
      pending bits for the local CPU interrupts (timer & perf counter
      overflow), so when they were connected to the same interrupt line the
      timer handler had to call the performance counter handler before knowing
      whether a timer interrupt was actually pending.
      
      Now another CPU local interrupt, for the Fast Debug Channel (FDC), can
      also be routed to an arbitrary interrupt line. It isn't scalable to keep
      adding cross-calls between handlers for these cases of shared interrupt
      lines, especially since the FDC could in theory share its interrupt line
      with the performance counter, timer, or both.
      
      Fortunately since release 2 of the architecture separate interrupt
      pending bits do exist in the Cause register. This allows local
      interrupts which share an interrupt line to have separate handlers using
      IRQF_SHARED. Unfortunately they can't easily have their own irqchip as
      there is no generic way to individually mask them.
      
      Enable this sharing to happen by removing the special case for when the
      perf count shares an IRQ with the timer. cp0_perfcount_irq and
      cp0_compare_irq can then be set to the same value with shared interrupt
      handlers registered for both of them.
      
      Pre-R2 code should be unaffected. cp0_perfcount_irq will always be -1
      and the timer handler will contnue to call into the perf counter
      handler.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9131/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      4a91d8fb
    • James Hogan's avatar
      MIPS: OProfile: Allow sharing IRQ with timer · 369a93bb
      James Hogan authored
      
      
      When requesting the performance counter overflow interrupt, pass flags
      which are compatible with the cevt-r4k driver, in particular
      IRQF_SHARED so that the two handlers can share the same IRQ. This is
      possible since release 2 of the architecture where there are separate
      pending interrupt bits for the timer interrupt and the performance
      counter interrupt.
      
      This will be necessary since the FDC interrupt can also be arbitrarily
      routed to a CPU interrupt, possibly sharing with the timer, the
      performance counters, or both, and it isn't scalable to have all the
      handlers able to call other handlers that may be on the same IRQ line.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Robert Richter <rric@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: oprofile-list@lists.sf.net
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9130/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      369a93bb
    • James Hogan's avatar
      MIPS: perf: Allow sharing IRQ with timer · a1ec0e18
      James Hogan authored
      
      
      When requesting the performance counter overflow interrupt, pass flags
      which are compatible with the cevt-r4k driver, in particular
      IRQF_SHARED so that the two handlers can share the same IRQ. This is
      possible since release 2 of the architecture where there are separate
      pending interrupt bits for the timer interrupt and the performance
      counter interrupt.
      
      This will be necessary since the FDC interrupt can also be arbitrarily
      routed to a CPU interrupt, possibly sharing with the timer, the
      performance counters, or both, and it isn't scalable to have all the
      handlers able to call other handlers that may be on the same IRQ line.
      
      Shared handlers must also have a unique device pointer so they can be
      individually removed, so &mipspmu is now passed in for that instead of
      NULL.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9129/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      a1ec0e18
    • Ralf Baechle's avatar
      MIPS: cevt-r4k: Cleanup c0_compare_interrupt. · f0c5b894
      Ralf Baechle authored
      
      
      The attempt to get gcc to generate best possible code turned
      c0_compare_interrupt() into a bit of Italian pasta code.  Tweak for
      sanity.
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      f0c5b894
    • James Hogan's avatar
      MIPS: cevt-r4k: Make interrupt handler shared · 7dfe8198
      James Hogan authored
      
      
      Make the cevt-r4k interrupt handler shared so that other interrupt
      handlers (specifically the performance counter overflow handler and fast
      debug channel interrupt handler) can share the same interrupt line.
      
      This simply imvolves returning IRQ_NONE when no timer interrupt has been
      handled to allow other handlers to run, and passing IRQF_SHARED when
      setting up the IRQ handler so that other handlers (with compatible
      flags) can be registered.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/9128/
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      7dfe8198