s626.c 86.5 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
/*
  comedi/drivers/s626.c
  Sensoray s626 Comedi driver

  COMEDI - Linux Control and Measurement Device Interface
  Copyright (C) 2000 David A. Schleef <ds@schleef.org>

  Based on Sensoray Model 626 Linux driver Version 0.2
  Copyright (C) 2002-2004 Sensoray Co., Inc.

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; if not, write to the Free Software
  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

*/

/*
Driver: s626
Description: Sensoray 626 driver
Devices: [Sensoray] 626 (s626)
Authors: Gianluca Palli <gpalli@deis.unibo.it>,
Updated: Fri, 15 Feb 2008 10:28:42 +0000
Status: experimental

35
Configuration options: not applicable, uses PCI auto config
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

INSN_CONFIG instructions:
  analog input:
   none

  analog output:
   none

  digital channel:
   s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
   supported configuration options:
   INSN_CONFIG_DIO_QUERY
   COMEDI_INPUT
   COMEDI_OUTPUT

  encoder:
   Every channel must be configured before reading.

   Example code

   insn.insn=INSN_CONFIG;   //configuration instruction
   insn.n=1;                //number of operation (must be 1)
   insn.data=&initialvalue; //initial value loaded into encoder
59
				//during configuration
60
61
   insn.subdev=5;           //encoder subdevice
   insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
62
							//to configure
63
64
65
66

   comedi_do_insn(cf,&insn); //executing configuration
*/

67
#include <linux/pci.h>
68
#include <linux/interrupt.h>
69
70
71
72
73
74
75
76
#include <linux/kernel.h>
#include <linux/types.h>

#include "../comedidev.h"

#include "comedi_fc.h"
#include "s626.h"

77
78
79
80
81
#define PCI_VENDOR_ID_S626 0x1131
#define PCI_DEVICE_ID_S626 0x7146
#define PCI_SUBVENDOR_ID_S626 0x6000
#define PCI_SUBDEVICE_ID_S626 0x0272

82
struct s626_private {
83
	void __iomem *mmio;
84
	uint8_t ai_cmd_running;	/*  ai_cmd is running */
Lucas De Marchi's avatar
Lucas De Marchi committed
85
	uint8_t ai_continous;	/*  continous acquisition */
86
	int ai_sample_count;	/*  number of samples to acquire */
87
88
89
90
91
92
93
94
	unsigned int ai_sample_timer;
	/*  time between samples in  units of the timer */
	int ai_convert_count;	/*  conversion counter */
	unsigned int ai_convert_timer;
	/*  time between conversion in  units of the timer */
	uint16_t CounterIntEnabs;
	/* Counter interrupt enable  mask for MISC2 register. */
	uint8_t AdcItems;	/* Number of items in ADC poll  list. */
95
	struct bufferDMA RPSBuf;	/* DMA buffer used to hold ADC (RPS1) program. */
96
	struct bufferDMA ANABuf;
97
98
99
100
101
102
103
104
105
	/* DMA buffer used to receive ADC data and hold DAC data. */
	uint32_t *pDacWBuf;
	/* Pointer to logical adrs of DMA buffer used to hold DAC  data. */
	uint16_t Dacpol;	/* Image of DAC polarity register. */
	uint8_t TrimSetpoint[12];	/* Images of TrimDAC setpoints */
	/* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
	uint32_t I2CAdrs;
	/* I2C device address for onboard EEPROM (board rev dependent). */
	/*   short         I2Cards; */
106
	unsigned int ao_readback[S626_DAC_CHANNELS];
107
};
108

109
/*  COUNTER OBJECT ------------------------------------------------ */
110
struct enc_private {
111
	/*  Pointers to functions that differ for A and B counters: */
112
113
114
115
116
117
118
119
120
121
	uint16_t(*GetEnable) (struct comedi_device *dev, struct enc_private *);	/* Return clock enable. */
	uint16_t(*GetIntSrc) (struct comedi_device *dev, struct enc_private *);	/* Return interrupt source. */
	uint16_t(*GetLoadTrig) (struct comedi_device *dev, struct enc_private *);	/* Return preload trigger source. */
	uint16_t(*GetMode) (struct comedi_device *dev, struct enc_private *);	/* Return standardized operating mode. */
	void (*PulseIndex) (struct comedi_device *dev, struct enc_private *);	/* Generate soft index strobe. */
	void (*SetEnable) (struct comedi_device *dev, struct enc_private *, uint16_t enab);	/* Program clock enable. */
	void (*SetIntSrc) (struct comedi_device *dev, struct enc_private *, uint16_t IntSource);	/* Program interrupt source. */
	void (*SetLoadTrig) (struct comedi_device *dev, struct enc_private *, uint16_t Trig);	/* Program preload trigger source. */
	void (*SetMode) (struct comedi_device *dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc);	/* Program standardized operating mode. */
	void (*ResetCapFlags) (struct comedi_device *dev, struct enc_private *);	/* Reset event capture flags. */
122
123
124
125
126
127

	uint16_t MyCRA;		/*    Address of CRA register. */
	uint16_t MyCRB;		/*    Address of CRB register. */
	uint16_t MyLatchLsw;	/*    Address of Latch least-significant-word */
	/*    register. */
	uint16_t MyEventBits[4];	/*    Bit translations for IntSrc -->RDMISC2. */
128
};
129

130
#define encpriv ((struct enc_private *)(dev->subdevices+5)->private)
131

132
/*  Counter overflow/index event flag masks for RDMISC2. */
133
134
#define INDXMASK(C)		(1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 +  4)))
#define OVERMASK(C)		(1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
135
136
#define EVBITS(C)		{ 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }

137
138
/*  Translation table to map IntSrc into equivalent RDMISC2 event flag  bits. */
/* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
139

140
141
142
143
144
145
146
147
148
149
/*
 * Enable/disable a function or test status bit(s) that are accessed
 * through Main Control Registers 1 or 2.
 */
static void s626_mc_enable(struct comedi_device *dev,
			   unsigned int cmd, unsigned int reg)
{
	struct s626_private *devpriv = dev->private;
	unsigned int val = (cmd << 16) | cmd;

150
	writel(val, devpriv->mmio + reg);
151
}
152

153
154
155
156
157
static void s626_mc_disable(struct comedi_device *dev,
			    unsigned int cmd, unsigned int reg)
{
	struct s626_private *devpriv = dev->private;

158
	writel(cmd << 16 , devpriv->mmio + reg);
159
}
160

161
162
163
164
165
166
static bool s626_mc_test(struct comedi_device *dev,
			 unsigned int cmd, unsigned int reg)
{
	struct s626_private *devpriv = dev->private;
	unsigned int val;

167
	val = readl(devpriv->mmio + reg);
168
169
170

	return (val & cmd) ? true : false;
}
171

172
#define BUGFIX_STREG(REGADRS)   (REGADRS - 4)
173

174
/*  Write a time slot control record to TSL2. */
175
#define VECTPORT(VECTNUM)		(P_TSL2 + ((VECTNUM) << 2))
176

177
/*  Code macros used for constructing I2C command bytes. */
178
179
180
#define I2C_B2(ATTR, VAL)	(((ATTR) << 6) | ((VAL) << 24))
#define I2C_B1(ATTR, VAL)	(((ATTR) << 4) | ((VAL) << 16))
#define I2C_B0(ATTR, VAL)	(((ATTR) << 2) | ((VAL) <<  8))
181

182
183
184
185
186
static const struct comedi_lrange s626_range_table = {
	2, {
		BIP_RANGE(5),
		BIP_RANGE(10),
	}
187
188
};

189
190
191
192
/*  Execute a DEBI transfer.  This must be called from within a */
/*  critical section. */
static void DEBItransfer(struct comedi_device *dev)
{
193
194
	struct s626_private *devpriv = dev->private;

195
196
	/* Initiate upload of shadow RAM to DEBI control register */
	s626_mc_enable(dev, MC2_UPLD_DEBI, P_MC2);
197

198
199
200
201
202
	/*
	 * Wait for completion of upload from shadow RAM to
	 * DEBI control register.
	 */
	while (!s626_mc_test(dev, MC2_UPLD_DEBI, P_MC2))
203
204
		;

205
	/* Wait until DEBI transfer is done */
206
	while (readl(devpriv->mmio + P_PSR) & PSR_DEBI_S)
207
208
209
210
211
212
213
		;
}

/*  Initialize the DEBI interface for all transfers. */

static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
{
214
	struct s626_private *devpriv = dev->private;
215

216
	/* Set up DEBI control register value in shadow RAM */
217
	writel(DEBI_CMD_RDWORD | addr, devpriv->mmio + P_DEBICMD);
218
219
220
221

	/*  Execute the DEBI transfer. */
	DEBItransfer(dev);

222
	return readl(devpriv->mmio + P_DEBIAD);
223
224
225
226
227
}

/*  Write a value to a gate array register. */
static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
{
228
	struct s626_private *devpriv = dev->private;
229

230
	/* Set up DEBI control register value in shadow RAM */
231
232
	writel(DEBI_CMD_WRWORD | addr, devpriv->mmio + P_DEBICMD);
	writel(wdata, devpriv->mmio + P_DEBIAD);
233
234
235
236
237
238
239
240
241

	/*  Execute the DEBI transfer. */
	DEBItransfer(dev);
}

/* Replace the specified bits in a gate array register.  Imports: mask
 * specifies bits that are to be preserved, wdata is new value to be
 * or'd with the masked original.
 */
242
243
static void DEBIreplace(struct comedi_device *dev, unsigned int addr,
			unsigned int mask, unsigned int wdata)
244
{
245
	struct s626_private *devpriv = dev->private;
246
	unsigned int val;
247

248
	addr &= 0xffff;
249
	writel(DEBI_CMD_RDWORD | addr, devpriv->mmio + P_DEBICMD);
250
	DEBItransfer(dev);
251

252
253
	writel(DEBI_CMD_WRWORD | addr, devpriv->mmio + P_DEBICMD);
	val = readl(devpriv->mmio + P_DEBIAD);
254
255
	val &= mask;
	val |= wdata;
256
	writel(val & 0xffff, devpriv->mmio + P_DEBIAD);
257
	DEBItransfer(dev);
258
259
}

260
261
262
263
/* **************  EEPROM ACCESS FUNCTIONS  ************** */

static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
{
264
	struct s626_private *devpriv = dev->private;
265
	unsigned int ctrl;
266

267
	/* Write I2C command to I2C Transfer Control shadow register */
268
	writel(val, devpriv->mmio + P_I2CCTRL);
269

270
271
272
273
274
	/*
	 * Upload I2C shadow registers into working registers and
	 * wait for upload confirmation.
	 */
	s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
275
	while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2))
276
277
		;

278
279
	/* Wait until I2C bus transfer is finished or an error occurs */
	do {
280
		ctrl = readl(devpriv->mmio + P_I2CCTRL);
281
	} while ((ctrl & (I2C_BUSY | I2C_ERR)) == I2C_BUSY);
282

283
284
	/* Return non-zero if I2C error occurred */
	return ctrl & I2C_ERR;
285
286
287
288
289
}

/*  Read uint8_t from EEPROM. */
static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
{
290
	struct s626_private *devpriv = dev->private;
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317

	/*  Send EEPROM target address. */
	if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
			 /* Byte2 = I2C command: write to I2C EEPROM  device. */
			 | I2C_B1(I2C_ATTRSTOP, addr)
			 /* Byte1 = EEPROM internal target address. */
			 | I2C_B0(I2C_ATTRNOP, 0))) {	/*  Byte0 = Not sent. */
		/*  Abort function and declare error if handshake failed. */
		return 0;
	}
	/*  Execute EEPROM read. */
	if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR)

			 /*  Byte2 = I2C */
			 /*  command: read */
			 /*  from I2C EEPROM */
			 /*  device. */
			 |I2C_B1(I2C_ATTRSTOP, 0)

			 /*  Byte1 receives */
			 /*  uint8_t from */
			 /*  EEPROM. */
			 |I2C_B0(I2C_ATTRNOP, 0))) {	/*  Byte0 = Not  sent. */

		/*  Abort function and declare error if handshake failed. */
		return 0;
	}
318

319
	return (readl(devpriv->mmio + P_I2CCTRL) >> 16) & 0xff;
320
321
}

322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
/* ***********  DAC FUNCTIONS *********** */

/*  Slot 0 base settings. */
#define VECT0	(XSD2 | RSD3 | SIB_A2)
/*  Slot 0 always shifts in  0xFF and store it to  FB_BUFFER2. */

/*  TrimDac LogicalChan-to-PhysicalChan mapping table. */
static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };

/*  TrimDac LogicalChan-to-EepromAdrs mapping table. */
static uint8_t trimadrs[] = { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };

/* Private helper function: Transmit serial data to DAC via Audio
 * channel 2.  Assumes: (1) TSL2 slot records initialized, and (2)
 * Dacpol contains valid target image.
 */
static void SendDAC(struct comedi_device *dev, uint32_t val)
{
340
	struct s626_private *devpriv = dev->private;
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358

	/* START THE SERIAL CLOCK RUNNING ------------- */

	/* Assert DAC polarity control and enable gating of DAC serial clock
	 * and audio bit stream signals.  At this point in time we must be
	 * assured of being in time slot 0.  If we are not in slot 0, the
	 * serial clock and audio stream signals will be disabled; this is
	 * because the following DEBIwrite statement (which enables signals
	 * to be passed through the gate array) would execute before the
	 * trailing edge of WS1/WS3 (which turns off the signals), thus
	 * causing the signals to be inactive during the DAC write.
	 */
	DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);

	/* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */

	/* Copy DAC setpoint value to DAC's output DMA buffer. */

359
	/* writel(val, devpriv->mmio + (uint32_t)devpriv->pDacWBuf); */
360
361
	*devpriv->pDacWBuf = val;

362
363
364
	/*
	 * Enable the output DMA transfer. This will cause the DMAC to copy
	 * the DAC's data value to A2's output FIFO. The DMA transfer will
365
366
367
	 * then immediately terminate because the protection address is
	 * reached upon transfer of the first DWORD value.
	 */
368
	s626_mc_enable(dev, MC1_A2OUT, P_MC1);
369
370
371

	/*  While the DMA transfer is executing ... */

372
373
374
375
	/*
	 * Reset Audio2 output FIFO's underflow flag (along with any
	 * other FIFO underflow/overflow flags). When set, this flag
	 * will indicate that we have emerged from slot 0.
376
	 */
377
	writel(ISR_AFOU, devpriv->mmio + P_ISR);
378
379
380
381
382
383
384

	/* Wait for the DMA transfer to finish so that there will be data
	 * available in the FIFO when time slot 1 tries to transfer a DWORD
	 * from the FIFO to the output buffer register.  We test for DMA
	 * Done by polling the DMAC enable flag; this flag is automatically
	 * cleared when the transfer has finished.
	 */
385
	while (readl(devpriv->mmio + P_MC1) & MC1_A2OUT)
386
387
388
389
390
391
392
393
394
		;

	/* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */

	/* FIFO data is now available, so we enable execution of time slots
	 * 1 and higher by clearing the EOS flag in slot 0.  Note that SD3
	 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
	 * detection.
	 */
395
	writel(XSD2 | RSD3 | SIB_A2, devpriv->mmio + VECTPORT(0));
396
397
398
399
400
401
402

	/* Wait for slot 1 to execute to ensure that the Packet will be
	 * transmitted.  This is detected by polling the Audio2 output FIFO
	 * underflow flag, which will be set when slot 1 execution has
	 * finished transferring the DAC's data DWORD from the output FIFO
	 * to the output buffer register.
	 */
403
	while (!(readl(devpriv->mmio + P_SSR) & SSR_AF2_OUT))
404
405
406
407
408
409
410
411
		;

	/* Set up to trap execution at slot 0 when the TSL sequencer cycles
	 * back to slot 0 after executing the EOS in slot 5.  Also,
	 * simultaneously shift out and in the 0x00 that is ALWAYS the value
	 * stored in the last byte to be shifted out of the FIFO's DWORD
	 * buffer register.
	 */
412
	writel(XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS,
413
	       devpriv->mmio + VECTPORT(0));
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433

	/* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */

	/* Wait for the TSL to finish executing all time slots before
	 * exiting this function.  We must do this so that the next DAC
	 * write doesn't start, thereby enabling clock/chip select signals:
	 *
	 * 1. Before the TSL sequence cycles back to slot 0, which disables
	 *    the clock/cs signal gating and traps slot // list execution.
	 *    we have not yet finished slot 5 then the clock/cs signals are
	 *    still gated and we have not finished transmitting the stream.
	 *
	 * 2. While slots 2-5 are executing due to a late slot 0 trap.  In
	 *    this case, the slot sequence is currently repeating, but with
	 *    clock/cs signals disabled.  We must wait for slot 0 to trap
	 *    execution before setting up the next DAC setpoint DMA transfer
	 *    and enabling the clock/cs signals.  To detect the end of slot 5,
	 *    we test for the FB_BUFFER2 MSB contents to be equal to 0xFF.  If
	 *    the TSL has not yet finished executing slot 5 ...
	 */
434
	if (readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000) {
435
436
437
438
439
440
		/* The trap was set on time and we are still executing somewhere
		 * in slots 2-5, so we now wait for slot 0 to execute and trap
		 * TSL execution.  This is detected when FB_BUFFER2 MSB changes
		 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
		 * out/in on SD2 the 0x00 that is always referenced by slot 5.
		 */
441
		while (readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000)
442
443
444
445
446
447
448
449
450
451
			;
	}
	/* Either (1) we were too late setting the slot 0 trap; the TSL
	 * sequencer restarted slot 0 before we could set the EOS trap flag,
	 * or (2) we were not late and execution is now trapped at slot 0.
	 * In either case, we must now change slot 0 so that it will store
	 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
	 * In order to do this, we reprogram slot 0 so that it will shift in
	 * SD3, which is driven only by a pull-up resistor.
	 */
452
	writel(RSD3 | SIB_A2 | EOS, devpriv->mmio + VECTPORT(0));
453
454
455
456
457

	/* Wait for slot 0 to execute, at which time the TSL is setup for
	 * the next DAC write.  This is detected when FB_BUFFER2 MSB changes
	 * from 0x00 to 0xFF.
	 */
458
	while (!(readl(devpriv->mmio + P_FB_BUFFER2) & 0xff000000))
459
460
461
462
463
464
		;
}

/*  Private helper function: Write setpoint to an application DAC channel. */
static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
{
465
	struct s626_private *devpriv = dev->private;
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
	register uint16_t signmask;
	register uint32_t WSImage;

	/*  Adjust DAC data polarity and set up Polarity Control Register */
	/*  image. */
	signmask = 1 << chan;
	if (dacdata < 0) {
		dacdata = -dacdata;
		devpriv->Dacpol |= signmask;
	} else
		devpriv->Dacpol &= ~signmask;

	/*  Limit DAC setpoint value to valid range. */
	if ((uint16_t) dacdata > 0x1FFF)
		dacdata = 0x1FFF;

	/* Set up TSL2 records (aka "vectors") for DAC update.  Vectors V2
	 * and V3 transmit the setpoint to the target DAC.  V4 and V5 send
	 * data to a non-existent TrimDac channel just to keep the clock
	 * running after sending data to the target DAC.  This is necessary
	 * to eliminate the clock glitch that would otherwise occur at the
	 * end of the target DAC's serial data stream.  When the sequence
	 * restarts at V0 (after executing V5), the gate array automatically
	 * disables gating for the DAC clock and all DAC chip selects.
	 */

492
	/* Choose DAC chip select to be asserted */
493
	WSImage = (chan & 2) ? WS1 : WS2;
494
	/* Slot 2: Transmit high data byte to target DAC */
495
	writel(XSD2 | XFIFO_1 | WSImage, devpriv->mmio + VECTPORT(2));
496
	/* Slot 3: Transmit low data byte to target DAC */
497
	writel(XSD2 | XFIFO_0 | WSImage, devpriv->mmio + VECTPORT(3));
498
	/* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
499
	writel(XSD2 | XFIFO_3 | WS3, devpriv->mmio + VECTPORT(4));
500
	/* Slot 5: running after writing target DAC's low data byte */
501
	writel(XSD2 | XFIFO_2 | WS3 | EOS, devpriv->mmio + VECTPORT(5));
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522

	/*  Construct and transmit target DAC's serial packet:
	 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
	 * and D<12:0> is the DAC setpoint.  Append a WORD value (that writes
	 * to a  non-existent TrimDac channel) that serves to keep the clock
	 * running after the packet has been sent to the target DAC.
	 */
	SendDAC(dev, 0x0F000000
		/* Continue clock after target DAC data (write to non-existent trimdac). */
		| 0x00004000
		/* Address the two main dual-DAC devices (TSL's chip select enables
		 * target device). */
		| ((uint32_t) (chan & 1) << 15)
		/*  Address the DAC channel within the  device. */
		| (uint32_t) dacdata);	/*  Include DAC setpoint data. */

}

static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
			 uint8_t DacData)
{
523
	struct s626_private *devpriv = dev->private;
524
525
526
527
528
529
530
531
532
533
534
535
536
	uint32_t chan;

	/*  Save the new setpoint in case the application needs to read it back later. */
	devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData;

	/*  Map logical channel number to physical channel number. */
	chan = (uint32_t) trimchan[LogicalChan];

	/* Set up TSL2 records for TrimDac write operation.  All slots shift
	 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
	 * can be detected.
	 */

537
	/* Slot 2: Send high uint8_t to target TrimDac */
538
	writel(XSD2 | XFIFO_1 | WS3, devpriv->mmio + VECTPORT(2));
539
	/* Slot 3: Send low uint8_t to target TrimDac */
540
	writel(XSD2 | XFIFO_0 | WS3, devpriv->mmio + VECTPORT(3));
541
	/* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
542
	writel(XSD2 | XFIFO_3 | WS1, devpriv->mmio + VECTPORT(4));
543
	/* Slot 5: Send NOP low  uint8_t to DAC0 */
544
	writel(XSD2 | XFIFO_2 | WS1 | EOS, devpriv->mmio + VECTPORT(5));
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567

	/* Construct and transmit target DAC's serial packet:
	 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
	 * DAC channel's address, and D<7:0> is the DAC setpoint.  Append a
	 * WORD value (that writes a channel 0 NOP command to a non-existent
	 * main DAC channel) that serves to keep the clock running after the
	 * packet has been sent to the target DAC.
	 */

	/*  Address the DAC channel within the trimdac device. */
	SendDAC(dev, ((uint32_t) chan << 8)
		| (uint32_t) DacData);	/*  Include DAC setpoint data. */
}

static void LoadTrimDACs(struct comedi_device *dev)
{
	register uint8_t i;

	/*  Copy TrimDac setpoint values from EEPROM to TrimDacs. */
	for (i = 0; i < ARRAY_SIZE(trimchan); i++)
		WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i]));
}

568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
/* ******  COUNTER FUNCTIONS  ******* */
/* All counter functions address a specific counter by means of the
 * "Counter" argument, which is a logical counter number.  The Counter
 * argument may have any of the following legal values: 0=0A, 1=1A,
 * 2=2A, 3=0B, 4=1B, 5=2B.
 */

/*  Read a counter's output latch. */
static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k)
{
	register uint32_t value;

	/*  Latch counts and fetch LSW of latched counts value. */
	value = (uint32_t) DEBIread(dev, k->MyLatchLsw);

	/*  Fetch MSW of latched counts and combine with LSW. */
	value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16);

	/*  Return latched counts. */
	return value;
}

/* Return/set a counter pair's latch trigger source.  0: On read
 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
 * latches B.
 */
static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
			   uint16_t value)
{
	DEBIreplace(dev, k->MyCRB,
598
599
		    ~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC),
		    value << CRBBIT_LATCHSRC);
600
601
602
603
604
605
}

/*  Write value into counter preload register. */
static void Preload(struct comedi_device *dev, struct enc_private *k,
		    uint32_t value)
{
606
	DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value);
607
608
609
610
	DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2),
		  (uint16_t) (value >> 16));
}

611
static unsigned int s626_ai_reg_to_uint(int data)
612
{
613
	unsigned int tempdata;
614

615
616
617
618
619
	tempdata = (data >> 18);
	if (tempdata & 0x2000)
		tempdata &= 0x1fff;
	else
		tempdata += (1 << 13);
620

621
622
	return tempdata;
}
623

624
625
626
/* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data){ */
/*   return 0; */
/* } */
627

628
629
static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
{
630
631
	unsigned int group = chan / 16;
	unsigned int mask = 1 << (chan - (16 * group));
632
633
634
	unsigned int status;

	/* set channel to capture positive edge */
635
636
	status = DEBIread(dev, LP_RDEDGSEL(group));
	DEBIwrite(dev, LP_WREDGSEL(group), mask | status);
637
638

	/* enable interrupt on selected channel */
639
640
	status = DEBIread(dev, LP_RDINTSEL(group));
	DEBIwrite(dev, LP_WRINTSEL(group), mask | status);
641
642
643
644
645

	/* enable edge capture write command */
	DEBIwrite(dev, LP_MISC1, MISC1_EDCAP);

	/* enable edge capture on selected channel */
646
647
	status = DEBIread(dev, LP_RDCAPSEL(group));
	DEBIwrite(dev, LP_WRCAPSEL(group), mask | status);
648
649
650
651
652
653
654
655
656
657
658

	return 0;
}

static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
			      unsigned int mask)
{
	/* disable edge capture write command */
	DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);

	/* enable edge capture on selected channel */
659
	DEBIwrite(dev, LP_WRCAPSEL(group), mask);
660
661
662
663
664
665
666
667
668
669
670

	return 0;
}

static int s626_dio_clear_irq(struct comedi_device *dev)
{
	unsigned int group;

	/* disable edge capture write command */
	DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);

671
672
673
	/* clear all dio pending events and interrupt */
	for (group = 0; group < S626_DIO_BANKS; group++)
		DEBIwrite(dev, LP_WRCAPSEL(group), 0xffff);
674
675
676
677

	return 0;
}

678
679
680
681
682
683
684
685
686
687
688
689
690
691
static void handle_dio_interrupt(struct comedi_device *dev,
				 uint16_t irqbit, uint8_t group)
{
	struct s626_private *devpriv = dev->private;
	struct comedi_subdevice *s = dev->read_subdev;
	struct comedi_cmd *cmd = &s->async->cmd;

	s626_dio_reset_irq(dev, group, irqbit);

	if (devpriv->ai_cmd_running) {
		/* check if interrupt is an ai acquisition start trigger */
		if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
		    cmd->start_src == TRIG_EXT) {
			/* Start executing the RPS program */
692
			s626_mc_enable(dev, MC1_ERPS1, P_MC1);
693
694
695
696
697
698

			if (cmd->scan_begin_src == TRIG_EXT)
				s626_dio_set_irq(dev, cmd->scan_begin_arg);
		}
		if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
		    cmd->scan_begin_src == TRIG_EXT) {
699
700
			/* Trigger ADC scan loop start */
			s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716

			if (cmd->convert_src == TRIG_EXT) {
				devpriv->ai_convert_count = cmd->chanlist_len;

				s626_dio_set_irq(dev, cmd->convert_arg);
			}

			if (cmd->convert_src == TRIG_TIMER) {
				struct enc_private *k = &encpriv[5];

				devpriv->ai_convert_count = cmd->chanlist_len;
				k->SetEnable(dev, k, CLKENAB_ALWAYS);
			}
		}
		if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
		    cmd->convert_src == TRIG_EXT) {
717
718
			/* Trigger ADC scan loop start */
			s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744

			devpriv->ai_convert_count--;
			if (devpriv->ai_convert_count > 0)
				s626_dio_set_irq(dev, cmd->convert_arg);
		}
	}
}

static void check_dio_interrupts(struct comedi_device *dev)
{
	uint16_t irqbit;
	uint8_t group;

	for (group = 0; group < S626_DIO_BANKS; group++) {
		irqbit = 0;
		/* read interrupt type */
		irqbit = DEBIread(dev, LP_RDCAPFLG(group));

		/* check if interrupt is generated from dio channels */
		if (irqbit) {
			handle_dio_interrupt(dev, irqbit, group);
			return;
		}
	}
}

745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
static void check_counter_interrupts(struct comedi_device *dev)
{
	struct s626_private *devpriv = dev->private;
	struct comedi_subdevice *s = dev->read_subdev;
	struct comedi_async *async = s->async;
	struct comedi_cmd *cmd = &async->cmd;
	struct enc_private *k;
	uint16_t irqbit;

	/* read interrupt type */
	irqbit = DEBIread(dev, LP_RDMISC2);

	/* check interrupt on counters */
	if (irqbit & IRQ_COINT1A) {
		k = &encpriv[0];

		/* clear interrupt capture flag */
		k->ResetCapFlags(dev, k);
	}
	if (irqbit & IRQ_COINT2A) {
		k = &encpriv[1];

		/* clear interrupt capture flag */
		k->ResetCapFlags(dev, k);
	}
	if (irqbit & IRQ_COINT3A) {
		k = &encpriv[2];

		/* clear interrupt capture flag */
		k->ResetCapFlags(dev, k);
	}
	if (irqbit & IRQ_COINT1B) {
		k = &encpriv[3];

		/* clear interrupt capture flag */
		k->ResetCapFlags(dev, k);
	}
	if (irqbit & IRQ_COINT2B) {
		k = &encpriv[4];

		/* clear interrupt capture flag */
		k->ResetCapFlags(dev, k);

		if (devpriv->ai_convert_count > 0) {
			devpriv->ai_convert_count--;
			if (devpriv->ai_convert_count == 0)
				k->SetEnable(dev, k, CLKENAB_INDEX);

			if (cmd->convert_src == TRIG_TIMER) {
794
795
				/* Trigger ADC scan loop start */
				s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
796
797
798
799
800
801
802
803
804
805
			}
		}
	}
	if (irqbit & IRQ_COINT3B) {
		k = &encpriv[5];

		/* clear interrupt capture flag */
		k->ResetCapFlags(dev, k);

		if (cmd->scan_begin_src == TRIG_TIMER) {
806
807
			/* Trigger ADC scan loop start */
			s626_mc_enable(dev, MC2_ADC_RPS, P_MC2);
808
809
810
811
812
813
814
815
816
817
		}

		if (cmd->convert_src == TRIG_TIMER) {
			k = &encpriv[4];
			devpriv->ai_convert_count = cmd->chanlist_len;
			k->SetEnable(dev, k, CLKENAB_ALWAYS);
		}
	}
}

818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
static bool handle_eos_interrupt(struct comedi_device *dev)
{
	struct s626_private *devpriv = dev->private;
	struct comedi_subdevice *s = dev->read_subdev;
	struct comedi_async *async = s->async;
	struct comedi_cmd *cmd = &async->cmd;
	/*
	 * Init ptr to DMA buffer that holds new ADC data.  We skip the
	 * first uint16_t in the buffer because it contains junk data
	 * from the final ADC of the previous poll list scan.
	 */
	int32_t *readaddr = (int32_t *)devpriv->ANABuf.LogicalBase + 1;
	bool finished = false;
	int i;

	/* get the data and hand it over to comedi */
	for (i = 0; i < cmd->chanlist_len; i++) {
		short tempdata;

		/*
		 * Convert ADC data to 16-bit integer values and copy
		 * to application buffer.
		 */
		tempdata = s626_ai_reg_to_uint((int)*readaddr);
		readaddr++;

		/* put data into read buffer */
		/* comedi_buf_put(async, tempdata); */
		cfc_write_to_buffer(s, tempdata);
	}

	/* end of scan occurs */
	async->events |= COMEDI_CB_EOS;

	if (!devpriv->ai_continous)
		devpriv->ai_sample_count--;
	if (devpriv->ai_sample_count <= 0) {
		devpriv->ai_cmd_running = 0;

857
858
		/* Stop RPS program */
		s626_mc_disable(dev, MC1_ERPS1, P_MC1);
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875

		/* send end of acquisition */
		async->events |= COMEDI_CB_EOA;

		/* disable master interrupt */
		finished = true;
	}

	if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
		s626_dio_set_irq(dev, cmd->scan_begin_arg);

	/* tell comedi that data is there */
	comedi_event(dev, s);

	return finished;
}

876
877
878
static irqreturn_t s626_irq_handler(int irq, void *d)
{
	struct comedi_device *dev = d;
879
	struct s626_private *devpriv = dev->private;
880
881
	unsigned long flags;
	uint32_t irqtype, irqstatus;
882

883
	if (!dev->attached)
884
885
886
		return IRQ_NONE;
	/*  lock to avoid race with comedi_poll */
	spin_lock_irqsave(&dev->spinlock, flags);
887

888
	/* save interrupt enable register state */
889
	irqstatus = readl(devpriv->mmio + P_IER);
890

891
	/* read interrupt type */
892
	irqtype = readl(devpriv->mmio + P_ISR);
893

894
	/* disable master interrupt */
895
	writel(0, devpriv->mmio + P_IER);
896

897
	/* clear interrupt */
898
	writel(irqtype, devpriv->mmio + P_ISR);
899

900
901
	switch (irqtype) {
	case IRQ_RPS1:		/*  end_of_scan occurs */
902
		if (handle_eos_interrupt(dev))
903
904
905
906
			irqstatus = 0;
		break;
	case IRQ_GPIO3:	/* check dio and conter interrupt */
		/* s626_dio_clear_irq(dev); */
907
		check_dio_interrupts(dev);
908
909
		check_counter_interrupts(dev);
		break;
910
	}
911

912
	/* enable interrupt */
913
	writel(irqstatus, devpriv->mmio + P_IER);
914

915
916
917
	spin_unlock_irqrestore(&dev->spinlock, flags);
	return IRQ_HANDLED;
}
918

919
920
921
922
923
/*
 * this functions build the RPS program for hardware driven acquistion
 */
static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
{
924
	struct s626_private *devpriv = dev->private;
925
926
927
928
929
930
	register uint32_t *pRPS;
	uint32_t JmpAdrs;
	uint16_t i;
	uint16_t n;
	uint32_t LocalPPL;
	struct comedi_cmd *cmd = &(dev->subdevices->async->cmd);
931

932
933
	/* Stop RPS program in case it is currently running */
	s626_mc_disable(dev, MC1_ERPS1, P_MC1);
934

935
936
	/*  Set starting logical address to write RPS commands. */
	pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
937

938
939
	/* Initialize RPS instruction pointer */
	writel((uint32_t)devpriv->RPSBuf.PhysicalBase,
940
	       devpriv->mmio + P_RPSADDR1);
941

942
	/*  Construct RPS program in RPSBuf DMA buffer */
943

944
945
946
947
948
	if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
		/*  Wait for Start trigger. */
		*pRPS++ = RPS_PAUSE | RPS_SIGADC;
		*pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
	}
949

950
951
952
953
954
955
956
957
958
	/* SAA7146 BUG WORKAROUND Do a dummy DEBI Write.  This is necessary
	 * because the first RPS DEBI Write following a non-RPS DEBI write
	 * seems to always fail.  If we don't do this dummy write, the ADC
	 * gain might not be set to the value required for the first slot in
	 * the poll list; the ADC gain would instead remain unchanged from
	 * the previously programmed value.
	 */
	*pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
	/* Write DEBI Write command and address to shadow RAM. */
959

960
961
962
	*pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
	*pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
	/*  Write DEBI immediate data  to shadow RAM: */
963

964
965
	*pRPS++ = GSEL_BIPOLAR5V;
	/*  arbitrary immediate data  value. */
966

967
968
969
970
	*pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
	/*  Reset "shadow RAM  uploaded" flag. */
	*pRPS++ = RPS_UPLOAD | RPS_DEBI;	/*  Invoke shadow RAM upload. */
	*pRPS++ = RPS_PAUSE | RPS_DEBI;	/*  Wait for shadow upload to finish. */
971

972
973
974
975
976
977
978
979
980
	/* Digitize all slots in the poll list. This is implemented as a
	 * for loop to limit the slot count to 16 in case the application
	 * forgot to set the EOPL flag in the final slot.
	 */
	for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
		/* Convert application's poll list item to private board class
		 * format.  Each app poll list item is an uint8_t with form
		 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
		 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
981
		 */
982
983
984
		LocalPPL =
		    (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
				   GSEL_BIPOLAR10V);
985

986
987
988
989
990
991
992
993
994
995
996
997
998
999
		/*  Switch ADC analog gain. */
		*pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);	/*  Write DEBI command */
		/*  and address to */
		/*  shadow RAM. */
		*pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
		*pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);	/*  Write DEBI */
		/*  immediate data to */
		/*  shadow RAM. */
		*pRPS++ = LocalPPL;
		*pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;	/*  Reset "shadow RAM uploaded" */
		/*  flag. */
		*pRPS++ = RPS_UPLOAD | RPS_DEBI;	/*  Invoke shadow RAM upload. */
		*pRPS++ = RPS_PAUSE | RPS_DEBI;	/*  Wait for shadow upload to */
		/*  finish. */
1000