rtd520.c 57.1 KB
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/*
    comedi/drivers/rtd520.c
    Comedi driver for Real Time Devices (RTD) PCI4520/DM7520

    COMEDI - Linux Control and Measurement Device Interface
    Copyright (C) 2001 David A. Schleef <ds@schleef.org>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
Driver: rtd520
Description: Real Time Devices PCI4520/DM7520
Author: Dan Christian
Devices: [Real Time Devices] DM7520HR-1 (rtd520), DM7520HR-8,
  PCI4520, PCI4520-8
Status: Works.  Only tested on DM7520-8.  Not SMP safe.

Configuration options:
  [0] - PCI bus of device (optional)
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	If bus / slot is not specified, the first available PCI
	device will be used.
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  [1] - PCI slot of device (optional)
*/
/*
    Created by Dan Christian, NASA Ames Research Center.

    The PCI4520 is a PCI card.  The DM7520 is a PC/104-plus card.
    Both have:
    8/16 12 bit ADC with FIFO and channel gain table
    8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
    8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
    2 12 bit DACs with FIFOs
    2 bits output
    2 bits input
    bus mastering DMA
    timers: ADC sample, pacer, burst, about, delay, DA1, DA2
    sample counter
    3 user timer/counters (8254)
    external interrupt

    The DM7520 has slightly fewer features (fewer gain steps).

    These boards can support external multiplexors and multi-board
    synchronization, but this driver doesn't support that.

    Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
    Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
    Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
    Call them and ask for the register level manual.
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    PCI chip: http://www.plxtech.com/products/io/pci9080
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    Notes:
    This board is memory mapped.  There is some IO stuff, but it isn't needed.

    I use a pretty loose naming style within the driver (rtd_blah).
    All externally visible names should be rtd520_blah.
    I use camelCase for structures (and inside them).
    I may also use upper CamelCase for function names (old habit).

    This board is somewhat related to the RTD PCI4400 board.

    I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
    das1800, since they have the best documented code.  Driver
    cb_pcidas64.c uses the same DMA controller.

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    As far as I can tell, the About interrupt doesn't work if Sample is
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    also enabled.  It turns out that About really isn't needed, since
    we always count down samples read.

    There was some timer/counter code, but it didn't follow the right API.

*/

/*
  driver status:

  Analog-In supports instruction and command mode.

  With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
  (single channel, 64K read buffer).  I get random system lockups when
  using DMA with ALI-15xx based systems.  I haven't been able to test
  any other chipsets.  The lockups happen soon after the start of an
  acquistion, not in the middle of a long run.

  Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
  (with a 256K read buffer).

  Digital-IO and Analog-Out only support instruction mode.

*/

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#include <linux/interrupt.h>
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#include <linux/delay.h>

#include "../comedidev.h"

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#include "comedi_fc.h"

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#define DRV_NAME "rtd520"

/*======================================================================
  Driver specific stuff (tunable)
======================================================================*/
/* Enable this to test the new DMA support. You may get hard lock ups */
/*#define USE_DMA*/

/* We really only need 2 buffers.  More than that means being much
   smarter about knowing which ones are full. */
#define DMA_CHAIN_COUNT 2	/* max DMA segments/buffers in a ring (min 2) */

/* Target period for periodic transfers.  This sets the user read latency. */
/* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
/* If this is too low, efficiency is poor */
#define TRANS_TARGET_PERIOD 10000000	/* 10 ms (in nanoseconds) */

/* Set a practical limit on how long a list to support (affects memory use) */
/* The board support a channel list up to the FIFO length (1K or 8K) */
#define RTD_MAX_CHANLIST	128	/* max channel list that we allow */

/* tuning for ai/ao instruction done polling */
#ifdef FAST_SPIN
#define WAIT_QUIETLY		/* as nothing, spin on done bit */
#define RTD_ADC_TIMEOUT	66000	/* 2 msec at 33mhz bus rate */
#define RTD_DAC_TIMEOUT	66000
#define RTD_DMA_TIMEOUT	33000	/* 1 msec */
#else
/* by delaying, power and electrical noise are reduced somewhat */
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#define WAIT_QUIETLY	udelay(1)
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#define RTD_ADC_TIMEOUT	2000	/* in usec */
#define RTD_DAC_TIMEOUT	2000	/* in usec */
#define RTD_DMA_TIMEOUT	1000	/* in usec */
#endif

/*======================================================================
  Board specific stuff
======================================================================*/

/* registers  */
#define PCI_VENDOR_ID_RTD	0x1435
/*
  The board has three memory windows: las0, las1, and lcfg (the PCI chip)
  Las1 has the data and can be burst DMAed 32bits at a time.
*/
#define LCFG_PCIINDEX	0
/* PCI region 1 is a 256 byte IO space mapping.  Use??? */
#define LAS0_PCIINDEX	2	/* PCI memory resources */
#define LAS1_PCIINDEX	3
#define LCFG_PCISIZE	0x100
#define LAS0_PCISIZE	0x200
#define LAS1_PCISIZE	0x10

#define RTD_CLOCK_RATE	8000000	/* 8Mhz onboard clock */
#define RTD_CLOCK_BASE	125	/* clock period in ns */

/* Note: these speed are slower than the spec, but fit the counter resolution*/
#define RTD_MAX_SPEED	1625	/* when sampling, in nanoseconds */
/* max speed if we don't have to wait for settling */
#define RTD_MAX_SPEED_1	875	/* if single channel, in nanoseconds */

#define RTD_MIN_SPEED	2097151875	/* (24bit counter) in nanoseconds */
/* min speed when only 1 channel (no burst counter) */
#define RTD_MIN_SPEED_1	5000000	/* 200Hz, in nanoseconds */

#include "rtd520.h"
#include "plx9080.h"

/* Setup continuous ring of 1/2 FIFO transfers.  See RTD manual p91 */
#define DMA_MODE_BITS (\
		       PLX_LOCAL_BUS_16_WIDE_BITS \
		       | PLX_DMA_EN_READYIN_BIT \
		       | PLX_DMA_LOCAL_BURST_EN_BIT \
		       | PLX_EN_CHAIN_BIT \
		       | PLX_DMA_INTR_PCI_BIT \
		       | PLX_LOCAL_ADDR_CONST_BIT \
		       | PLX_DEMAND_MODE_BIT)

#define DMA_TRANSFER_BITS (\
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/* descriptors in PCI memory*/  PLX_DESC_IN_PCI_BIT \
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/* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
/* from board to PCI */		| PLX_XFER_LOCAL_TO_PCI)

/*======================================================================
  Comedi specific stuff
======================================================================*/

/*
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 * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
 */
static const struct comedi_lrange rtd_ai_7520_range = {
	18, {
		/* +-5V input range gain steps */
		BIP_RANGE(5.0),
		BIP_RANGE(5.0 / 2),
		BIP_RANGE(5.0 / 4),
		BIP_RANGE(5.0 / 8),
		BIP_RANGE(5.0 / 16),
		BIP_RANGE(5.0 / 32),
		/* +-10V input range gain steps */
		BIP_RANGE(10.0),
		BIP_RANGE(10.0 / 2),
		BIP_RANGE(10.0 / 4),
		BIP_RANGE(10.0 / 8),
		BIP_RANGE(10.0 / 16),
		BIP_RANGE(10.0 / 32),
		/* +10V input range gain steps */
		UNI_RANGE(10.0),
		UNI_RANGE(10.0 / 2),
		UNI_RANGE(10.0 / 4),
		UNI_RANGE(10.0 / 8),
		UNI_RANGE(10.0 / 16),
		UNI_RANGE(10.0 / 32),
	}
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};

/* PCI4520 has two more gains (6 more entries) */
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static const struct comedi_lrange rtd_ai_4520_range = {
	24, {
		/* +-5V input range gain steps */
		BIP_RANGE(5.0),
		BIP_RANGE(5.0 / 2),
		BIP_RANGE(5.0 / 4),
		BIP_RANGE(5.0 / 8),
		BIP_RANGE(5.0 / 16),
		BIP_RANGE(5.0 / 32),
		BIP_RANGE(5.0 / 64),
		BIP_RANGE(5.0 / 128),
		/* +-10V input range gain steps */
		BIP_RANGE(10.0),
		BIP_RANGE(10.0 / 2),
		BIP_RANGE(10.0 / 4),
		BIP_RANGE(10.0 / 8),
		BIP_RANGE(10.0 / 16),
		BIP_RANGE(10.0 / 32),
		BIP_RANGE(10.0 / 64),
		BIP_RANGE(10.0 / 128),
		/* +10V input range gain steps */
		UNI_RANGE(10.0),
		UNI_RANGE(10.0 / 2),
		UNI_RANGE(10.0 / 4),
		UNI_RANGE(10.0 / 8),
		UNI_RANGE(10.0 / 16),
		UNI_RANGE(10.0 / 32),
		UNI_RANGE(10.0 / 64),
		UNI_RANGE(10.0 / 128),
	}
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};

/* Table order matches range values */
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static const struct comedi_lrange rtd_ao_range = {
	4, {
		UNI_RANGE(5),
		UNI_RANGE(10),
		BIP_RANGE(5),
		BIP_RANGE(10),
	}
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};

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struct rtdBoard {
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	const char *name;
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	int device_id;
	int aiChans;
	int aiBits;
	int aiMaxGain;
	int range10Start;	/* start of +-10V range */
	int rangeUniStart;	/* start of +10V range */
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};
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static const struct rtdBoard rtd520Boards[] = {
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	{
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		.name		= "DM7520",
		.device_id	= 0x7520,
		.aiChans	= 16,
		.aiBits		= 12,
		.aiMaxGain	= 32,
		.range10Start	= 6,
		.rangeUniStart	= 12,
	}, {
		.name		= "PCI4520",
		.device_id	= 0x4520,
		.aiChans	= 16,
		.aiBits		= 12,
		.aiMaxGain	= 128,
		.range10Start	= 8,
		.rangeUniStart	= 16,
	},
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};

/*
   This structure is for data unique to this hardware driver.
   This is also unique for each board in the system.
*/
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struct rtdPrivate {
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	/* memory mapped board structures */
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	void __iomem *las0;
	void __iomem *las1;
	void __iomem *lcfg;
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	unsigned long intCount;	/* interrupt count */
	long aiCount;		/* total transfer size (samples) */
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	int transCount;		/* # to transfer data. 0->1/2FIFO */
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	int flags;		/* flag event modes */

	/* channel list info */
	/* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
	unsigned char chanBipolar[RTD_MAX_CHANLIST / 8];	/* bit array */

	/* read back data */
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	unsigned int aoValue[2];	/* Used for AO read back */
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	/* timer gate (when enabled) */
	u8 utcGate[4];		/* 1 extra allows simple range check */

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	/* shadow registers affect other registers, but can't be read back */
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	/* The macros below update these on writes */
	u16 intMask;		/* interrupt mask */
	u16 intClearMask;	/* interrupt clear mask */
	u8 utcCtrl[4];		/* crtl mode for 3 utc + read back */
	u8 dioStatus;		/* could be read back (dio0Ctrl) */
#ifdef USE_DMA
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	/*
	 * Always DMA 1/2 FIFO.  Buffer (dmaBuff?) is (at least) twice that
	 * size.  After transferring, interrupt processes 1/2 FIFO and
	 * passes to comedi
	 */
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	s16 dma0Offset;		/* current processing offset (0, 1/2) */
	uint16_t *dma0Buff[DMA_CHAIN_COUNT];	/* DMA buffers (for ADC) */
	dma_addr_t dma0BuffPhysAddr[DMA_CHAIN_COUNT];	/* physical addresses */
	struct plx_dma_desc *dma0Chain;	/* DMA descriptor ring for dmaBuff */
	dma_addr_t dma0ChainPhysAddr;	/* physical addresses */
	/* shadow registers */
	u8 dma0Control;
	u8 dma1Control;
#endif				/* USE_DMA */
	unsigned fifoLen;
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};
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/* bit defines for "flags" */
#define SEND_EOS	0x01	/* send End Of Scan events */
#define DMA0_ACTIVE	0x02	/* DMA0 is active */
#define DMA1_ACTIVE	0x04	/* DMA1 is active */

/* Macros for accessing channel list bit array */
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#define CHAN_ARRAY_TEST(array, index) \
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	(((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
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#define CHAN_ARRAY_SET(array, index) \
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	(((array)[(index)/8] |= 1 << ((index) & 0x7)))
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#define CHAN_ARRAY_CLEAR(array, index) \
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	(((array)[(index)/8] &= ~(1 << ((index) & 0x7))))

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/*
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  Given a desired period and the clock period (both in ns),
  return the proper counter value (divider-1).
  Sets the original period to be the true value.
  Note: you have to check if the value is larger than the counter range!
*/
static int rtd_ns_to_timer_base(unsigned int *nanosec,	/* desired period (in ns) */
				int round_mode, int base)
{				/* clock period (in ns) */
	int divider;

	switch (round_mode) {
	case TRIG_ROUND_NEAREST:
	default:
		divider = (*nanosec + base / 2) / base;
		break;
	case TRIG_ROUND_DOWN:
		divider = (*nanosec) / base;
		break;
	case TRIG_ROUND_UP:
		divider = (*nanosec + base - 1) / base;
		break;
	}
	if (divider < 2)
		divider = 2;	/* min is divide by 2 */

	/* Note: we don't check for max, because different timers
	   have different ranges */

	*nanosec = base * divider;
	return divider - 1;	/* countdown is divisor+1 */
}
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/*
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  Given a desired period (in ns),
  return the proper counter value (divider-1) for the internal clock.
  Sets the original period to be the true value.
*/
static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
{
	return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
}
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/*
  Convert a single comedi channel-gain entry to a RTD520 table entry
*/
static unsigned short rtdConvertChanGain(struct comedi_device *dev,
					 unsigned int comediChan, int chanIndex)
{				/* index in channel list */
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	const struct rtdBoard *thisboard = comedi_board(dev);
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	struct rtdPrivate *devpriv = dev->private;
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	unsigned int chan, range, aref;
	unsigned short r = 0;
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	chan = CR_CHAN(comediChan);
	range = CR_RANGE(comediChan);
	aref = CR_AREF(comediChan);
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	r |= chan & 0xf;
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	/* Note: we also setup the channel list bipolar flag array */
	if (range < thisboard->range10Start) {	/* first batch are +-5 */
		r |= 0x000;	/* +-5 range */
		r |= (range & 0x7) << 4;	/* gain */
		CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
	} else if (range < thisboard->rangeUniStart) {	/* second batch are +-10 */
		r |= 0x100;	/* +-10 range */
		/* gain */
		r |= ((range - thisboard->range10Start) & 0x7) << 4;
		CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
	} else {		/* last batch is +10 */
		r |= 0x200;	/* +10 range */
		/* gain */
		r |= ((range - thisboard->rangeUniStart) & 0x7) << 4;
		CHAN_ARRAY_CLEAR(devpriv->chanBipolar, chanIndex);
	}
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	switch (aref) {
	case AREF_GROUND:	/* on-board ground */
		break;

	case AREF_COMMON:
		r |= 0x80;	/* ref external analog common */
		break;

	case AREF_DIFF:
		r |= 0x400;	/* differential inputs */
		break;

	case AREF_OTHER:	/* ??? */
		break;
	}
	/*printk ("chan=%d r=%d a=%d -> 0x%x\n",
	   chan, range, aref, r); */
	return r;
}

/*
  Setup the channel-gain table from a comedi list
*/
static void rtd_load_channelgain_list(struct comedi_device *dev,
				      unsigned int n_chan, unsigned int *list)
{
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	struct rtdPrivate *devpriv = dev->private;

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	if (n_chan > 1) {	/* setup channel gain table */
		int ii;
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		writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
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		writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
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		for (ii = 0; ii < n_chan; ii++) {
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			writel(rtdConvertChanGain(dev, list[ii], ii),
				devpriv->las0 + LAS0_CGT_WRITE);
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		}
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	} else {		/* just use the channel gain latch */
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		writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
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		writel(rtdConvertChanGain(dev, list[0], 0),
			devpriv->las0 + LAS0_CGL_WRITE);
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	}
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}

/* determine fifo size by doing adc conversions until the fifo half
empty status flag clears */
static int rtd520_probe_fifo_depth(struct comedi_device *dev)
{
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	struct rtdPrivate *devpriv = dev->private;
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	unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
	unsigned i;
	static const unsigned limit = 0x2000;
	unsigned fifo_size = 0;

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	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
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	rtd_load_channelgain_list(dev, 1, &chanspec);
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	/* ADC conversion trigger source: SOFTWARE */
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	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
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	/* convert  samples */
	for (i = 0; i < limit; ++i) {
		unsigned fifo_status;
		/* trigger conversion */
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		writew(0, devpriv->las0 + LAS0_ADC);
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		udelay(1);
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		fifo_status = readl(devpriv->las0 + LAS0_ADC);
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		if ((fifo_status & FS_ADC_HEMPTY) == 0) {
			fifo_size = 2 * i;
			break;
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		}
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	}
	if (i == limit) {
		printk(KERN_INFO "\ncomedi: %s: failed to probe fifo size.\n",
		       DRV_NAME);
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		return -EIO;
	}
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	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
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	if (fifo_size != 0x400 && fifo_size != 0x2000) {
		printk
		    (KERN_INFO "\ncomedi: %s: unexpected fifo size of %i, expected 1024 or 8192.\n",
		     DRV_NAME, fifo_size);
		return -EIO;
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	}
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	return fifo_size;
}
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/*
  "instructions" read/write data in "one-shot" or "software-triggered"
  mode (simplest case).
  This doesn't use interrupts.
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  Note, we don't do any settling delays.  Use a instruction list to
  select, delay, then read.
 */
static int rtd_ai_rinsn(struct comedi_device *dev,
			struct comedi_subdevice *s, struct comedi_insn *insn,
			unsigned int *data)
{
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	struct rtdPrivate *devpriv = dev->private;
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	int n, ii;
	int stat;
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	/* clear any old fifo data */
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	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
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	/* write channel to multiplexer and clear channel gain table */
	rtd_load_channelgain_list(dev, 1, &insn->chanspec);
545

546
	/* ADC conversion trigger source: SOFTWARE */
547
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
548

549
550
551
552
	/* convert n samples */
	for (n = 0; n < insn->n; n++) {
		s16 d;
		/* trigger conversion */
553
		writew(0, devpriv->las0 + LAS0_ADC);
554
555

		for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
556
			stat = readl(devpriv->las0 + LAS0_ADC);
557
558
559
560
561
562
563
564
565
566
567
568
			if (stat & FS_ADC_NOT_EMPTY)	/* 1 -> not empty */
				break;
			WAIT_QUIETLY;
		}
		if (ii >= RTD_ADC_TIMEOUT) {
			DPRINTK
			    ("rtd520: Error: ADC never finished! FifoStatus=0x%x\n",
			     stat ^ 0x6666);
			return -ETIMEDOUT;
		}

		/* read data */
569
		d = readw(devpriv->las1 + LAS1_ADC_FIFO);
570
571
572
573
574
575
576
		/*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
		d = d >> 3;	/* low 3 bits are marker lines */
		if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
			/* convert to comedi unsigned data */
			data[n] = d + 2048;
		else
			data[n] = d;
577
578
	}

579
580
581
	/* return the number of samples read/written */
	return n;
}
582

583
584
585
/*
  Get what we know is there.... Fast!
  This uses 1/2 the bus cycles of read_dregs (below).
586

587
588
589
590
591
  The manual claims that we can do a lword read, but it doesn't work here.
*/
static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
		     int count)
{
592
	struct rtdPrivate *devpriv = dev->private;
593
	int ii;
594

595
596
597
	for (ii = 0; ii < count; ii++) {
		short sample;
		s16 d;
598

599
		if (0 == devpriv->aiCount) {	/* done */
600
			d = readw(devpriv->las1 + LAS1_ADC_FIFO);
601
602
603
			continue;
		}
#if 0
604
		if (!(readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY)) {
605
606
607
608
609
			DPRINTK("comedi: READ OOPS on %d of %d\n", ii + 1,
				count);
			break;
		}
#endif
610
		d = readw(devpriv->las1 + LAS1_ADC_FIFO);
611

612
613
614
615
616
617
		d = d >> 3;	/* low 3 bits are marker lines */
		if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
			/* convert to comedi unsigned data */
			sample = d + 2048;
		} else
			sample = d;
618

619
620
		if (!comedi_buf_put(s->async, sample))
			return -1;
621

622
623
624
625
626
		if (devpriv->aiCount > 0)	/* < 0, means read forever */
			devpriv->aiCount--;
	}
	return 0;
}
627

628
629
630
631
632
/*
  unknown amout of data is waiting in fifo.
*/
static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
{
633
634
	struct rtdPrivate *devpriv = dev->private;

635
	while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
636
		short sample;
637
		s16 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
638

639
640
641
		if (0 == devpriv->aiCount) {	/* done */
			continue;	/* read rest */
		}
642

643
644
645
646
647
648
		d = d >> 3;	/* low 3 bits are marker lines */
		if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
			/* convert to comedi unsigned data */
			sample = d + 2048;
		} else
			sample = d;
649

650
651
		if (!comedi_buf_put(s->async, sample))
			return -1;
652

653
654
655
656
657
		if (devpriv->aiCount > 0)	/* < 0, means read forever */
			devpriv->aiCount--;
	}
	return 0;
}
658
659

#ifdef USE_DMA
660
661
662
663
664
/*
  Terminate a DMA transfer and wait for everything to quiet down
*/
void abort_dma(struct comedi_device *dev, unsigned int channel)
{				/* DMA channel 0, 1 */
665
	struct rtdPrivate *devpriv = dev->private;
666
667
668
669
	unsigned long dma_cs_addr;	/* the control/status register */
	uint8_t status;
	unsigned int ii;
	/* unsigned long flags; */
670

671
672
	dma_cs_addr = (unsigned long)devpriv->lcfg
	    + ((channel == 0) ? LCFG_DMACSR0 : LCFG_DMACSR1);
673

674
675
	/*  spinlock for plx dma control/status reg */
	/* spin_lock_irqsave( &dev->spinlock, flags ); */
676

677
678
679
680
681
682
683
	/*  abort dma transfer if necessary */
	status = readb(dma_cs_addr);
	if ((status & PLX_DMA_EN_BIT) == 0) {	/* not enabled (Error?) */
		DPRINTK("rtd520: AbortDma on non-active channel %d (0x%x)\n",
			channel, status);
		goto abortDmaExit;
	}
684

685
686
687
688
689
690
691
692
693
	/* wait to make sure done bit is zero (needed?) */
	for (ii = 0; (status & PLX_DMA_DONE_BIT) && ii < RTD_DMA_TIMEOUT; ii++) {
		WAIT_QUIETLY;
		status = readb(dma_cs_addr);
	}
	if (status & PLX_DMA_DONE_BIT) {
		printk("rtd520: Timeout waiting for dma %i done clear\n",
		       channel);
		goto abortDmaExit;
694
695
	}

696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
	/* disable channel (required) */
	writeb(0, dma_cs_addr);
	udelay(1);		/* needed?? */
	/* set abort bit for channel */
	writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);

	/*  wait for dma done bit to be set */
	status = readb(dma_cs_addr);
	for (ii = 0;
	     (status & PLX_DMA_DONE_BIT) == 0 && ii < RTD_DMA_TIMEOUT; ii++) {
		status = readb(dma_cs_addr);
		WAIT_QUIETLY;
	}
	if ((status & PLX_DMA_DONE_BIT) == 0) {
		printk("rtd520: Timeout waiting for dma %i done set\n",
		       channel);
712
713
	}

714
715
716
abortDmaExit:
	/* spin_unlock_irqrestore( &dev->spinlock, flags ); */
}
717

718
719
720
721
722
723
/*
  Process what is in the DMA transfer buffer and pass to comedi
  Note: this is not re-entrant
*/
static int ai_process_dma(struct comedi_device *dev, struct comedi_subdevice *s)
{
724
	struct rtdPrivate *devpriv = dev->private;
725
726
	int ii, n;
	s16 *dp;
727

728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
	if (devpriv->aiCount == 0)	/* transfer already complete */
		return 0;

	dp = devpriv->dma0Buff[devpriv->dma0Offset];
	for (ii = 0; ii < devpriv->fifoLen / 2;) {	/* convert samples */
		short sample;

		if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
			sample = (*dp >> 3) + 2048;	/* convert to comedi unsigned data */
		else
			sample = *dp >> 3;	/* low 3 bits are marker lines */

		*dp++ = sample;	/* put processed value back */

		if (++s->async->cur_chan >= s->async->cmd.chanlist_len)
			s->async->cur_chan = 0;

		++ii;		/* number ready to transfer */
		if (devpriv->aiCount > 0) {	/* < 0, means read forever */
			if (--devpriv->aiCount == 0) {	/* done */
				/*DPRINTK ("rtd520: Final %d samples\n", ii); */
				break;
			}
751
752
		}
	}
753
754
755
756
757
758
759
760
761

	/* now pass the whole array to the comedi buffer */
	dp = devpriv->dma0Buff[devpriv->dma0Offset];
	n = comedi_buf_write_alloc(s->async, ii * sizeof(s16));
	if (n < (ii * sizeof(s16))) {	/* any residual is an error */
		DPRINTK("rtd520:ai_process_dma buffer overflow %d samples!\n",
			ii - (n / sizeof(s16)));
		s->async->events |= COMEDI_CB_ERROR;
		return -1;
762
	}
763
764
	comedi_buf_memcpy_to(s->async, 0, dp, n);
	comedi_buf_write_free(s->async, n);
765

766
767
768
769
	/*
	 * always at least 1 scan -- 1/2 FIFO is larger than our max scan list
	 */
	s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
770

771
772
773
774
775
776
	if (++devpriv->dma0Offset >= DMA_CHAIN_COUNT) {	/* next buffer */
		devpriv->dma0Offset = 0;
	}
	return 0;
}
#endif /* USE_DMA */
777

778
779
780
781
782
783
784
785
786
/*
  Handle all rtd520 interrupts.
  Runs atomically and is never re-entered.
  This is a "slow handler";  other interrupts may be active.
  The data conversion may someday happen in a "bottom half".
*/
static irqreturn_t rtd_interrupt(int irq,	/* interrupt number (ignored) */
				 void *d)
{				/* our data *//* cpu context (ignored) */
787
	struct comedi_device *dev = d;
788
	struct comedi_subdevice *s = &dev->subdevices[0];
789
	struct rtdPrivate *devpriv = dev->private;
790
	u32 overrun;
791
792
	u16 status;
	u16 fifoStatus;
793

794
795
	if (!dev->attached)
		return IRQ_NONE;
796

797
	devpriv->intCount++;	/* DEBUG statistics */
798

799
	fifoStatus = readl(devpriv->las0 + LAS0_ADC);
800
801
802
803
804
	/* check for FIFO full, this automatically halts the ADC! */
	if (!(fifoStatus & FS_ADC_NOT_FULL)) {	/* 0 -> full */
		DPRINTK("rtd520: FIFO full! fifo_status=0x%x\n", (fifoStatus ^ 0x6666) & 0x7777);	/* should be all 0s */
		goto abortTransfer;
	}
805
#ifdef USE_DMA
806
	if (devpriv->flags & DMA0_ACTIVE) {	/* Check DMA */
807
		u32 istatus = readl(devpriv->lcfg + LCFG_ITCSR);
808

809
810
811
812
813
		if (istatus & ICS_DMA0_A) {
			if (ai_process_dma(dev, s) < 0) {
				DPRINTK
				    ("rtd520: comedi read buffer overflow (DMA) with %ld to go!\n",
				     devpriv->aiCount);
814
815
816
817
				devpriv->dma0Control &= ~PLX_DMA_START_BIT;
				devpriv->dma0Control |= PLX_CLEAR_DMA_INTR_BIT;
				writeb(devpriv->dma0Control,
					devpriv->lcfg + LCFG_DMACSR0);
818
				goto abortTransfer;
819
			}
820
821
822

			/*DPRINTK ("rtd520: DMA transfer: %ld to go, istatus %x\n",
			   devpriv->aiCount, istatus); */
823
824
825
826
			devpriv->dma0Control &= ~PLX_DMA_START_BIT;
			devpriv->dma0Control |= PLX_CLEAR_DMA_INTR_BIT;
			writeb(devpriv->dma0Control,
				devpriv->lcfg + LCFG_DMACSR0);
827
828
829
830
831
832
833
			if (0 == devpriv->aiCount) {	/* counted down */
				DPRINTK("rtd520: Samples Done (DMA).\n");
				goto transferDone;
			}
			comedi_event(dev, s);
		} else {
			/*DPRINTK ("rtd520: No DMA ready: istatus %x\n", istatus); */
834
		}
835
836
	}
	/* Fall through and check for other interrupt sources */
837
#endif /* USE_DMA */
838

839
	status = readw(devpriv->las0 + LAS0_IT);
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
	/* if interrupt was not caused by our board, or handled above */
	if (0 == status)
		return IRQ_HANDLED;

	if (status & IRQM_ADC_ABOUT_CNT) {	/* sample count -> read FIFO */
		/* since the priority interrupt controller may have queued a sample
		   counter interrupt, even though we have already finished,
		   we must handle the possibility that there is no data here */
		if (!(fifoStatus & FS_ADC_HEMPTY)) {	/* 0 -> 1/2 full */
			/*DPRINTK("rtd520: Sample int, reading 1/2FIFO.  fifo_status 0x%x\n",
			   (fifoStatus ^ 0x6666) & 0x7777); */
			if (ai_read_n(dev, s, devpriv->fifoLen / 2) < 0) {
				DPRINTK
				    ("rtd520: comedi read buffer overflow (1/2FIFO) with %ld to go!\n",
				     devpriv->aiCount);
				goto abortTransfer;
			}
			if (0 == devpriv->aiCount) {	/* counted down */
				DPRINTK("rtd520: Samples Done (1/2). fifo_status was 0x%x\n", (fifoStatus ^ 0x6666) & 0x7777);	/* should be all 0s */
				goto transferDone;
			}
			comedi_event(dev, s);
		} else if (devpriv->transCount > 0) {	/* read often */
			/*DPRINTK("rtd520: Sample int, reading %d  fifo_status 0x%x\n",
			   devpriv->transCount, (fifoStatus ^ 0x6666) & 0x7777); */
			if (fifoStatus & FS_ADC_NOT_EMPTY) {	/* 1 -> not empty */
				if (ai_read_n(dev, s, devpriv->transCount) < 0) {
					DPRINTK
					    ("rtd520: comedi read buffer overflow (N) with %ld to go!\n",
					     devpriv->aiCount);
					goto abortTransfer;
				}
				if (0 == devpriv->aiCount) {	/* counted down */
					DPRINTK
					    ("rtd520: Samples Done (N). fifo_status was 0x%x\n",
					     (fifoStatus ^ 0x6666) & 0x7777);
					goto transferDone;
				}
				comedi_event(dev, s);
			}
		} else {	/* wait for 1/2 FIFO (old) */
			DPRINTK
			    ("rtd520: Sample int.  Wait for 1/2. fifo_status 0x%x\n",
			     (fifoStatus ^ 0x6666) & 0x7777);
884
		}
885
886
	} else {
		DPRINTK("rtd520: unknown interrupt source!\n");
887
888
	}

889
890
	overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
	if (overrun) {
891
892
		DPRINTK
		    ("rtd520: Interrupt overrun with %ld to go! over_status=0x%x\n",
893
		     devpriv->aiCount, overrun);
894
895
		goto abortTransfer;
	}
896

897
	/* clear the interrupt */
898
899
	devpriv->intClearMask = status;
	writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
900
	readw(devpriv->las0 + LAS0_CLEAR);
901
	return IRQ_HANDLED;
902

903
abortTransfer:
904
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
905
906
907
	s->async->events |= COMEDI_CB_ERROR;
	devpriv->aiCount = 0;	/* stop and don't transfer any more */
	/* fall into transferDone */
908

909
transferDone:
910
	/* pacer stop source: SOFTWARE */
911
	writel(0, devpriv->las0 + LAS0_PACER_STOP);
912
	writel(0, devpriv->las0 + LAS0_PACER);	/* stop pacer */
913
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
914
915
	devpriv->intMask = 0;
	writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
916
917
#ifdef USE_DMA
	if (devpriv->flags & DMA0_ACTIVE) {
918
919
		writel(readl(devpriv->lcfg + LCFG_ITCSR) & ~ICS_DMA0_E,
			devpriv->lcfg + LCFG_ITCSR);
920
921
922
923
924
925
926
		abort_dma(dev, 0);
		devpriv->flags &= ~DMA0_ACTIVE;
		/* if Using DMA, then we should have read everything by now */
		if (devpriv->aiCount > 0) {
			DPRINTK("rtd520: Lost DMA data! %ld remain\n",
				devpriv->aiCount);
		}
927
	}
928
#endif /* USE_DMA */
929

930
	if (devpriv->aiCount > 0) {	/* there shouldn't be anything left */
931
		fifoStatus = readl(devpriv->las0 + LAS0_ADC);
932
933
934
		DPRINTK("rtd520: Finishing up. %ld remain, fifoStat=%x\n", devpriv->aiCount, (fifoStatus ^ 0x6666) & 0x7777);	/* should read all 0s */
		ai_read_dregs(dev, s);	/* read anything left in FIFO */
	}
935

936
937
	s->async->events |= COMEDI_CB_EOA;	/* signal end to comedi */
	comedi_event(dev, s);
938

939
	/* clear the interrupt */
940
	status = readw(devpriv->las0 + LAS0_IT);
941
942
	devpriv->intClearMask = status;
	writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
943
	readw(devpriv->las0 + LAS0_CLEAR);
944

945
	fifoStatus = readl(devpriv->las0 + LAS0_ADC);
946
	overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
947
948
	DPRINTK
	    ("rtd520: Acquisition complete. %ld ints, intStat=%x, overStat=%x\n",
949
	     devpriv->intCount, status, overrun);
950
951

	return IRQ_HANDLED;
952
953
}

954
#if 0
955
/*
956
  return the number of samples available
957
*/
958
static int rtd_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
959
{
960
961
962
	/* TODO: This needs to mask interrupts, read_dregs, and then re-enable */
	/* Not sure what to do if DMA is active */
	return s->async->buf_write_count - s->async->buf_read_count;
963
}
964
#endif
965

966
967
968
/*
  cmdtest tests a particular command to see if it is valid.
  Using the cmdtest ioctl, a user can create a valid cmd
969
  and then have it executed by the cmd ioctl (asynchronously).
970
971
972
973
974
975
976

  cmdtest returns 1,2,3,4 or 0, depending on which tests
  the command passes.
*/

static int rtd_ai_cmdtest(struct comedi_device *dev,
			  struct comedi_subdevice *s, struct comedi_cmd *cmd)
977
{
978
979
	int err = 0;
	int tmp;
980

981
	/* Step 1 : check if triggers are trivially valid */
982

983
984
985
986
987
988
	err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_begin_src,
					TRIG_TIMER | TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
989
990
991
992

	if (err)
		return 1;

993
	/* Step 2a : make sure trigger sources are unique */
994

995
996
997
998
999
	err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
	err |= cfc_check_trigger_is_unique(cmd->convert_src);
	err |= cfc_check_trigger_is_unique(cmd->stop_src);

	/* Step 2b : and mutually compatible */
1000

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