rtd520.c 45.6 KB
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/*
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 * comedi/drivers/rtd520.c
 * Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
 *
 * COMEDI - Linux Control and Measurement Device Interface
 * Copyright (C) 2001 David A. Schleef <ds@schleef.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */
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/*
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 * Driver: rtd520
 * Description: Real Time Devices PCI4520/DM7520
 * Devices: (Real Time Devices) DM7520HR-1 [DM7520]
 *	    (Real Time Devices) DM7520HR-8 [DM7520]
 *	    (Real Time Devices) PCI4520 [PCI4520]
 *	    (Real Time Devices) PCI4520-8 [PCI4520]
 * Author: Dan Christian
 * Status: Works. Only tested on DM7520-8. Not SMP safe.
 *
 * Configuration options: not applicable, uses PCI auto config
 */
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/*
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 * Created by Dan Christian, NASA Ames Research Center.
 *
 * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
 * Both have:
 *   8/16 12 bit ADC with FIFO and channel gain table
 *   8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
 *   8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
 *   2 12 bit DACs with FIFOs
 *   2 bits output
 *   2 bits input
 *   bus mastering DMA
 *   timers: ADC sample, pacer, burst, about, delay, DA1, DA2
 *   sample counter
 *   3 user timer/counters (8254)
 *   external interrupt
 *
 * The DM7520 has slightly fewer features (fewer gain steps).
 *
 * These boards can support external multiplexors and multi-board
 * synchronization, but this driver doesn't support that.
 *
 * Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
 * Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
 * Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
 * Call them and ask for the register level manual.
 * PCI chip: http://www.plxtech.com/products/io/pci9080
 *
 * Notes:
 * This board is memory mapped. There is some IO stuff, but it isn't needed.
 *
 * I use a pretty loose naming style within the driver (rtd_blah).
 * All externally visible names should be rtd520_blah.
 * I use camelCase for structures (and inside them).
 * I may also use upper CamelCase for function names (old habit).
 *
 * This board is somewhat related to the RTD PCI4400 board.
 *
 * I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
 * das1800, since they have the best documented code. Driver cb_pcidas64.c
 * uses the same DMA controller.
 *
 * As far as I can tell, the About interrupt doesn't work if Sample is
 * also enabled. It turns out that About really isn't needed, since
 * we always count down samples read.
 *
 * There was some timer/counter code, but it didn't follow the right API.
 */
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 * driver status:
 *
 * Analog-In supports instruction and command mode.
 *
 * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
 * (single channel, 64K read buffer). I get random system lockups when
 * using DMA with ALI-15xx based systems. I haven't been able to test
 * any other chipsets. The lockups happen soon after the start of an
 * acquistion, not in the middle of a long run.
 *
 * Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
 * (with a 256K read buffer).
 *
 * Digital-IO and Analog-Out only support instruction mode.
 */
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include "../comedidev.h"

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#include "comedi_fc.h"
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#include "plx9080.h"
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/*
 * Local Address Space 0 Offsets
 */
#define LAS0_USER_IO		0x0008	/* User I/O */
#define LAS0_ADC		0x0010	/* FIFO Status/Software A/D Start */
#define FS_DAC1_NOT_EMPTY	(1 << 0)	/* DAC1 FIFO not empty */
#define FS_DAC1_HEMPTY		(1 << 1)	/* DAC1 FIFO half empty */
#define FS_DAC1_NOT_FULL	(1 << 2)	/* DAC1 FIFO not full */
#define FS_DAC2_NOT_EMPTY	(1 << 4)	/* DAC2 FIFO not empty */
#define FS_DAC2_HEMPTY		(1 << 5)	/* DAC2 FIFO half empty */
#define FS_DAC2_NOT_FULL	(1 << 6)	/* DAC2 FIFO not full */
#define FS_ADC_NOT_EMPTY	(1 << 8)	/* ADC FIFO not empty */
#define FS_ADC_HEMPTY		(1 << 9)	/* ADC FIFO half empty */
#define FS_ADC_NOT_FULL		(1 << 10)	/* ADC FIFO not full */
#define FS_DIN_NOT_EMPTY	(1 << 12)	/* DIN FIFO not empty */
#define FS_DIN_HEMPTY		(1 << 13)	/* DIN FIFO half empty */
#define FS_DIN_NOT_FULL		(1 << 14)	/* DIN FIFO not full */
#define LAS0_DAC1		0x0014	/* Software D/A1 Update (w) */
#define LAS0_DAC2		0x0018	/* Software D/A2 Update (w) */
#define LAS0_DAC		0x0024	/* Software Simultaneous Update (w) */
#define LAS0_PACER		0x0028	/* Software Pacer Start/Stop */
#define LAS0_TIMER		0x002c	/* Timer Status/HDIN Software Trig. */
#define LAS0_IT			0x0030	/* Interrupt Status/Enable */
#define IRQM_ADC_FIFO_WRITE	(1 << 0)	/* ADC FIFO Write */
#define IRQM_CGT_RESET		(1 << 1)	/* Reset CGT */
#define IRQM_CGT_PAUSE		(1 << 3)	/* Pause CGT */
#define IRQM_ADC_ABOUT_CNT	(1 << 4)	/* About Counter out */
#define IRQM_ADC_DELAY_CNT	(1 << 5)	/* Delay Counter out */
#define IRQM_ADC_SAMPLE_CNT	(1 << 6)	/* ADC Sample Counter */
#define IRQM_DAC1_UCNT		(1 << 7)	/* DAC1 Update Counter */
#define IRQM_DAC2_UCNT		(1 << 8)	/* DAC2 Update Counter */
#define IRQM_UTC1		(1 << 9)	/* User TC1 out */
#define IRQM_UTC1_INV		(1 << 10)	/* User TC1 out, inverted */
#define IRQM_UTC2		(1 << 11)	/* User TC2 out */
#define IRQM_DIGITAL_IT		(1 << 12)	/* Digital Interrupt */
#define IRQM_EXTERNAL_IT	(1 << 13)	/* External Interrupt */
#define IRQM_ETRIG_RISING	(1 << 14)	/* Ext Trigger rising-edge */
#define IRQM_ETRIG_FALLING	(1 << 15)	/* Ext Trigger falling-edge */
#define LAS0_CLEAR		0x0034	/* Clear/Set Interrupt Clear Mask */
#define LAS0_OVERRUN		0x0038	/* Pending interrupts/Clear Overrun */
#define LAS0_PCLK		0x0040	/* Pacer Clock (24bit) */
#define LAS0_BCLK		0x0044	/* Burst Clock (10bit) */
#define LAS0_ADC_SCNT		0x0048	/* A/D Sample counter (10bit) */
#define LAS0_DAC1_UCNT		0x004c	/* D/A1 Update counter (10 bit) */
#define LAS0_DAC2_UCNT		0x0050	/* D/A2 Update counter (10 bit) */
#define LAS0_DCNT		0x0054	/* Delay counter (16 bit) */
#define LAS0_ACNT		0x0058	/* About counter (16 bit) */
#define LAS0_DAC_CLK		0x005c	/* DAC clock (16bit) */
#define LAS0_UTC0		0x0060	/* 8254 TC Counter 0 */
#define LAS0_UTC1		0x0064	/* 8254 TC Counter 1 */
#define LAS0_UTC2		0x0068	/* 8254 TC Counter 2 */
#define LAS0_UTC_CTRL		0x006c	/* 8254 TC Control */
#define LAS0_DIO0		0x0070	/* Digital I/O Port 0 */
#define LAS0_DIO1		0x0074	/* Digital I/O Port 1 */
#define LAS0_DIO0_CTRL		0x0078	/* Digital I/O Control */
#define LAS0_DIO_STATUS		0x007c	/* Digital I/O Status */
#define LAS0_BOARD_RESET	0x0100	/* Board reset */
#define LAS0_DMA0_SRC		0x0104	/* DMA 0 Sources select */
#define LAS0_DMA1_SRC		0x0108	/* DMA 1 Sources select */
#define LAS0_ADC_CONVERSION	0x010c	/* A/D Conversion Signal select */
#define LAS0_BURST_START	0x0110	/* Burst Clock Start Trigger select */
#define LAS0_PACER_START	0x0114	/* Pacer Clock Start Trigger select */
#define LAS0_PACER_STOP		0x0118	/* Pacer Clock Stop Trigger select */
#define LAS0_ACNT_STOP_ENABLE	0x011c	/* About Counter Stop Enable */
#define LAS0_PACER_REPEAT	0x0120	/* Pacer Start Trigger Mode select */
#define LAS0_DIN_START		0x0124	/* HiSpd DI Sampling Signal select */
#define LAS0_DIN_FIFO_CLEAR	0x0128	/* Digital Input FIFO Clear */
#define LAS0_ADC_FIFO_CLEAR	0x012c	/* A/D FIFO Clear */
#define LAS0_CGT_WRITE		0x0130	/* Channel Gain Table Write */
#define LAS0_CGL_WRITE		0x0134	/* Channel Gain Latch Write */
#define LAS0_CG_DATA		0x0138	/* Digital Table Write */
#define LAS0_CGT_ENABLE		0x013c	/* Channel Gain Table Enable */
#define LAS0_CG_ENABLE		0x0140	/* Digital Table Enable */
#define LAS0_CGT_PAUSE		0x0144	/* Table Pause Enable */
#define LAS0_CGT_RESET		0x0148	/* Reset Channel Gain Table */
#define LAS0_CGT_CLEAR		0x014c	/* Clear Channel Gain Table */
#define LAS0_DAC1_CTRL		0x0150	/* D/A1 output type/range */
#define LAS0_DAC1_SRC		0x0154	/* D/A1 update source */
#define LAS0_DAC1_CYCLE		0x0158	/* D/A1 cycle mode */
#define LAS0_DAC1_RESET		0x015c	/* D/A1 FIFO reset */
#define LAS0_DAC1_FIFO_CLEAR	0x0160	/* D/A1 FIFO clear */
#define LAS0_DAC2_CTRL		0x0164	/* D/A2 output type/range */
#define LAS0_DAC2_SRC		0x0168	/* D/A2 update source */
#define LAS0_DAC2_CYCLE		0x016c	/* D/A2 cycle mode */
#define LAS0_DAC2_RESET		0x0170	/* D/A2 FIFO reset */
#define LAS0_DAC2_FIFO_CLEAR	0x0174	/* D/A2 FIFO clear */
#define LAS0_ADC_SCNT_SRC	0x0178	/* A/D Sample Counter Source select */
#define LAS0_PACER_SELECT	0x0180	/* Pacer Clock select */
#define LAS0_SBUS0_SRC		0x0184	/* SyncBus 0 Source select */
#define LAS0_SBUS0_ENABLE	0x0188	/* SyncBus 0 enable */
#define LAS0_SBUS1_SRC		0x018c	/* SyncBus 1 Source select */
#define LAS0_SBUS1_ENABLE	0x0190	/* SyncBus 1 enable */
#define LAS0_SBUS2_SRC		0x0198	/* SyncBus 2 Source select */
#define LAS0_SBUS2_ENABLE	0x019c	/* SyncBus 2 enable */
#define LAS0_ETRG_POLARITY	0x01a4	/* Ext. Trigger polarity select */
#define LAS0_EINT_POLARITY	0x01a8	/* Ext. Interrupt polarity select */
#define LAS0_UTC0_CLOCK		0x01ac	/* UTC0 Clock select */
#define LAS0_UTC0_GATE		0x01b0	/* UTC0 Gate select */
#define LAS0_UTC1_CLOCK		0x01b4	/* UTC1 Clock select */
#define LAS0_UTC1_GATE		0x01b8	/* UTC1 Gate select */
#define LAS0_UTC2_CLOCK		0x01bc	/* UTC2 Clock select */
#define LAS0_UTC2_GATE		0x01c0	/* UTC2 Gate select */
#define LAS0_UOUT0_SELECT	0x01c4	/* User Output 0 source select */
#define LAS0_UOUT1_SELECT	0x01c8	/* User Output 1 source select */
#define LAS0_DMA0_RESET		0x01cc	/* DMA0 Request state machine reset */
#define LAS0_DMA1_RESET		0x01d0	/* DMA1 Request state machine reset */

/*
 * Local Address Space 1 Offsets
 */
#define LAS1_ADC_FIFO		0x0000	/* A/D FIFO (16bit) */
#define LAS1_HDIO_FIFO		0x0004	/* HiSpd DI FIFO (16bit) */
#define LAS1_DAC1_FIFO		0x0008	/* D/A1 FIFO (16bit) */
#define LAS1_DAC2_FIFO		0x000c	/* D/A2 FIFO (16bit) */

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/*======================================================================
  Driver specific stuff (tunable)
======================================================================*/

/* We really only need 2 buffers.  More than that means being much
   smarter about knowing which ones are full. */
#define DMA_CHAIN_COUNT 2	/* max DMA segments/buffers in a ring (min 2) */

/* Target period for periodic transfers.  This sets the user read latency. */
/* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
/* If this is too low, efficiency is poor */
#define TRANS_TARGET_PERIOD 10000000	/* 10 ms (in nanoseconds) */

/* Set a practical limit on how long a list to support (affects memory use) */
/* The board support a channel list up to the FIFO length (1K or 8K) */
#define RTD_MAX_CHANLIST	128	/* max channel list that we allow */

/* tuning for ai/ao instruction done polling */
#ifdef FAST_SPIN
#define WAIT_QUIETLY		/* as nothing, spin on done bit */
#define RTD_ADC_TIMEOUT	66000	/* 2 msec at 33mhz bus rate */
#define RTD_DAC_TIMEOUT	66000
#define RTD_DMA_TIMEOUT	33000	/* 1 msec */
#else
/* by delaying, power and electrical noise are reduced somewhat */
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#define WAIT_QUIETLY	udelay(1)
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#define RTD_ADC_TIMEOUT	2000	/* in usec */
#define RTD_DAC_TIMEOUT	2000	/* in usec */
#define RTD_DMA_TIMEOUT	1000	/* in usec */
#endif

/*======================================================================
  Board specific stuff
======================================================================*/

#define RTD_CLOCK_RATE	8000000	/* 8Mhz onboard clock */
#define RTD_CLOCK_BASE	125	/* clock period in ns */

/* Note: these speed are slower than the spec, but fit the counter resolution*/
#define RTD_MAX_SPEED	1625	/* when sampling, in nanoseconds */
/* max speed if we don't have to wait for settling */
#define RTD_MAX_SPEED_1	875	/* if single channel, in nanoseconds */

#define RTD_MIN_SPEED	2097151875	/* (24bit counter) in nanoseconds */
/* min speed when only 1 channel (no burst counter) */
#define RTD_MIN_SPEED_1	5000000	/* 200Hz, in nanoseconds */

/* Setup continuous ring of 1/2 FIFO transfers.  See RTD manual p91 */
#define DMA_MODE_BITS (\
		       PLX_LOCAL_BUS_16_WIDE_BITS \
		       | PLX_DMA_EN_READYIN_BIT \
		       | PLX_DMA_LOCAL_BURST_EN_BIT \
		       | PLX_EN_CHAIN_BIT \
		       | PLX_DMA_INTR_PCI_BIT \
		       | PLX_LOCAL_ADDR_CONST_BIT \
		       | PLX_DEMAND_MODE_BIT)

#define DMA_TRANSFER_BITS (\
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/* descriptors in PCI memory*/  PLX_DESC_IN_PCI_BIT \
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/* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
/* from board to PCI */		| PLX_XFER_LOCAL_TO_PCI)

/*======================================================================
  Comedi specific stuff
======================================================================*/

/*
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 * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
 */
static const struct comedi_lrange rtd_ai_7520_range = {
	18, {
		/* +-5V input range gain steps */
		BIP_RANGE(5.0),
		BIP_RANGE(5.0 / 2),
		BIP_RANGE(5.0 / 4),
		BIP_RANGE(5.0 / 8),
		BIP_RANGE(5.0 / 16),
		BIP_RANGE(5.0 / 32),
		/* +-10V input range gain steps */
		BIP_RANGE(10.0),
		BIP_RANGE(10.0 / 2),
		BIP_RANGE(10.0 / 4),
		BIP_RANGE(10.0 / 8),
		BIP_RANGE(10.0 / 16),
		BIP_RANGE(10.0 / 32),
		/* +10V input range gain steps */
		UNI_RANGE(10.0),
		UNI_RANGE(10.0 / 2),
		UNI_RANGE(10.0 / 4),
		UNI_RANGE(10.0 / 8),
		UNI_RANGE(10.0 / 16),
		UNI_RANGE(10.0 / 32),
	}
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};

/* PCI4520 has two more gains (6 more entries) */
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static const struct comedi_lrange rtd_ai_4520_range = {
	24, {
		/* +-5V input range gain steps */
		BIP_RANGE(5.0),
		BIP_RANGE(5.0 / 2),
		BIP_RANGE(5.0 / 4),
		BIP_RANGE(5.0 / 8),
		BIP_RANGE(5.0 / 16),
		BIP_RANGE(5.0 / 32),
		BIP_RANGE(5.0 / 64),
		BIP_RANGE(5.0 / 128),
		/* +-10V input range gain steps */
		BIP_RANGE(10.0),
		BIP_RANGE(10.0 / 2),
		BIP_RANGE(10.0 / 4),
		BIP_RANGE(10.0 / 8),
		BIP_RANGE(10.0 / 16),
		BIP_RANGE(10.0 / 32),
		BIP_RANGE(10.0 / 64),
		BIP_RANGE(10.0 / 128),
		/* +10V input range gain steps */
		UNI_RANGE(10.0),
		UNI_RANGE(10.0 / 2),
		UNI_RANGE(10.0 / 4),
		UNI_RANGE(10.0 / 8),
		UNI_RANGE(10.0 / 16),
		UNI_RANGE(10.0 / 32),
		UNI_RANGE(10.0 / 64),
		UNI_RANGE(10.0 / 128),
	}
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};

/* Table order matches range values */
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static const struct comedi_lrange rtd_ao_range = {
	4, {
		UNI_RANGE(5),
		UNI_RANGE(10),
		BIP_RANGE(5),
		BIP_RANGE(10),
	}
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};

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enum rtd_boardid {
	BOARD_DM7520,
	BOARD_PCI4520,
};

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struct rtdBoard {
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	const char *name;
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	int range10Start;	/* start of +-10V range */
	int rangeUniStart;	/* start of +10V range */
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	const struct comedi_lrange *ai_range;
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};
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static const struct rtdBoard rtd520Boards[] = {
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	[BOARD_DM7520] = {
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		.name		= "DM7520",
		.range10Start	= 6,
		.rangeUniStart	= 12,
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		.ai_range	= &rtd_ai_7520_range,
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	},
	[BOARD_PCI4520] = {
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		.name		= "PCI4520",
		.range10Start	= 8,
		.rangeUniStart	= 16,
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		.ai_range	= &rtd_ai_4520_range,
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	},
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};

/*
   This structure is for data unique to this hardware driver.
   This is also unique for each board in the system.
*/
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struct rtdPrivate {
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	/* memory mapped board structures */
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	void __iomem *las0;
	void __iomem *las1;
	void __iomem *lcfg;
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	long aiCount;		/* total transfer size (samples) */
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	int transCount;		/* # to transfer data. 0->1/2FIFO */
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	int flags;		/* flag event modes */

	/* channel list info */
	/* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
	unsigned char chanBipolar[RTD_MAX_CHANLIST / 8];	/* bit array */

	/* read back data */
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	unsigned int aoValue[2];	/* Used for AO read back */
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	/* timer gate (when enabled) */
	u8 utcGate[4];		/* 1 extra allows simple range check */

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	/* shadow registers affect other registers, but can't be read back */
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	/* The macros below update these on writes */
	u16 intMask;		/* interrupt mask */
	u16 intClearMask;	/* interrupt clear mask */
	u8 utcCtrl[4];		/* crtl mode for 3 utc + read back */
	unsigned fifoLen;
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};
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/* bit defines for "flags" */
#define SEND_EOS	0x01	/* send End Of Scan events */
#define DMA0_ACTIVE	0x02	/* DMA0 is active */
#define DMA1_ACTIVE	0x04	/* DMA1 is active */

/* Macros for accessing channel list bit array */
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#define CHAN_ARRAY_TEST(array, index) \
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	(((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
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#define CHAN_ARRAY_SET(array, index) \
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	(((array)[(index)/8] |= 1 << ((index) & 0x7)))
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#define CHAN_ARRAY_CLEAR(array, index) \
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	(((array)[(index)/8] &= ~(1 << ((index) & 0x7))))

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/*
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441
  Given a desired period and the clock period (both in ns),
  return the proper counter value (divider-1).
  Sets the original period to be the true value.
  Note: you have to check if the value is larger than the counter range!
*/
442
static int rtd_ns_to_timer_base(unsigned int *nanosec,
443
				int round_mode, int base)
444
{
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
	int divider;

	switch (round_mode) {
	case TRIG_ROUND_NEAREST:
	default:
		divider = (*nanosec + base / 2) / base;
		break;
	case TRIG_ROUND_DOWN:
		divider = (*nanosec) / base;
		break;
	case TRIG_ROUND_UP:
		divider = (*nanosec + base - 1) / base;
		break;
	}
	if (divider < 2)
		divider = 2;	/* min is divide by 2 */

	/* Note: we don't check for max, because different timers
	   have different ranges */

	*nanosec = base * divider;
	return divider - 1;	/* countdown is divisor+1 */
}
468
469

/*
470
471
472
473
474
475
476
477
  Given a desired period (in ns),
  return the proper counter value (divider-1) for the internal clock.
  Sets the original period to be the true value.
*/
static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
{
	return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
}
478

479
480
481
482
483
484
/*
  Convert a single comedi channel-gain entry to a RTD520 table entry
*/
static unsigned short rtdConvertChanGain(struct comedi_device *dev,
					 unsigned int comediChan, int chanIndex)
{				/* index in channel list */
485
	const struct rtdBoard *thisboard = comedi_board(dev);
486
	struct rtdPrivate *devpriv = dev->private;
487
488
	unsigned int chan, range, aref;
	unsigned short r = 0;
489

490
491
492
	chan = CR_CHAN(comediChan);
	range = CR_RANGE(comediChan);
	aref = CR_AREF(comediChan);
493

494
	r |= chan & 0xf;
495

496
	/* Note: we also setup the channel list bipolar flag array */
497
498
499
500
	if (range < thisboard->range10Start) {
		/* +-5 range */
		r |= 0x000;
		r |= (range & 0x7) << 4;
501
		CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
502
503
504
	} else if (range < thisboard->rangeUniStart) {
		/* +-10 range */
		r |= 0x100;
505
506
		r |= ((range - thisboard->range10Start) & 0x7) << 4;
		CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
507
508
509
	} else {
		/* +10 range */
		r |= 0x200;
510
511
512
		r |= ((range - thisboard->rangeUniStart) & 0x7) << 4;
		CHAN_ARRAY_CLEAR(devpriv->chanBipolar, chanIndex);
	}
513

514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
	switch (aref) {
	case AREF_GROUND:	/* on-board ground */
		break;

	case AREF_COMMON:
		r |= 0x80;	/* ref external analog common */
		break;

	case AREF_DIFF:
		r |= 0x400;	/* differential inputs */
		break;

	case AREF_OTHER:	/* ??? */
		break;
	}
	/*printk ("chan=%d r=%d a=%d -> 0x%x\n",
	   chan, range, aref, r); */
	return r;
}

/*
  Setup the channel-gain table from a comedi list
*/
static void rtd_load_channelgain_list(struct comedi_device *dev,
				      unsigned int n_chan, unsigned int *list)
{
540
541
	struct rtdPrivate *devpriv = dev->private;

542
543
	if (n_chan > 1) {	/* setup channel gain table */
		int ii;
544
545

		writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
546
		writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
547
		for (ii = 0; ii < n_chan; ii++) {
548
549
			writel(rtdConvertChanGain(dev, list[ii], ii),
				devpriv->las0 + LAS0_CGT_WRITE);
550
		}
551
	} else {		/* just use the channel gain latch */
552
		writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
553
554
		writel(rtdConvertChanGain(dev, list[0], 0),
			devpriv->las0 + LAS0_CGL_WRITE);
555
	}
556
557
558
559
560
561
}

/* determine fifo size by doing adc conversions until the fifo half
empty status flag clears */
static int rtd520_probe_fifo_depth(struct comedi_device *dev)
{
562
	struct rtdPrivate *devpriv = dev->private;
563
564
565
566
567
	unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
	unsigned i;
	static const unsigned limit = 0x2000;
	unsigned fifo_size = 0;

568
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
569
	rtd_load_channelgain_list(dev, 1, &chanspec);
570
	/* ADC conversion trigger source: SOFTWARE */
571
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
572
573
574
575
	/* convert  samples */
	for (i = 0; i < limit; ++i) {
		unsigned fifo_status;
		/* trigger conversion */
576
		writew(0, devpriv->las0 + LAS0_ADC);
577
		udelay(1);
578
		fifo_status = readl(devpriv->las0 + LAS0_ADC);
579
580
581
		if ((fifo_status & FS_ADC_HEMPTY) == 0) {
			fifo_size = 2 * i;
			break;
582
		}
583
584
	}
	if (i == limit) {
585
		dev_info(dev->class_dev, "failed to probe fifo size.\n");
586
587
		return -EIO;
	}
588
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
589
	if (fifo_size != 0x400 && fifo_size != 0x2000) {
590
591
592
		dev_info(dev->class_dev,
			 "unexpected fifo size of %i, expected 1024 or 8192.\n",
			 fifo_size);
593
		return -EIO;
594
	}
595
596
	return fifo_size;
}
597

598
599
600
601
/*
  "instructions" read/write data in "one-shot" or "software-triggered"
  mode (simplest case).
  This doesn't use interrupts.
602

603
604
605
606
607
608
609
  Note, we don't do any settling delays.  Use a instruction list to
  select, delay, then read.
 */
static int rtd_ai_rinsn(struct comedi_device *dev,
			struct comedi_subdevice *s, struct comedi_insn *insn,
			unsigned int *data)
{
610
	struct rtdPrivate *devpriv = dev->private;
611
612
	int n, ii;
	int stat;
613

614
	/* clear any old fifo data */
615
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
616

617
618
	/* write channel to multiplexer and clear channel gain table */
	rtd_load_channelgain_list(dev, 1, &insn->chanspec);
619

620
	/* ADC conversion trigger source: SOFTWARE */
621
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
622

623
624
625
626
	/* convert n samples */
	for (n = 0; n < insn->n; n++) {
		s16 d;
		/* trigger conversion */
627
		writew(0, devpriv->las0 + LAS0_ADC);
628
629

		for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
630
			stat = readl(devpriv->las0 + LAS0_ADC);
631
632
633
634
			if (stat & FS_ADC_NOT_EMPTY)	/* 1 -> not empty */
				break;
			WAIT_QUIETLY;
		}
635
		if (ii >= RTD_ADC_TIMEOUT)
636
637
638
			return -ETIMEDOUT;

		/* read data */
639
		d = readw(devpriv->las1 + LAS1_ADC_FIFO);
640
641
642
643
644
645
646
		/*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
		d = d >> 3;	/* low 3 bits are marker lines */
		if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
			/* convert to comedi unsigned data */
			data[n] = d + 2048;
		else
			data[n] = d;
647
648
	}

649
650
651
	/* return the number of samples read/written */
	return n;
}
652

653
654
655
/*
  Get what we know is there.... Fast!
  This uses 1/2 the bus cycles of read_dregs (below).
656

657
658
659
660
661
  The manual claims that we can do a lword read, but it doesn't work here.
*/
static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
		     int count)
{
662
	struct rtdPrivate *devpriv = dev->private;
663
	int ii;
664

665
666
667
	for (ii = 0; ii < count; ii++) {
		short sample;
		s16 d;
668

669
		if (0 == devpriv->aiCount) {	/* done */
670
			d = readw(devpriv->las1 + LAS1_ADC_FIFO);
671
672
			continue;
		}
673

674
		d = readw(devpriv->las1 + LAS1_ADC_FIFO);
675
676
677
678
679
680
		d = d >> 3;	/* low 3 bits are marker lines */
		if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
			/* convert to comedi unsigned data */
			sample = d + 2048;
		} else
			sample = d;
681

682
683
		if (!comedi_buf_put(s->async, sample))
			return -1;
684

685
686
687
688
689
		if (devpriv->aiCount > 0)	/* < 0, means read forever */
			devpriv->aiCount--;
	}
	return 0;
}
690

691
692
693
694
695
/*
  unknown amout of data is waiting in fifo.
*/
static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
{
696
697
	struct rtdPrivate *devpriv = dev->private;

698
	while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
699
		short sample;
700
		s16 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
701

702
703
704
		if (0 == devpriv->aiCount) {	/* done */
			continue;	/* read rest */
		}
705

706
707
708
709
710
711
		d = d >> 3;	/* low 3 bits are marker lines */
		if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
			/* convert to comedi unsigned data */
			sample = d + 2048;
		} else
			sample = d;
712

713
714
		if (!comedi_buf_put(s->async, sample))
			return -1;
715

716
717
718
719
720
		if (devpriv->aiCount > 0)	/* < 0, means read forever */
			devpriv->aiCount--;
	}
	return 0;
}
721

722
723
724
725
726
727
728
729
730
/*
  Handle all rtd520 interrupts.
  Runs atomically and is never re-entered.
  This is a "slow handler";  other interrupts may be active.
  The data conversion may someday happen in a "bottom half".
*/
static irqreturn_t rtd_interrupt(int irq,	/* interrupt number (ignored) */
				 void *d)
{				/* our data *//* cpu context (ignored) */
731
	struct comedi_device *dev = d;
732
	struct comedi_subdevice *s = &dev->subdevices[0];
733
	struct rtdPrivate *devpriv = dev->private;
734
	u32 overrun;
735
736
	u16 status;
	u16 fifoStatus;
737

738
739
	if (!dev->attached)
		return IRQ_NONE;
740

741
	fifoStatus = readl(devpriv->las0 + LAS0_ADC);
742
	/* check for FIFO full, this automatically halts the ADC! */
743
	if (!(fifoStatus & FS_ADC_NOT_FULL))	/* 0 -> full */
744
745
		goto abortTransfer;

746
	status = readw(devpriv->las0 + LAS0_IT);
747
748
749
750
751
	/* if interrupt was not caused by our board, or handled above */
	if (0 == status)
		return IRQ_HANDLED;

	if (status & IRQM_ADC_ABOUT_CNT) {	/* sample count -> read FIFO */
752
753
754
755
756
757
758
759
		/*
		 * since the priority interrupt controller may have queued
		 * a sample counter interrupt, even though we have already
		 * finished, we must handle the possibility that there is
		 * no data here
		 */
		if (!(fifoStatus & FS_ADC_HEMPTY)) {
			/* FIFO half full */
760
			if (ai_read_n(dev, s, devpriv->fifoLen / 2) < 0)
761
				goto abortTransfer;
762
763

			if (0 == devpriv->aiCount)
764
				goto transferDone;
765

766
			comedi_event(dev, s);
767
768
769
		} else if (devpriv->transCount > 0) {
			if (fifoStatus & FS_ADC_NOT_EMPTY) {
				/* FIFO not empty */
770
				if (ai_read_n(dev, s, devpriv->transCount) < 0)
771
					goto abortTransfer;
772
773

				if (0 == devpriv->aiCount)
774
					goto transferDone;
775

776
777
				comedi_event(dev, s);
			}
778
779
780
		}
	}

781
	overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
782
	if (overrun)
783
		goto abortTransfer;
784

785
	/* clear the interrupt */
786
787
	devpriv->intClearMask = status;
	writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
788
	readw(devpriv->las0 + LAS0_CLEAR);
789
	return IRQ_HANDLED;
790

791
abortTransfer:
792
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
793
794
795
	s->async->events |= COMEDI_CB_ERROR;
	devpriv->aiCount = 0;	/* stop and don't transfer any more */
	/* fall into transferDone */
796

797
transferDone:
798
	/* pacer stop source: SOFTWARE */
799
	writel(0, devpriv->las0 + LAS0_PACER_STOP);
800
	writel(0, devpriv->las0 + LAS0_PACER);	/* stop pacer */
801
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
802
803
	devpriv->intMask = 0;
	writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
804

805
	if (devpriv->aiCount > 0) {	/* there shouldn't be anything left */
806
		fifoStatus = readl(devpriv->las0 + LAS0_ADC);
807
808
		ai_read_dregs(dev, s);	/* read anything left in FIFO */
	}
809

810
811
	s->async->events |= COMEDI_CB_EOA;	/* signal end to comedi */
	comedi_event(dev, s);
812

813
	/* clear the interrupt */
814
	status = readw(devpriv->las0 + LAS0_IT);
815
816
	devpriv->intClearMask = status;
	writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
817
	readw(devpriv->las0 + LAS0_CLEAR);
818

819
	fifoStatus = readl(devpriv->las0 + LAS0_ADC);
820
	overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
821
822

	return IRQ_HANDLED;
823
824
}

825
826
827
/*
  cmdtest tests a particular command to see if it is valid.
  Using the cmdtest ioctl, a user can create a valid cmd
828
  and then have it executed by the cmd ioctl (asynchronously).
829
830
831
832
833
834
835

  cmdtest returns 1,2,3,4 or 0, depending on which tests
  the command passes.
*/

static int rtd_ai_cmdtest(struct comedi_device *dev,
			  struct comedi_subdevice *s, struct comedi_cmd *cmd)
836
{
837
838
	int err = 0;
	int tmp;
839

840
	/* Step 1 : check if triggers are trivially valid */
841

842
843
844
845
846
847
	err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_begin_src,
					TRIG_TIMER | TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
848
849
850
851

	if (err)
		return 1;

852
	/* Step 2a : make sure trigger sources are unique */
853

854
855
856
857
858
	err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
	err |= cfc_check_trigger_is_unique(cmd->convert_src);
	err |= cfc_check_trigger_is_unique(cmd->stop_src);

	/* Step 2b : and mutually compatible */
859

860
861
	if (err)
		return 2;
862

863
	/* Step 3: check if arguments are trivially valid */
864

865
	err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
866

867
868
869
	if (cmd->scan_begin_src == TRIG_TIMER) {
		/* Note: these are time periods, not actual rates */
		if (1 == cmd->chanlist_len) {	/* no scanning */
870
871
			if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
						      RTD_MAX_SPEED_1)) {
872
873
				rtd_ns_to_timer(&cmd->scan_begin_arg,
						TRIG_ROUND_UP);
874
				err |= -EINVAL;
875
			}
876
877
			if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
						      RTD_MIN_SPEED_1)) {
878
879
				rtd_ns_to_timer(&cmd->scan_begin_arg,
						TRIG_ROUND_DOWN);
880
				err |= -EINVAL;
881
882
			}
		} else {
883
884
			if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
						      RTD_MAX_SPEED)) {
885
886
				rtd_ns_to_timer(&cmd->scan_begin_arg,
						TRIG_ROUND_UP);
887
				err |= -EINVAL;
888
			}
889
890
			if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
						      RTD_MIN_SPEED)) {
891
892
				rtd_ns_to_timer(&cmd->scan_begin_arg,
						TRIG_ROUND_DOWN);
893
				err |= -EINVAL;
894
			}
895
		}
896
897
898
899
	} else {
		/* external trigger */
		/* should be level/edge, hi/lo specification here */
		/* should specify multiple external triggers */
900
		err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
901
	}
902

903
904
	if (cmd->convert_src == TRIG_TIMER) {
		if (1 == cmd->chanlist_len) {	/* no scanning */
905
906
			if (cfc_check_trigger_arg_min(&cmd->convert_arg,
						      RTD_MAX_SPEED_1)) {
907
908
				rtd_ns_to_timer(&cmd->convert_arg,
						TRIG_ROUND_UP);
909
				err |= -EINVAL;
910
			}
911
912
			if (cfc_check_trigger_arg_max(&cmd->convert_arg,
						      RTD_MIN_SPEED_1)) {
913
914
				rtd_ns_to_timer(&cmd->convert_arg,
						TRIG_ROUND_DOWN);
915
				err |= -EINVAL;
916
917
			}
		} else {
918
919
			if (cfc_check_trigger_arg_min(&cmd->convert_arg,
						      RTD_MAX_SPEED)) {
920
921
				rtd_ns_to_timer(&cmd->convert_arg,
						TRIG_ROUND_UP);
922
				err |= -EINVAL;
923
			}
924
925
			if (cfc_check_trigger_arg_max(&cmd->convert_arg,
						      RTD_MIN_SPEED)) {
926
927
				rtd_ns_to_timer(&cmd->convert_arg,
						TRIG_ROUND_DOWN);
928
				err |= -EINVAL;
929
930
931
932
933
			}
		}
	} else {
		/* external trigger */
		/* see above */
934
		err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9);
935
936
937
938
939
940
	}

	if (cmd->stop_src == TRIG_COUNT) {
		/* TODO check for rounding error due to counter wrap */
	} else {
		/* TRIG_NONE */
941
		err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
942
	}
943

944
945
	if (err)
		return 3;
946

947
948
949
950
951
952

	/* step 4: fix up any arguments */

	if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
		cmd->chanlist_len = RTD_MAX_CHANLIST;
		err++;
953
	}
954
955
956
957
958
959
	if (cmd->scan_begin_src == TRIG_TIMER) {
		tmp = cmd->scan_begin_arg;
		rtd_ns_to_timer(&cmd->scan_begin_arg,
				cmd->flags & TRIG_ROUND_MASK);
		if (tmp != cmd->scan_begin_arg)
			err++;
960

961
962
963
964
965
966
967
	}
	if (cmd->convert_src == TRIG_TIMER) {
		tmp = cmd->convert_arg;
		rtd_ns_to_timer(&cmd->convert_arg,
				cmd->flags & TRIG_ROUND_MASK);
		if (tmp != cmd->convert_arg)
			err++;
968

969
970
971
972
973
974
		if (cmd->scan_begin_src == TRIG_TIMER
		    && (cmd->scan_begin_arg
			< (cmd->convert_arg * cmd->scan_end_arg))) {
			cmd->scan_begin_arg =
			    cmd->convert_arg * cmd->scan_end_arg;
			err++;
975
		}
976
	}
977

978
979
	if (err)
		return 4;
980
981
982
983
984

	return 0;
}

/*
985
986
987
988
  Execute a analog in command with many possible triggering options.
  The data get stored in the async structure of the subdevice.
  This is usually done by an interrupt handler.
  Userland gets to the data using read calls.
989
*/
990
991
static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
{
992
	struct rtdPrivate *devpriv = dev->private;
993
994
	struct comedi_cmd *cmd = &s->async->cmd;
	int timer;
995

996
	/* stop anything currently running */
997
	/* pacer stop source: SOFTWARE */
998
	writel(0, devpriv->las0 + LAS0_PACER_STOP);
999
	writel(0, devpriv->las0 + LAS0_PACER);	/* stop pacer */
1000
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);