rtd520.c 43.1 KB
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/*
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 * comedi/drivers/rtd520.c
 * Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
 *
 * COMEDI - Linux Control and Measurement Device Interface
 * Copyright (C) 2001 David A. Schleef <ds@schleef.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */
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/*
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 * Driver: rtd520
 * Description: Real Time Devices PCI4520/DM7520
 * Devices: (Real Time Devices) DM7520HR-1 [DM7520]
 *	    (Real Time Devices) DM7520HR-8 [DM7520]
 *	    (Real Time Devices) PCI4520 [PCI4520]
 *	    (Real Time Devices) PCI4520-8 [PCI4520]
 * Author: Dan Christian
 * Status: Works. Only tested on DM7520-8. Not SMP safe.
 *
 * Configuration options: not applicable, uses PCI auto config
 */
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/*
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 * Created by Dan Christian, NASA Ames Research Center.
 *
 * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
 * Both have:
 *   8/16 12 bit ADC with FIFO and channel gain table
 *   8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
 *   8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
 *   2 12 bit DACs with FIFOs
 *   2 bits output
 *   2 bits input
 *   bus mastering DMA
 *   timers: ADC sample, pacer, burst, about, delay, DA1, DA2
 *   sample counter
 *   3 user timer/counters (8254)
 *   external interrupt
 *
 * The DM7520 has slightly fewer features (fewer gain steps).
 *
 * These boards can support external multiplexors and multi-board
 * synchronization, but this driver doesn't support that.
 *
 * Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
 * Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
 * Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
 * Call them and ask for the register level manual.
 * PCI chip: http://www.plxtech.com/products/io/pci9080
 *
 * Notes:
 * This board is memory mapped. There is some IO stuff, but it isn't needed.
 *
 * I use a pretty loose naming style within the driver (rtd_blah).
 * All externally visible names should be rtd520_blah.
 * I use camelCase for structures (and inside them).
 * I may also use upper CamelCase for function names (old habit).
 *
 * This board is somewhat related to the RTD PCI4400 board.
 *
 * I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
 * das1800, since they have the best documented code. Driver cb_pcidas64.c
 * uses the same DMA controller.
 *
 * As far as I can tell, the About interrupt doesn't work if Sample is
 * also enabled. It turns out that About really isn't needed, since
 * we always count down samples read.
 *
 * There was some timer/counter code, but it didn't follow the right API.
 */
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/*
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 * driver status:
 *
 * Analog-In supports instruction and command mode.
 *
 * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
 * (single channel, 64K read buffer). I get random system lockups when
 * using DMA with ALI-15xx based systems. I haven't been able to test
 * any other chipsets. The lockups happen soon after the start of an
 * acquistion, not in the middle of a long run.
 *
 * Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
 * (with a 256K read buffer).
 *
 * Digital-IO and Analog-Out only support instruction mode.
 */
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include "../comedidev.h"

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#include "comedi_fc.h"
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#include "plx9080.h"
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/*
 * Local Address Space 0 Offsets
 */
#define LAS0_USER_IO		0x0008	/* User I/O */
#define LAS0_ADC		0x0010	/* FIFO Status/Software A/D Start */
#define FS_DAC1_NOT_EMPTY	(1 << 0)	/* DAC1 FIFO not empty */
#define FS_DAC1_HEMPTY		(1 << 1)	/* DAC1 FIFO half empty */
#define FS_DAC1_NOT_FULL	(1 << 2)	/* DAC1 FIFO not full */
#define FS_DAC2_NOT_EMPTY	(1 << 4)	/* DAC2 FIFO not empty */
#define FS_DAC2_HEMPTY		(1 << 5)	/* DAC2 FIFO half empty */
#define FS_DAC2_NOT_FULL	(1 << 6)	/* DAC2 FIFO not full */
#define FS_ADC_NOT_EMPTY	(1 << 8)	/* ADC FIFO not empty */
#define FS_ADC_HEMPTY		(1 << 9)	/* ADC FIFO half empty */
#define FS_ADC_NOT_FULL		(1 << 10)	/* ADC FIFO not full */
#define FS_DIN_NOT_EMPTY	(1 << 12)	/* DIN FIFO not empty */
#define FS_DIN_HEMPTY		(1 << 13)	/* DIN FIFO half empty */
#define FS_DIN_NOT_FULL		(1 << 14)	/* DIN FIFO not full */
#define LAS0_DAC1		0x0014	/* Software D/A1 Update (w) */
#define LAS0_DAC2		0x0018	/* Software D/A2 Update (w) */
#define LAS0_DAC		0x0024	/* Software Simultaneous Update (w) */
#define LAS0_PACER		0x0028	/* Software Pacer Start/Stop */
#define LAS0_TIMER		0x002c	/* Timer Status/HDIN Software Trig. */
#define LAS0_IT			0x0030	/* Interrupt Status/Enable */
#define IRQM_ADC_FIFO_WRITE	(1 << 0)	/* ADC FIFO Write */
#define IRQM_CGT_RESET		(1 << 1)	/* Reset CGT */
#define IRQM_CGT_PAUSE		(1 << 3)	/* Pause CGT */
#define IRQM_ADC_ABOUT_CNT	(1 << 4)	/* About Counter out */
#define IRQM_ADC_DELAY_CNT	(1 << 5)	/* Delay Counter out */
#define IRQM_ADC_SAMPLE_CNT	(1 << 6)	/* ADC Sample Counter */
#define IRQM_DAC1_UCNT		(1 << 7)	/* DAC1 Update Counter */
#define IRQM_DAC2_UCNT		(1 << 8)	/* DAC2 Update Counter */
#define IRQM_UTC1		(1 << 9)	/* User TC1 out */
#define IRQM_UTC1_INV		(1 << 10)	/* User TC1 out, inverted */
#define IRQM_UTC2		(1 << 11)	/* User TC2 out */
#define IRQM_DIGITAL_IT		(1 << 12)	/* Digital Interrupt */
#define IRQM_EXTERNAL_IT	(1 << 13)	/* External Interrupt */
#define IRQM_ETRIG_RISING	(1 << 14)	/* Ext Trigger rising-edge */
#define IRQM_ETRIG_FALLING	(1 << 15)	/* Ext Trigger falling-edge */
#define LAS0_CLEAR		0x0034	/* Clear/Set Interrupt Clear Mask */
#define LAS0_OVERRUN		0x0038	/* Pending interrupts/Clear Overrun */
#define LAS0_PCLK		0x0040	/* Pacer Clock (24bit) */
#define LAS0_BCLK		0x0044	/* Burst Clock (10bit) */
#define LAS0_ADC_SCNT		0x0048	/* A/D Sample counter (10bit) */
#define LAS0_DAC1_UCNT		0x004c	/* D/A1 Update counter (10 bit) */
#define LAS0_DAC2_UCNT		0x0050	/* D/A2 Update counter (10 bit) */
#define LAS0_DCNT		0x0054	/* Delay counter (16 bit) */
#define LAS0_ACNT		0x0058	/* About counter (16 bit) */
#define LAS0_DAC_CLK		0x005c	/* DAC clock (16bit) */
#define LAS0_UTC0		0x0060	/* 8254 TC Counter 0 */
#define LAS0_UTC1		0x0064	/* 8254 TC Counter 1 */
#define LAS0_UTC2		0x0068	/* 8254 TC Counter 2 */
#define LAS0_UTC_CTRL		0x006c	/* 8254 TC Control */
#define LAS0_DIO0		0x0070	/* Digital I/O Port 0 */
#define LAS0_DIO1		0x0074	/* Digital I/O Port 1 */
#define LAS0_DIO0_CTRL		0x0078	/* Digital I/O Control */
#define LAS0_DIO_STATUS		0x007c	/* Digital I/O Status */
#define LAS0_BOARD_RESET	0x0100	/* Board reset */
#define LAS0_DMA0_SRC		0x0104	/* DMA 0 Sources select */
#define LAS0_DMA1_SRC		0x0108	/* DMA 1 Sources select */
#define LAS0_ADC_CONVERSION	0x010c	/* A/D Conversion Signal select */
#define LAS0_BURST_START	0x0110	/* Burst Clock Start Trigger select */
#define LAS0_PACER_START	0x0114	/* Pacer Clock Start Trigger select */
#define LAS0_PACER_STOP		0x0118	/* Pacer Clock Stop Trigger select */
#define LAS0_ACNT_STOP_ENABLE	0x011c	/* About Counter Stop Enable */
#define LAS0_PACER_REPEAT	0x0120	/* Pacer Start Trigger Mode select */
#define LAS0_DIN_START		0x0124	/* HiSpd DI Sampling Signal select */
#define LAS0_DIN_FIFO_CLEAR	0x0128	/* Digital Input FIFO Clear */
#define LAS0_ADC_FIFO_CLEAR	0x012c	/* A/D FIFO Clear */
#define LAS0_CGT_WRITE		0x0130	/* Channel Gain Table Write */
#define LAS0_CGL_WRITE		0x0134	/* Channel Gain Latch Write */
#define LAS0_CG_DATA		0x0138	/* Digital Table Write */
#define LAS0_CGT_ENABLE		0x013c	/* Channel Gain Table Enable */
#define LAS0_CG_ENABLE		0x0140	/* Digital Table Enable */
#define LAS0_CGT_PAUSE		0x0144	/* Table Pause Enable */
#define LAS0_CGT_RESET		0x0148	/* Reset Channel Gain Table */
#define LAS0_CGT_CLEAR		0x014c	/* Clear Channel Gain Table */
#define LAS0_DAC1_CTRL		0x0150	/* D/A1 output type/range */
#define LAS0_DAC1_SRC		0x0154	/* D/A1 update source */
#define LAS0_DAC1_CYCLE		0x0158	/* D/A1 cycle mode */
#define LAS0_DAC1_RESET		0x015c	/* D/A1 FIFO reset */
#define LAS0_DAC1_FIFO_CLEAR	0x0160	/* D/A1 FIFO clear */
#define LAS0_DAC2_CTRL		0x0164	/* D/A2 output type/range */
#define LAS0_DAC2_SRC		0x0168	/* D/A2 update source */
#define LAS0_DAC2_CYCLE		0x016c	/* D/A2 cycle mode */
#define LAS0_DAC2_RESET		0x0170	/* D/A2 FIFO reset */
#define LAS0_DAC2_FIFO_CLEAR	0x0174	/* D/A2 FIFO clear */
#define LAS0_ADC_SCNT_SRC	0x0178	/* A/D Sample Counter Source select */
#define LAS0_PACER_SELECT	0x0180	/* Pacer Clock select */
#define LAS0_SBUS0_SRC		0x0184	/* SyncBus 0 Source select */
#define LAS0_SBUS0_ENABLE	0x0188	/* SyncBus 0 enable */
#define LAS0_SBUS1_SRC		0x018c	/* SyncBus 1 Source select */
#define LAS0_SBUS1_ENABLE	0x0190	/* SyncBus 1 enable */
#define LAS0_SBUS2_SRC		0x0198	/* SyncBus 2 Source select */
#define LAS0_SBUS2_ENABLE	0x019c	/* SyncBus 2 enable */
#define LAS0_ETRG_POLARITY	0x01a4	/* Ext. Trigger polarity select */
#define LAS0_EINT_POLARITY	0x01a8	/* Ext. Interrupt polarity select */
#define LAS0_UTC0_CLOCK		0x01ac	/* UTC0 Clock select */
#define LAS0_UTC0_GATE		0x01b0	/* UTC0 Gate select */
#define LAS0_UTC1_CLOCK		0x01b4	/* UTC1 Clock select */
#define LAS0_UTC1_GATE		0x01b8	/* UTC1 Gate select */
#define LAS0_UTC2_CLOCK		0x01bc	/* UTC2 Clock select */
#define LAS0_UTC2_GATE		0x01c0	/* UTC2 Gate select */
#define LAS0_UOUT0_SELECT	0x01c4	/* User Output 0 source select */
#define LAS0_UOUT1_SELECT	0x01c8	/* User Output 1 source select */
#define LAS0_DMA0_RESET		0x01cc	/* DMA0 Request state machine reset */
#define LAS0_DMA1_RESET		0x01d0	/* DMA1 Request state machine reset */

/*
 * Local Address Space 1 Offsets
 */
#define LAS1_ADC_FIFO		0x0000	/* A/D FIFO (16bit) */
#define LAS1_HDIO_FIFO		0x0004	/* HiSpd DI FIFO (16bit) */
#define LAS1_DAC1_FIFO		0x0008	/* D/A1 FIFO (16bit) */
#define LAS1_DAC2_FIFO		0x000c	/* D/A2 FIFO (16bit) */

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/*======================================================================
  Driver specific stuff (tunable)
======================================================================*/

/* We really only need 2 buffers.  More than that means being much
   smarter about knowing which ones are full. */
#define DMA_CHAIN_COUNT 2	/* max DMA segments/buffers in a ring (min 2) */

/* Target period for periodic transfers.  This sets the user read latency. */
/* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
/* If this is too low, efficiency is poor */
#define TRANS_TARGET_PERIOD 10000000	/* 10 ms (in nanoseconds) */

/* Set a practical limit on how long a list to support (affects memory use) */
/* The board support a channel list up to the FIFO length (1K or 8K) */
#define RTD_MAX_CHANLIST	128	/* max channel list that we allow */

/* tuning for ai/ao instruction done polling */
#ifdef FAST_SPIN
#define WAIT_QUIETLY		/* as nothing, spin on done bit */
#define RTD_ADC_TIMEOUT	66000	/* 2 msec at 33mhz bus rate */
#define RTD_DAC_TIMEOUT	66000
#define RTD_DMA_TIMEOUT	33000	/* 1 msec */
#else
/* by delaying, power and electrical noise are reduced somewhat */
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#define WAIT_QUIETLY	udelay(1)
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#define RTD_ADC_TIMEOUT	2000	/* in usec */
#define RTD_DAC_TIMEOUT	2000	/* in usec */
#define RTD_DMA_TIMEOUT	1000	/* in usec */
#endif

/*======================================================================
  Board specific stuff
======================================================================*/

#define RTD_CLOCK_RATE	8000000	/* 8Mhz onboard clock */
#define RTD_CLOCK_BASE	125	/* clock period in ns */

/* Note: these speed are slower than the spec, but fit the counter resolution*/
#define RTD_MAX_SPEED	1625	/* when sampling, in nanoseconds */
/* max speed if we don't have to wait for settling */
#define RTD_MAX_SPEED_1	875	/* if single channel, in nanoseconds */

#define RTD_MIN_SPEED	2097151875	/* (24bit counter) in nanoseconds */
/* min speed when only 1 channel (no burst counter) */
#define RTD_MIN_SPEED_1	5000000	/* 200Hz, in nanoseconds */

/* Setup continuous ring of 1/2 FIFO transfers.  See RTD manual p91 */
#define DMA_MODE_BITS (\
		       PLX_LOCAL_BUS_16_WIDE_BITS \
		       | PLX_DMA_EN_READYIN_BIT \
		       | PLX_DMA_LOCAL_BURST_EN_BIT \
		       | PLX_EN_CHAIN_BIT \
		       | PLX_DMA_INTR_PCI_BIT \
		       | PLX_LOCAL_ADDR_CONST_BIT \
		       | PLX_DEMAND_MODE_BIT)

#define DMA_TRANSFER_BITS (\
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/* descriptors in PCI memory*/  PLX_DESC_IN_PCI_BIT \
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/* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
/* from board to PCI */		| PLX_XFER_LOCAL_TO_PCI)

/*======================================================================
  Comedi specific stuff
======================================================================*/

/*
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 * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
 */
static const struct comedi_lrange rtd_ai_7520_range = {
	18, {
		/* +-5V input range gain steps */
		BIP_RANGE(5.0),
		BIP_RANGE(5.0 / 2),
		BIP_RANGE(5.0 / 4),
		BIP_RANGE(5.0 / 8),
		BIP_RANGE(5.0 / 16),
		BIP_RANGE(5.0 / 32),
		/* +-10V input range gain steps */
		BIP_RANGE(10.0),
		BIP_RANGE(10.0 / 2),
		BIP_RANGE(10.0 / 4),
		BIP_RANGE(10.0 / 8),
		BIP_RANGE(10.0 / 16),
		BIP_RANGE(10.0 / 32),
		/* +10V input range gain steps */
		UNI_RANGE(10.0),
		UNI_RANGE(10.0 / 2),
		UNI_RANGE(10.0 / 4),
		UNI_RANGE(10.0 / 8),
		UNI_RANGE(10.0 / 16),
		UNI_RANGE(10.0 / 32),
	}
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};

/* PCI4520 has two more gains (6 more entries) */
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static const struct comedi_lrange rtd_ai_4520_range = {
	24, {
		/* +-5V input range gain steps */
		BIP_RANGE(5.0),
		BIP_RANGE(5.0 / 2),
		BIP_RANGE(5.0 / 4),
		BIP_RANGE(5.0 / 8),
		BIP_RANGE(5.0 / 16),
		BIP_RANGE(5.0 / 32),
		BIP_RANGE(5.0 / 64),
		BIP_RANGE(5.0 / 128),
		/* +-10V input range gain steps */
		BIP_RANGE(10.0),
		BIP_RANGE(10.0 / 2),
		BIP_RANGE(10.0 / 4),
		BIP_RANGE(10.0 / 8),
		BIP_RANGE(10.0 / 16),
		BIP_RANGE(10.0 / 32),
		BIP_RANGE(10.0 / 64),
		BIP_RANGE(10.0 / 128),
		/* +10V input range gain steps */
		UNI_RANGE(10.0),
		UNI_RANGE(10.0 / 2),
		UNI_RANGE(10.0 / 4),
		UNI_RANGE(10.0 / 8),
		UNI_RANGE(10.0 / 16),
		UNI_RANGE(10.0 / 32),
		UNI_RANGE(10.0 / 64),
		UNI_RANGE(10.0 / 128),
	}
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};

/* Table order matches range values */
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static const struct comedi_lrange rtd_ao_range = {
	4, {
		UNI_RANGE(5),
		UNI_RANGE(10),
		BIP_RANGE(5),
		BIP_RANGE(10),
	}
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};

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enum rtd_boardid {
	BOARD_DM7520,
	BOARD_PCI4520,
};

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struct rtd_boardinfo {
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	const char *name;
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	int range_bip10;	/* start of +-10V range */
	int range_uni10;	/* start of +10V range */
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	const struct comedi_lrange *ai_range;
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};
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static const struct rtd_boardinfo rtd520Boards[] = {
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	[BOARD_DM7520] = {
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		.name		= "DM7520",
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		.range_bip10	= 6,
		.range_uni10	= 12,
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		.ai_range	= &rtd_ai_7520_range,
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	},
	[BOARD_PCI4520] = {
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		.name		= "PCI4520",
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		.range_bip10	= 8,
		.range_uni10	= 16,
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		.ai_range	= &rtd_ai_4520_range,
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	},
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};

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struct rtd_private {
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	/* memory mapped board structures */
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	void __iomem *las0;
	void __iomem *las1;
	void __iomem *lcfg;
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	long ai_count;		/* total transfer size (samples) */
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	int xfer_count;		/* # to transfer data. 0->1/2FIFO */
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	int flags;		/* flag event modes */
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	DECLARE_BITMAP(chan_is_bipolar, RTD_MAX_CHANLIST);
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	unsigned int ao_readback[2];
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	unsigned fifosz;
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};
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/* bit defines for "flags" */
#define SEND_EOS	0x01	/* send End Of Scan events */
#define DMA0_ACTIVE	0x02	/* DMA0 is active */
#define DMA1_ACTIVE	0x04	/* DMA1 is active */

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/*
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  Given a desired period and the clock period (both in ns),
  return the proper counter value (divider-1).
  Sets the original period to be the true value.
  Note: you have to check if the value is larger than the counter range!
*/
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static int rtd_ns_to_timer_base(unsigned int *nanosec,
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				int round_mode, int base)
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{
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	int divider;

	switch (round_mode) {
	case TRIG_ROUND_NEAREST:
	default:
		divider = (*nanosec + base / 2) / base;
		break;
	case TRIG_ROUND_DOWN:
		divider = (*nanosec) / base;
		break;
	case TRIG_ROUND_UP:
		divider = (*nanosec + base - 1) / base;
		break;
	}
	if (divider < 2)
		divider = 2;	/* min is divide by 2 */

	/* Note: we don't check for max, because different timers
	   have different ranges */

	*nanosec = base * divider;
	return divider - 1;	/* countdown is divisor+1 */
}
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/*
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  Given a desired period (in ns),
  return the proper counter value (divider-1) for the internal clock.
  Sets the original period to be the true value.
*/
static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
{
	return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
}
449

450
451
452
/*
  Convert a single comedi channel-gain entry to a RTD520 table entry
*/
453
454
455
static unsigned short rtd_convert_chan_gain(struct comedi_device *dev,
					    unsigned int chanspec, int index)
{
456
	const struct rtd_boardinfo *board = comedi_board(dev);
457
	struct rtd_private *devpriv = dev->private;
458
459
460
	unsigned int chan = CR_CHAN(chanspec);
	unsigned int range = CR_RANGE(chanspec);
	unsigned int aref = CR_AREF(chanspec);
461
	unsigned short r = 0;
462

463
	r |= chan & 0xf;
464

465
	/* Note: we also setup the channel list bipolar flag array */
466
	if (range < board->range_bip10) {
467
468
469
		/* +-5 range */
		r |= 0x000;
		r |= (range & 0x7) << 4;
470
		__set_bit(index, devpriv->chan_is_bipolar);
471
	} else if (range < board->range_uni10) {
472
473
		/* +-10 range */
		r |= 0x100;
474
		r |= ((range - board->range_bip10) & 0x7) << 4;
475
		__set_bit(index, devpriv->chan_is_bipolar);
476
477
478
	} else {
		/* +10 range */
		r |= 0x200;
479
		r |= ((range - board->range_uni10) & 0x7) << 4;
480
		__clear_bit(index, devpriv->chan_is_bipolar);
481
	}
482

483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
	switch (aref) {
	case AREF_GROUND:	/* on-board ground */
		break;

	case AREF_COMMON:
		r |= 0x80;	/* ref external analog common */
		break;

	case AREF_DIFF:
		r |= 0x400;	/* differential inputs */
		break;

	case AREF_OTHER:	/* ??? */
		break;
	}
	/*printk ("chan=%d r=%d a=%d -> 0x%x\n",
	   chan, range, aref, r); */
	return r;
}

/*
  Setup the channel-gain table from a comedi list
*/
static void rtd_load_channelgain_list(struct comedi_device *dev,
				      unsigned int n_chan, unsigned int *list)
{
509
	struct rtd_private *devpriv = dev->private;
510

511
512
	if (n_chan > 1) {	/* setup channel gain table */
		int ii;
513
514

		writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
515
		writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
516
		for (ii = 0; ii < n_chan; ii++) {
517
			writel(rtd_convert_chan_gain(dev, list[ii], ii),
518
				devpriv->las0 + LAS0_CGT_WRITE);
519
		}
520
	} else {		/* just use the channel gain latch */
521
		writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
522
		writel(rtd_convert_chan_gain(dev, list[0], 0),
523
			devpriv->las0 + LAS0_CGL_WRITE);
524
	}
525
526
527
528
529
530
}

/* determine fifo size by doing adc conversions until the fifo half
empty status flag clears */
static int rtd520_probe_fifo_depth(struct comedi_device *dev)
{
531
	struct rtd_private *devpriv = dev->private;
532
533
534
535
536
	unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
	unsigned i;
	static const unsigned limit = 0x2000;
	unsigned fifo_size = 0;

537
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
538
	rtd_load_channelgain_list(dev, 1, &chanspec);
539
	/* ADC conversion trigger source: SOFTWARE */
540
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
541
542
543
544
	/* convert  samples */
	for (i = 0; i < limit; ++i) {
		unsigned fifo_status;
		/* trigger conversion */
545
		writew(0, devpriv->las0 + LAS0_ADC);
546
		udelay(1);
547
		fifo_status = readl(devpriv->las0 + LAS0_ADC);
548
549
550
		if ((fifo_status & FS_ADC_HEMPTY) == 0) {
			fifo_size = 2 * i;
			break;
551
		}
552
553
	}
	if (i == limit) {
554
		dev_info(dev->class_dev, "failed to probe fifo size.\n");
555
556
		return -EIO;
	}
557
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
558
	if (fifo_size != 0x400 && fifo_size != 0x2000) {
559
560
561
		dev_info(dev->class_dev,
			 "unexpected fifo size of %i, expected 1024 or 8192.\n",
			 fifo_size);
562
		return -EIO;
563
	}
564
565
	return fifo_size;
}
566

567
568
569
570
/*
  "instructions" read/write data in "one-shot" or "software-triggered"
  mode (simplest case).
  This doesn't use interrupts.
571

572
573
574
575
576
577
578
  Note, we don't do any settling delays.  Use a instruction list to
  select, delay, then read.
 */
static int rtd_ai_rinsn(struct comedi_device *dev,
			struct comedi_subdevice *s, struct comedi_insn *insn,
			unsigned int *data)
{
579
	struct rtd_private *devpriv = dev->private;
580
581
	int n, ii;
	int stat;
582

583
	/* clear any old fifo data */
584
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
585

586
587
	/* write channel to multiplexer and clear channel gain table */
	rtd_load_channelgain_list(dev, 1, &insn->chanspec);
588

589
	/* ADC conversion trigger source: SOFTWARE */
590
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
591

592
593
	/* convert n samples */
	for (n = 0; n < insn->n; n++) {
594
		unsigned short d;
595
		/* trigger conversion */
596
		writew(0, devpriv->las0 + LAS0_ADC);
597
598

		for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
599
			stat = readl(devpriv->las0 + LAS0_ADC);
600
601
602
603
			if (stat & FS_ADC_NOT_EMPTY)	/* 1 -> not empty */
				break;
			WAIT_QUIETLY;
		}
604
		if (ii >= RTD_ADC_TIMEOUT)
605
606
607
			return -ETIMEDOUT;

		/* read data */
608
		d = readw(devpriv->las1 + LAS1_ADC_FIFO);
609
610
		/*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
		d = d >> 3;	/* low 3 bits are marker lines */
611
		if (test_bit(0, devpriv->chan_is_bipolar))
612
			/* convert to comedi unsigned data */
613
614
			d = comedi_offset_munge(s, d);
		data[n] = d & s->maxdata;
615
616
	}

617
618
619
	/* return the number of samples read/written */
	return n;
}
620

621
622
623
/*
  Get what we know is there.... Fast!
  This uses 1/2 the bus cycles of read_dregs (below).
624

625
626
627
628
629
  The manual claims that we can do a lword read, but it doesn't work here.
*/
static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
		     int count)
{
630
	struct rtd_private *devpriv = dev->private;
631
	int ii;
632

633
	for (ii = 0; ii < count; ii++) {
634
		unsigned short d;
635

636
		if (0 == devpriv->ai_count) {	/* done */
637
			d = readw(devpriv->las1 + LAS1_ADC_FIFO);
638
639
			continue;
		}
640

641
		d = readw(devpriv->las1 + LAS1_ADC_FIFO);
642
		d = d >> 3;	/* low 3 bits are marker lines */
643
		if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
644
			/* convert to comedi unsigned data */
645
646
			d = comedi_offset_munge(s, d);
		d &= s->maxdata;
647

648
		if (!comedi_buf_put(s->async, d))
649
			return -1;
650

651
652
		if (devpriv->ai_count > 0)	/* < 0, means read forever */
			devpriv->ai_count--;
653
654
655
	}
	return 0;
}
656

657
658
659
660
661
/*
  unknown amout of data is waiting in fifo.
*/
static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
{
662
	struct rtd_private *devpriv = dev->private;
663

664
	while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
665
		unsigned short d = readw(devpriv->las1 + LAS1_ADC_FIFO);
666

667
		if (0 == devpriv->ai_count) {	/* done */
668
669
			continue;	/* read rest */
		}
670

671
		d = d >> 3;	/* low 3 bits are marker lines */
672
		if (test_bit(s->async->cur_chan, devpriv->chan_is_bipolar))
673
			/* convert to comedi unsigned data */
674
675
			d = comedi_offset_munge(s, d);
		d &= s->maxdata;
676

677
		if (!comedi_buf_put(s->async, d))
678
			return -1;
679

680
681
		if (devpriv->ai_count > 0)	/* < 0, means read forever */
			devpriv->ai_count--;
682
683
684
	}
	return 0;
}
685

686
687
688
689
690
691
/*
  Handle all rtd520 interrupts.
  Runs atomically and is never re-entered.
  This is a "slow handler";  other interrupts may be active.
  The data conversion may someday happen in a "bottom half".
*/
692
693
static irqreturn_t rtd_interrupt(int irq, void *d)
{
694
	struct comedi_device *dev = d;
695
	struct comedi_subdevice *s = &dev->subdevices[0];
696
	struct rtd_private *devpriv = dev->private;
697
	u32 overrun;
698
	u16 status;
699
	u16 fifo_status;
700

701
702
	if (!dev->attached)
		return IRQ_NONE;
703

704
	fifo_status = readl(devpriv->las0 + LAS0_ADC);
705
	/* check for FIFO full, this automatically halts the ADC! */
706
707
	if (!(fifo_status & FS_ADC_NOT_FULL))	/* 0 -> full */
		goto xfer_abort;
708

709
	status = readw(devpriv->las0 + LAS0_IT);
710
711
712
713
714
	/* if interrupt was not caused by our board, or handled above */
	if (0 == status)
		return IRQ_HANDLED;

	if (status & IRQM_ADC_ABOUT_CNT) {	/* sample count -> read FIFO */
715
716
717
718
719
720
		/*
		 * since the priority interrupt controller may have queued
		 * a sample counter interrupt, even though we have already
		 * finished, we must handle the possibility that there is
		 * no data here
		 */
721
		if (!(fifo_status & FS_ADC_HEMPTY)) {
722
			/* FIFO half full */
723
			if (ai_read_n(dev, s, devpriv->fifosz / 2) < 0)
724
				goto xfer_abort;
725

726
			if (0 == devpriv->ai_count)
727
				goto xfer_done;
728

729
			comedi_event(dev, s);
730
		} else if (devpriv->xfer_count > 0) {
731
			if (fifo_status & FS_ADC_NOT_EMPTY) {
732
				/* FIFO not empty */
733
				if (ai_read_n(dev, s, devpriv->xfer_count) < 0)
734
					goto xfer_abort;
735

736
				if (0 == devpriv->ai_count)
737
					goto xfer_done;
738

739
740
				comedi_event(dev, s);
			}
741
742
743
		}
	}

744
	overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
745
	if (overrun)
746
		goto xfer_abort;
747

748
	/* clear the interrupt */
749
	writew(status, devpriv->las0 + LAS0_CLEAR);
750
	readw(devpriv->las0 + LAS0_CLEAR);
751
	return IRQ_HANDLED;
752

753
xfer_abort:
754
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
755
	s->async->events |= COMEDI_CB_ERROR;
756
	devpriv->ai_count = 0;	/* stop and don't transfer any more */
757
	/* fall into xfer_done */
758

759
xfer_done:
760
	/* pacer stop source: SOFTWARE */
761
	writel(0, devpriv->las0 + LAS0_PACER_STOP);
762
	writel(0, devpriv->las0 + LAS0_PACER);	/* stop pacer */
763
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
764
	writew(0, devpriv->las0 + LAS0_IT);
765

766
	if (devpriv->ai_count > 0) {	/* there shouldn't be anything left */
767
		fifo_status = readl(devpriv->las0 + LAS0_ADC);
768
769
		ai_read_dregs(dev, s);	/* read anything left in FIFO */
	}
770

771
772
	s->async->events |= COMEDI_CB_EOA;	/* signal end to comedi */
	comedi_event(dev, s);
773

774
	/* clear the interrupt */
775
	status = readw(devpriv->las0 + LAS0_IT);
776
	writew(status, devpriv->las0 + LAS0_CLEAR);
777
	readw(devpriv->las0 + LAS0_CLEAR);
778

779
	fifo_status = readl(devpriv->las0 + LAS0_ADC);
780
	overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
781
782

	return IRQ_HANDLED;
783
784
}

785
786
787
/*
  cmdtest tests a particular command to see if it is valid.
  Using the cmdtest ioctl, a user can create a valid cmd
788
  and then have it executed by the cmd ioctl (asynchronously).
789
790
791
792
793
794
795

  cmdtest returns 1,2,3,4 or 0, depending on which tests
  the command passes.
*/

static int rtd_ai_cmdtest(struct comedi_device *dev,
			  struct comedi_subdevice *s, struct comedi_cmd *cmd)
796
{
797
798
	int err = 0;
	int tmp;
799

800
	/* Step 1 : check if triggers are trivially valid */
801

802
803
804
805
806
807
	err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_begin_src,
					TRIG_TIMER | TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
808
809
810
811

	if (err)
		return 1;

812
	/* Step 2a : make sure trigger sources are unique */
813

814
815
816
817
818
	err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
	err |= cfc_check_trigger_is_unique(cmd->convert_src);
	err |= cfc_check_trigger_is_unique(cmd->stop_src);

	/* Step 2b : and mutually compatible */
819

820
821
	if (err)
		return 2;
822

823
	/* Step 3: check if arguments are trivially valid */
824

825
	err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
826

827
828
829
	if (cmd->scan_begin_src == TRIG_TIMER) {
		/* Note: these are time periods, not actual rates */
		if (1 == cmd->chanlist_len) {	/* no scanning */
830
831
			if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
						      RTD_MAX_SPEED_1)) {
832
833
				rtd_ns_to_timer(&cmd->scan_begin_arg,
						TRIG_ROUND_UP);
834
				err |= -EINVAL;
835
			}
836
837
			if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
						      RTD_MIN_SPEED_1)) {
838
839
				rtd_ns_to_timer(&cmd->scan_begin_arg,
						TRIG_ROUND_DOWN);
840
				err |= -EINVAL;
841
842
			}
		} else {
843
844
			if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
						      RTD_MAX_SPEED)) {
845
846
				rtd_ns_to_timer(&cmd->scan_begin_arg,
						TRIG_ROUND_UP);
847
				err |= -EINVAL;
848
			}
849
850
			if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
						      RTD_MIN_SPEED)) {
851
852
				rtd_ns_to_timer(&cmd->scan_begin_arg,
						TRIG_ROUND_DOWN);
853
				err |= -EINVAL;
854
			}
855
		}
856
857
858
859
	} else {
		/* external trigger */
		/* should be level/edge, hi/lo specification here */
		/* should specify multiple external triggers */
860
		err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
861
	}
862

863
864
	if (cmd->convert_src == TRIG_TIMER) {
		if (1 == cmd->chanlist_len) {	/* no scanning */
865
866
			if (cfc_check_trigger_arg_min(&cmd->convert_arg,
						      RTD_MAX_SPEED_1)) {
867
868
				rtd_ns_to_timer(&cmd->convert_arg,
						TRIG_ROUND_UP);
869
				err |= -EINVAL;
870
			}
871
872
			if (cfc_check_trigger_arg_max(&cmd->convert_arg,
						      RTD_MIN_SPEED_1)) {
873
874
				rtd_ns_to_timer(&cmd->convert_arg,
						TRIG_ROUND_DOWN);
875
				err |= -EINVAL;
876
877
			}
		} else {
878
879
			if (cfc_check_trigger_arg_min(&cmd->convert_arg,
						      RTD_MAX_SPEED)) {
880
881
				rtd_ns_to_timer(&cmd->convert_arg,
						TRIG_ROUND_UP);
882
				err |= -EINVAL;
883
			}
884
885
			if (cfc_check_trigger_arg_max(&cmd->convert_arg,
						      RTD_MIN_SPEED)) {
886
887
				rtd_ns_to_timer(&cmd->convert_arg,
						TRIG_ROUND_DOWN);
888
				err |= -EINVAL;
889
890
891
892
893
			}
		}
	} else {
		/* external trigger */
		/* see above */
894
		err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9);
895
896
897
898
899
900
	}

	if (cmd->stop_src == TRIG_COUNT) {
		/* TODO check for rounding error due to counter wrap */
	} else {
		/* TRIG_NONE */
901
		err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
902
	}
903

904
905
	if (err)
		return 3;
906

907
908
909
910
911
912

	/* step 4: fix up any arguments */

	if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
		cmd->chanlist_len = RTD_MAX_CHANLIST;
		err++;
913
	}
914
915
916
917
918
919
	if (cmd->scan_begin_src == TRIG_TIMER) {
		tmp = cmd->scan_begin_arg;
		rtd_ns_to_timer(&cmd->scan_begin_arg,
				cmd->flags & TRIG_ROUND_MASK);
		if (tmp != cmd->scan_begin_arg)
			err++;
920

921
922
923
924
925
926
927
	}
	if (cmd->convert_src == TRIG_TIMER) {
		tmp = cmd->convert_arg;
		rtd_ns_to_timer(&cmd->convert_arg,
				cmd->flags & TRIG_ROUND_MASK);
		if (tmp != cmd->convert_arg)
			err++;
928

929
930
931
932
933
934
		if (cmd->scan_begin_src == TRIG_TIMER
		    && (cmd->scan_begin_arg
			< (cmd->convert_arg * cmd->scan_end_arg))) {
			cmd->scan_begin_arg =
			    cmd->convert_arg * cmd->scan_end_arg;
			err++;
935
		}
936
	}
937

938
939
	if (err)
		return 4;
940
941
942
943
944

	return 0;
}

/*
945
946
947
948
  Execute a analog in command with many possible triggering options.
  The data get stored in the async structure of the subdevice.
  This is usually done by an interrupt handler.
  Userland gets to the data using read calls.
949
*/
950
951
static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
{
952
	struct rtd_private *devpriv = dev->private;
953
954
	struct comedi_cmd *cmd = &s->async->cmd;
	int timer;
955

956
	/* stop anything currently running */
957
	/* pacer stop source: SOFTWARE */
958
	writel(0, devpriv->las0 + LAS0_PACER_STOP);
959
	writel(0, devpriv->las0 + LAS0_PACER);	/* stop pacer */
960
	writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
961
	writew(0, devpriv->las0 + LAS0_IT);
962
	writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
963
	writel(0, devpriv->las0 + LAS0_OVERRUN);
964

965
966
967
	/* start configuration */
	/* load channel list and reset CGT */
	rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
968

969
970
	/* setup the common case and override if needed */
	if (cmd->chanlist_len > 1) {
971
		/* pacer start source: SOFTWARE */
972
		writel(0, devpriv->las0 + LAS0_PACER_START);
973
		/* burst trigger source: PACER */
974
		writel(1, devpriv->las0 + LAS0_BURST_START);
975
		/* ADC conversion trigger source: BURST */
976
		writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
977
	} else {		/* single channel */
978
		/* pacer start source: SOFTWARE */
979
		writel(0, devpriv->las0 + LAS0_PACER_START);
980
		/* ADC conversion trigger source: PACER */
981
		writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
982
	}
983
	writel((devpriv->fifosz / 2 - 1) & 0xffff, devpriv->las0 + LAS0_ACNT);
984
985
986
987
988

	if (TRIG_TIMER == cmd->scan_begin_src) {
		/* scan_begin_arg is in nanoseconds */
		/* find out how many samples to wait before transferring */
		if (cmd->flags & TRIG_WAKE_EOS) {
989
990
991
992
993
			/*
			 * this may generate un-sustainable interrupt rates
			 * the application is responsible for doing the
			 * right thing
			 */
994
			devpriv->xfer_count = cmd->chanlist_len;
995
996
997
			devpriv->flags |= SEND_EOS;
		} else {
			/* arrange to transfer data periodically */
998
			devpriv->xfer_count =
999
1000
			    (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
			    cmd->scan_begin_arg;