nouveau_dp.c 11.1 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
/*
 * Copyright 2009 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

25
#include <drm/drmP.h>
26
#include <drm/drm_dp_helper.h>
27

28
#include "nouveau_drm.h"
29
#include "nouveau_connector.h"
30
#include "nouveau_encoder.h"
31
#include "nouveau_crtc.h"
32

33
34
#include <core/class.h>

35
36
#include <subdev/gpio.h>
#include <subdev/i2c.h>
37

38
39
40
41
/******************************************************************************
 * link training
 *****************************************************************************/
struct dp_state {
42
	struct nouveau_i2c_port *auxch;
43
	struct nouveau_object *core;
44
	struct dcb_output *dcb;
45
	int crtc;
46
	u8 *dpcd;
47
48
49
50
51
	int link_nr;
	u32 link_bw;
	u8  stat[6];
	u8  conf[4];
};
52

53
54
static void
dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
55
{
56
	struct nouveau_drm *drm = nouveau_drm(dev);
57
58
59
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;
60
	u8 sink[2];
61
	u32 data;
62

63
	NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
64

65
	/* set desired link configuration on the source */
66
67
68
69
70
	data = ((dp->link_bw / 27000) << 8) | dp->link_nr;
	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
		data |= NV94_DISP_SOR_DP_LNKCTL_FRAME_ENH;

	nv_call(dp->core, NV94_DISP_SOR_DP_LNKCTL + moff, data);
71

72
73
	/* inform the sink of the new configuration */
	sink[0] = dp->link_bw / 27000;
74
	sink[1] = dp->link_nr;
75
	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
76
		sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
77

78
	nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2);
79
80
}

81
static void
82
dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
83
{
84
	struct nouveau_drm *drm = nouveau_drm(dev);
85
86
87
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;
88
89
	u8 sink_tp;

90
	NV_DEBUG(drm, "training pattern %d\n", pattern);
91

92
	nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, pattern);
93

94
	nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
95
	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
96
	sink_tp |= pattern;
97
	nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
98
99
100
}

static int
101
dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
102
{
103
	struct nouveau_drm *drm = nouveau_drm(dev);
104
105
106
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;
107
108
109
	int i;

	for (i = 0; i < dp->link_nr; i++) {
110
111
112
		u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
		u8 lpre = (lane & 0x0c) >> 2;
		u8 lvsw = (lane & 0x03) >> 0;
113

114
115
		dp->conf[i] = (lpre << 3) | lvsw;
		if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
116
			dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
117
		if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
118
			dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
119

120
		NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]);
121
122

		nv_call(dp->core, NV94_DISP_SOR_DP_DRVCTL(i) + moff, (lvsw << 8) | lpre);
123
124
	}

125
	return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
126
127
}

128
129
static int
dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
130
{
131
	struct nouveau_drm *drm = nouveau_drm(dev);
132
	int ret;
133

134
	udelay(delay);
135

136
	ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
137
	if (ret)
138
		return ret;
139

140
	NV_DEBUG(drm, "status %*ph\n", 6, dp->stat);
141
142
	return 0;
}
143

144
145
146
147
148
149
static int
dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
{
	bool cr_done = false, abort = false;
	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	int tries = 0, i;
150

151
	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
152

153
154
155
156
	do {
		if (dp_link_train_commit(dev, dp) ||
		    dp_link_train_update(dev, dp, 100))
			break;
157

158
159
160
161
162
163
164
165
166
167
		cr_done = true;
		for (i = 0; i < dp->link_nr; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE)) {
				cr_done = false;
				if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
					abort = true;
				break;
			}
		}
168

169
170
171
172
173
		if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
			voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
			tries = 0;
		}
	} while (!cr_done && !abort && ++tries < 5);
174

175
	return cr_done ? 0 : -1;
176
177
}

178
179
static int
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
180
{
181
182
	bool eq_done, cr_done = true;
	int tries = 0, i;
183

184
	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
185

186
187
	do {
		if (dp_link_train_update(dev, dp, 400))
188
189
			break;

190
191
192
193
194
195
196
197
198
		eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
		for (i = 0; i < dp->link_nr && eq_done; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE))
				cr_done = false;
			if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
			    !(lane & DP_LANE_SYMBOL_LOCKED))
				eq_done = false;
		}
199

200
201
202
203
204
		if (dp_link_train_commit(dev, dp))
			break;
	} while (!eq_done && cr_done && ++tries <= 5);

	return eq_done ? 0 : -1;
205
206
}

207
static void
208
dp_link_train_init(struct drm_device *dev, struct dp_state *dp, bool spread)
209
{
210
211
212
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;
213

214
215
216
217
	nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, (spread ?
			  NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON :
			  NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_OFF) |
			  NV94_DISP_SOR_DP_TRAIN_OP_INIT);
218
219
220
221
222
}

static void
dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
{
223
224
225
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;
226

227
228
	nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff,
			  NV94_DISP_SOR_DP_TRAIN_OP_FINI);
229
230
}

231
static bool
232
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
233
		      struct nouveau_object *core)
234
235
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
236
237
238
239
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nouveau_connector *nv_connector =
		nouveau_encoder_connector_get(nv_encoder);
	struct drm_device *dev = encoder->dev;
240
241
242
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
243
244
245
	const u32 bw_list[] = { 270000, 162000, 0 };
	const u32 *link_bw = bw_list;
	struct dp_state dp;
246

247
	dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
248
	if (!dp.auxch)
249
250
		return false;

251
	dp.core = core;
252
253
	dp.dcb = nv_encoder->dcb;
	dp.crtc = nv_crtc->index;
254
	dp.dpcd = nv_encoder->dp.dpcd;
255

256
257
258
	/* adjust required bandwidth for 8B/10B coding overhead */
	datarate = (datarate / 8) * 10;

259
260
261
262
	/* some sinks toggle hotplug in response to some of the actions
	 * we take during link training (DP_SET_POWER is one), we need
	 * to ignore them for the moment to avoid races.
	 */
263
264
	nouveau_event_put(gpio->events, nv_connector->hpd.line,
			 &nv_connector->hpd_func);
265

266
267
	/* enable down-spreading and execute pre-train script from vbios */
	dp_link_train_init(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
268

269
	/* start off at highest link rate supported by encoder and display */
270
	while (*link_bw > nv_encoder->dp.link_bw)
271
		link_bw++;
272

273
274
275
276
277
	while (link_bw[0]) {
		/* find minimum required lane count at this link rate */
		dp.link_nr = nv_encoder->dp.link_nr;
		while ((dp.link_nr >> 1) * link_bw[0] > datarate)
			dp.link_nr >>= 1;
278

279
280
281
282
		/* drop link rate to minimum with this lane count */
		while ((link_bw[1] * dp.link_nr) > datarate)
			link_bw++;
		dp.link_bw = link_bw[0];
283

284
285
		/* program selected link configuration */
		dp_set_link_config(dev, &dp);
286

287
288
289
290
		/* attempt to train the link at this configuration */
		memset(dp.stat, 0x00, sizeof(dp.stat));
		if (!dp_link_train_cr(dev, &dp) &&
		    !dp_link_train_eq(dev, &dp))
291
292
			break;

293
294
		/* retry at lower rate */
		link_bw++;
295
296
	}

297
298
	/* finish link training */
	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
299

300
	/* execute post-train script from vbios */
301
	dp_link_train_fini(dev, &dp);
302

303
	/* re-enable hotplug detect */
304
305
	nouveau_event_get(gpio->events, nv_connector->hpd.line,
			 &nv_connector->hpd_func);
306
	return true;
307
308
}

309
310
void
nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
311
		struct nouveau_object *core)
312
313
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
314
315
	struct nouveau_drm *drm = nouveau_drm(encoder->dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
316
	struct nouveau_i2c_port *auxch;
317
318
	u8 status;

319
	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
320
321
322
323
324
325
326
327
	if (!auxch)
		return;

	if (mode == DRM_MODE_DPMS_ON)
		status = DP_SET_POWER_D0;
	else
		status = DP_SET_POWER_D3;

328
	nv_wraux(auxch, DP_SET_POWER, &status, 1);
329
330

	if (mode == DRM_MODE_DPMS_ON)
331
		nouveau_dp_link_train(encoder, datarate, core);
332
333
}

334
static void
335
nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch,
336
337
		     u8 *dpcd)
{
338
	struct nouveau_drm *drm = nouveau_drm(dev);
339
340
341
342
343
	u8 buf[3];

	if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

344
345
	if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3))
		NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
346
347
			     buf[0], buf[1], buf[2]);

348
349
	if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3))
		NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
350
351
352
353
			     buf[0], buf[1], buf[2]);

}

354
355
356
357
358
bool
nouveau_dp_detect(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_device *dev = encoder->dev;
359
360
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
361
	struct nouveau_i2c_port *auxch;
362
	u8 *dpcd = nv_encoder->dp.dpcd;
363
364
	int ret;

365
	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
366
367
368
	if (!auxch)
		return false;

369
	ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
370
371
372
	if (ret)
		return false;

373
374
	nv_encoder->dp.link_bw = 27000 * dpcd[1];
	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
375

376
	NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
377
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
378
	NV_DEBUG(drm, "encoder: %dx%d\n",
379
380
		     nv_encoder->dcb->dpconf.link_nr,
		     nv_encoder->dcb->dpconf.link_bw);
381

382
	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
383
		nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
384
385
	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
		nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
386

387
	NV_DEBUG(drm, "maximum: %dx%d\n",
388
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
389

390
391
	nouveau_dp_probe_oui(dev, auxch, dpcd);

392
393
	return true;
}