intel_audio.c 30.7 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include <linux/kernel.h>
Imre Deak's avatar
Imre Deak committed
25
26
#include <linux/component.h>
#include <drm/i915_component.h>
27
#include <drm/intel_lpe_audio.h>
Imre Deak's avatar
Imre Deak committed
28
#include "intel_drv.h"
29
30
31
32
33

#include <drm/drmP.h>
#include <drm/drm_edid.h>
#include "i915_drv.h"

34
35
36
37
38
39
40
41
42
43
44
/**
 * DOC: High Definition Audio over HDMI and Display Port
 *
 * The graphics and audio drivers together support High Definition Audio over
 * HDMI and Display Port. The audio programming sequences are divided into audio
 * codec and controller enable and disable sequences. The graphics driver
 * handles the audio codec sequences, while the audio driver handles the audio
 * controller sequences.
 *
 * The disable sequences must be performed before disabling the transcoder or
 * port. The enable sequences may only be performed after enabling the
45
46
 * transcoder and port, and after completed link training. Therefore the audio
 * enable/disable sequences are part of the modeset sequence.
47
48
49
50
51
52
53
 *
 * The codec and controller sequences could be done either parallel or serial,
 * but generally the ELDV/PD change in the codec sequence indicates to the audio
 * driver that the controller sequence should start. Indeed, most of the
 * co-operation between the graphics and audio drivers is handled via audio
 * related registers. (The notable exception is the power management, not
 * covered here.)
54
 *
55
56
 * The struct &i915_audio_component is used to interact between the graphics
 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
57
 * defined in graphics driver and called in audio driver. The
58
 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
59
60
 */

61
/* DP N/M table */
62
#define LC_810M	810000
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
#define LC_540M	540000
#define LC_270M	270000
#define LC_162M	162000

struct dp_aud_n_m {
	int sample_rate;
	int clock;
	u16 m;
	u16 n;
};

/* Values according to DP 1.4 Table 2-104 */
static const struct dp_aud_n_m dp_aud_n_m[] = {
	{ 32000, LC_162M, 1024, 10125 },
	{ 44100, LC_162M, 784, 5625 },
	{ 48000, LC_162M, 512, 3375 },
	{ 64000, LC_162M, 2048, 10125 },
	{ 88200, LC_162M, 1568, 5625 },
	{ 96000, LC_162M, 1024, 3375 },
	{ 128000, LC_162M, 4096, 10125 },
	{ 176400, LC_162M, 3136, 5625 },
	{ 192000, LC_162M, 2048, 3375 },
	{ 32000, LC_270M, 1024, 16875 },
	{ 44100, LC_270M, 784, 9375 },
	{ 48000, LC_270M, 512, 5625 },
	{ 64000, LC_270M, 2048, 16875 },
	{ 88200, LC_270M, 1568, 9375 },
	{ 96000, LC_270M, 1024, 5625 },
	{ 128000, LC_270M, 4096, 16875 },
	{ 176400, LC_270M, 3136, 9375 },
	{ 192000, LC_270M, 2048, 5625 },
	{ 32000, LC_540M, 1024, 33750 },
	{ 44100, LC_540M, 784, 18750 },
	{ 48000, LC_540M, 512, 11250 },
	{ 64000, LC_540M, 2048, 33750 },
	{ 88200, LC_540M, 1568, 18750 },
	{ 96000, LC_540M, 1024, 11250 },
	{ 128000, LC_540M, 4096, 33750 },
	{ 176400, LC_540M, 3136, 18750 },
	{ 192000, LC_540M, 2048, 11250 },
103
104
105
106
107
108
109
110
111
	{ 32000, LC_810M, 1024, 50625 },
	{ 44100, LC_810M, 784, 28125 },
	{ 48000, LC_810M, 512, 16875 },
	{ 64000, LC_810M, 2048, 50625 },
	{ 88200, LC_810M, 1568, 28125 },
	{ 96000, LC_810M, 1024, 16875 },
	{ 128000, LC_810M, 4096, 50625 },
	{ 176400, LC_810M, 3136, 28125 },
	{ 192000, LC_810M, 2048, 16875 },
112
113
114
};

static const struct dp_aud_n_m *
115
audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
116
117
118
119
120
{
	int i;

	for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
		if (rate == dp_aud_n_m[i].sample_rate &&
121
		    crtc_state->port_clock == dp_aud_n_m[i].clock)
122
123
124
125
126
127
			return &dp_aud_n_m[i];
	}

	return NULL;
}

128
static const struct {
129
130
131
	int clock;
	u32 config;
} hdmi_audio_clock[] = {
132
	{ 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
133
134
	{ 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
	{ 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
135
	{ 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
136
	{ 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
137
138
	{ 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
	{ 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
139
	{ 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
140
	{ 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
141
142
143
	{ 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
};

144
145
/* HDMI N/CTS table */
#define TMDS_297M 297000
146
#define TMDS_296M 296703
147
148
149
#define TMDS_594M 594000
#define TMDS_593M 593407

150
151
152
153
154
static const struct {
	int sample_rate;
	int clock;
	int n;
	int cts;
155
} hdmi_aud_ncts[] = {
156
157
158
159
160
161
162
163
164
165
166
167
168
169
	{ 44100, TMDS_296M, 4459, 234375 },
	{ 44100, TMDS_297M, 4704, 247500 },
	{ 48000, TMDS_296M, 5824, 281250 },
	{ 48000, TMDS_297M, 5120, 247500 },
	{ 32000, TMDS_296M, 5824, 421875 },
	{ 32000, TMDS_297M, 3072, 222750 },
	{ 88200, TMDS_296M, 8918, 234375 },
	{ 88200, TMDS_297M, 9408, 247500 },
	{ 96000, TMDS_296M, 11648, 281250 },
	{ 96000, TMDS_297M, 10240, 247500 },
	{ 176400, TMDS_296M, 17836, 234375 },
	{ 176400, TMDS_297M, 18816, 247500 },
	{ 192000, TMDS_296M, 23296, 281250 },
	{ 192000, TMDS_297M, 20480, 247500 },
170
171
172
173
174
175
176
177
178
179
180
181
182
183
	{ 44100, TMDS_593M, 8918, 937500 },
	{ 44100, TMDS_594M, 9408, 990000 },
	{ 48000, TMDS_593M, 5824, 562500 },
	{ 48000, TMDS_594M, 6144, 594000 },
	{ 32000, TMDS_593M, 5824, 843750 },
	{ 32000, TMDS_594M, 3072, 445500 },
	{ 88200, TMDS_593M, 17836, 937500 },
	{ 88200, TMDS_594M, 18816, 990000 },
	{ 96000, TMDS_593M, 11648, 562500 },
	{ 96000, TMDS_594M, 12288, 594000 },
	{ 176400, TMDS_593M, 35672, 937500 },
	{ 176400, TMDS_594M, 37632, 990000 },
	{ 192000, TMDS_593M, 23296, 562500 },
	{ 192000, TMDS_594M, 24576, 594000 },
184
185
};

186
/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
187
static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
188
{
189
190
	const struct drm_display_mode *adjusted_mode =
		&crtc_state->base.adjusted_mode;
191
192
193
	int i;

	for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
194
		if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
195
196
197
198
			break;
	}

	if (i == ARRAY_SIZE(hdmi_audio_clock)) {
199
		DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
200
			      adjusted_mode->crtc_clock);
201
202
203
204
205
206
207
208
209
210
		i = 1;
	}

	DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
		      hdmi_audio_clock[i].clock,
		      hdmi_audio_clock[i].config);

	return hdmi_audio_clock[i].config;
}

211
static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
212
				   int rate)
213
{
214
215
	const struct drm_display_mode *adjusted_mode =
		&crtc_state->base.adjusted_mode;
216
217
	int i;

218
219
220
221
	for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
		if (rate == hdmi_aud_ncts[i].sample_rate &&
		    adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
			return hdmi_aud_ncts[i].n;
222
223
224
225
226
		}
	}
	return 0;
}

227
static bool intel_eld_uptodate(struct drm_connector *connector,
228
229
			       i915_reg_t reg_eldv, u32 bits_eldv,
			       i915_reg_t reg_elda, u32 bits_elda,
230
			       i915_reg_t reg_edid)
231
{
232
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
233
	const u8 *eld = connector->eld;
234
	u32 tmp;
235
	int i;
236

237
238
	tmp = I915_READ(reg_eldv);
	tmp &= bits_eldv;
239

240
	if (!tmp)
241
242
		return false;

243
244
245
	tmp = I915_READ(reg_elda);
	tmp &= ~bits_elda;
	I915_WRITE(reg_elda, tmp);
246

247
	for (i = 0; i < drm_eld_size(eld) / 4; i++)
248
		if (I915_READ(reg_edid) != *((const u32 *)eld + i))
249
250
251
252
253
			return false;

	return true;
}

254
255
256
static void g4x_audio_codec_disable(struct intel_encoder *encoder,
				    const struct intel_crtc_state *old_crtc_state,
				    const struct drm_connector_state *old_conn_state)
257
{
258
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
259
	u32 eldv, tmp;
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274

	DRM_DEBUG_KMS("Disable audio codec\n");

	tmp = I915_READ(G4X_AUD_VID_DID);
	if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

	/* Invalidate ELD */
	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp &= ~eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
}

275
276
277
static void g4x_audio_codec_enable(struct intel_encoder *encoder,
				   const struct intel_crtc_state *crtc_state,
				   const struct drm_connector_state *conn_state)
278
{
279
280
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct drm_connector *connector = conn_state->connector;
281
	const u8 *eld = connector->eld;
282
283
	u32 eldv;
	u32 tmp;
284
	int len, i;
285

286
	DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld));
287

288
289
	tmp = I915_READ(G4X_AUD_VID_DID);
	if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
290
291
292
293
294
295
		eldv = G4X_ELDV_DEVCL_DEVBLC;
	else
		eldv = G4X_ELDV_DEVCTG;

	if (intel_eld_uptodate(connector,
			       G4X_AUD_CNTL_ST, eldv,
296
			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
297
298
299
			       G4X_HDMIW_HDMIEDID))
		return;

300
	tmp = I915_READ(G4X_AUD_CNTL_ST);
301
	tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
302
303
	len = (tmp >> 9) & 0x1f;		/* ELD buffer size */
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
304

305
	len = min(drm_eld_size(eld) / 4, len);
306
307
	DRM_DEBUG_DRIVER("ELD size %d\n", len);
	for (i = 0; i < len; i++)
308
		I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
309

310
311
312
	tmp = I915_READ(G4X_AUD_CNTL_ST);
	tmp |= eldv;
	I915_WRITE(G4X_AUD_CNTL_ST, tmp);
313
314
}

315
static void
316
317
hsw_dp_audio_config_update(struct intel_encoder *encoder,
			   const struct intel_crtc_state *crtc_state)
318
{
319
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
320
	struct i915_audio_component *acomp = dev_priv->audio_component;
321
322
323
324
325
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
	enum port port = encoder->port;
	enum pipe pipe = crtc->pipe;
	const struct dp_aud_n_m *nm;
	int rate;
326
327
	u32 tmp;

328
329
	rate = acomp ? acomp->aud_sample_rate[port] : 0;
	nm = audio_config_dp_get_n_m(crtc_state, rate);
330
331
332
333
334
	if (nm)
		DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
	else
		DRM_DEBUG_KMS("using automatic Maud, Naud\n");

335
336
337
338
339
340
	tmp = I915_READ(HSW_AUD_CFG(pipe));
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	tmp |= AUD_CONFIG_N_VALUE_INDEX;

341
342
343
344
345
346
	if (nm) {
		tmp &= ~AUD_CONFIG_N_MASK;
		tmp |= AUD_CONFIG_N(nm->n);
		tmp |= AUD_CONFIG_N_PROG_ENABLE;
	}

347
	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
348
349
350
351
352
353
354
355
356
357
358
359
360

	tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
	tmp &= ~AUD_CONFIG_M_MASK;
	tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
	tmp &= ~AUD_M_CTS_M_PROG_ENABLE;

	if (nm) {
		tmp |= nm->m;
		tmp |= AUD_M_CTS_M_VALUE_INDEX;
		tmp |= AUD_M_CTS_M_PROG_ENABLE;
	}

	I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
361
362
363
}

static void
364
365
hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
			     const struct intel_crtc_state *crtc_state)
366
{
367
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
368
	struct i915_audio_component *acomp = dev_priv->audio_component;
369
370
371
372
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
	enum port port = encoder->port;
	enum pipe pipe = crtc->pipe;
	int n, rate;
373
374
	u32 tmp;

375
376
	rate = acomp ? acomp->aud_sample_rate[port] : 0;

377
378
379
380
	tmp = I915_READ(HSW_AUD_CFG(pipe));
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
381
	tmp |= audio_config_hdmi_pixel_clock(crtc_state);
382

383
	n = audio_config_hdmi_get_n(crtc_state, rate);
384
385
386
387
388
389
390
391
	if (n != 0) {
		DRM_DEBUG_KMS("using N %d\n", n);

		tmp &= ~AUD_CONFIG_N_MASK;
		tmp |= AUD_CONFIG_N(n);
		tmp |= AUD_CONFIG_N_PROG_ENABLE;
	} else {
		DRM_DEBUG_KMS("using automatic N\n");
392
393
394
	}

	I915_WRITE(HSW_AUD_CFG(pipe), tmp);
395

396
397
398
399
	/*
	 * Let's disable "Enable CTS or M Prog bit"
	 * and let HW calculate the value
	 */
400
	tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
401
	tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
402
403
	tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
	I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
404
405
}

406
static void
407
408
hsw_audio_config_update(struct intel_encoder *encoder,
			const struct intel_crtc_state *crtc_state)
409
{
410
411
	if (intel_crtc_has_dp_encoder(crtc_state))
		hsw_dp_audio_config_update(encoder, crtc_state);
412
	else
413
		hsw_hdmi_audio_config_update(encoder, crtc_state);
414
415
}

416
417
418
static void hsw_audio_codec_disable(struct intel_encoder *encoder,
				    const struct intel_crtc_state *old_crtc_state,
				    const struct drm_connector_state *old_conn_state)
419
{
420
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
421
422
	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
	enum pipe pipe = crtc->pipe;
423
	u32 tmp;
424

425
426
	DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));

427
428
	mutex_lock(&dev_priv->av_mutex);

429
430
431
432
433
434
	/* Disable timestamps */
	tmp = I915_READ(HSW_AUD_CFG(pipe));
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp |= AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
435
	if (intel_crtc_has_dp_encoder(old_crtc_state))
436
437
438
439
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	I915_WRITE(HSW_AUD_CFG(pipe), tmp);

	/* Invalidate ELD */
440
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
441
	tmp &= ~AUDIO_ELD_VALID(pipe);
442
	tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
443
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
444
445

	mutex_unlock(&dev_priv->av_mutex);
446
447
}

448
449
450
static void hsw_audio_codec_enable(struct intel_encoder *encoder,
				   const struct intel_crtc_state *crtc_state,
				   const struct drm_connector_state *conn_state)
451
{
452
453
454
455
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
	struct drm_connector *connector = conn_state->connector;
	enum pipe pipe = crtc->pipe;
456
457
	const u8 *eld = connector->eld;
	u32 tmp;
458
	int len, i;
459

460
	DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
461
		      pipe_name(pipe), drm_eld_size(eld));
462

463
464
	mutex_lock(&dev_priv->av_mutex);

465
466
	/* Enable audio presence detect, invalidate ELD */
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
467
468
	tmp |= AUDIO_OUTPUT_ENABLE(pipe);
	tmp &= ~AUDIO_ELD_VALID(pipe);
469
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
470

471
472
473
474
475
476
	/*
	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
	 * disabled during the mode set. The proper fix would be to push the
	 * rest of the setup into a vblank work item, queued here, but the
	 * infrastructure is not there yet.
	 */
477

478
479
	/* Reset ELD write address */
	tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
480
	tmp &= ~IBX_ELD_ADDRESS_MASK;
481
	I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
482

483
	/* Up to 84 bytes of hw ELD buffer */
484
485
	len = min(drm_eld_size(eld), 84);
	for (i = 0; i < len / 4; i++)
486
		I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const u32 *)eld + i));
487

488
	/* ELD valid */
489
	tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
490
	tmp |= AUDIO_ELD_VALID(pipe);
491
	I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
492
493

	/* Enable timestamps */
494
	hsw_audio_config_update(encoder, crtc_state);
495
496

	mutex_unlock(&dev_priv->av_mutex);
497
498
}

499
500
501
static void ilk_audio_codec_disable(struct intel_encoder *encoder,
				    const struct intel_crtc_state *old_crtc_state,
				    const struct drm_connector_state *old_conn_state)
502
{
503
504
505
506
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
	enum pipe pipe = crtc->pipe;
	enum port port = encoder->port;
507
	u32 tmp, eldv;
508
	i915_reg_t aud_config, aud_cntrl_st2;
509
510
511
512

	DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
		      port_name(port), pipe_name(pipe));

513
514
515
	if (WARN_ON(port == PORT_A))
		return;

516
	if (HAS_PCH_IBX(dev_priv)) {
517
518
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
519
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
520
521
522
523
524
525
526
527
528
529
530
531
532
		aud_config = VLV_AUD_CFG(pipe);
		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	} else {
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	}

	/* Disable timestamps */
	tmp = I915_READ(aud_config);
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp |= AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_UPPER_N_MASK;
	tmp &= ~AUD_CONFIG_LOWER_N_MASK;
533
	if (intel_crtc_has_dp_encoder(old_crtc_state))
534
535
536
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	I915_WRITE(aud_config, tmp);

537
	eldv = IBX_ELD_VALID(port);
538
539
540
541
542
543
544

	/* Invalidate ELD */
	tmp = I915_READ(aud_cntrl_st2);
	tmp &= ~eldv;
	I915_WRITE(aud_cntrl_st2, tmp);
}

545
546
547
static void ilk_audio_codec_enable(struct intel_encoder *encoder,
				   const struct intel_crtc_state *crtc_state,
				   const struct drm_connector_state *conn_state)
548
{
549
550
551
552
553
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
	struct drm_connector *connector = conn_state->connector;
	enum pipe pipe = crtc->pipe;
	enum port port = encoder->port;
554
	const u8 *eld = connector->eld;
555
	u32 tmp, eldv;
556
	int len, i;
557
	i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
558
559

	DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
560
		      port_name(port), pipe_name(pipe), drm_eld_size(eld));
561

562
563
564
	if (WARN_ON(port == PORT_A))
		return;

565
566
567
568
569
570
	/*
	 * FIXME: We're supposed to wait for vblank here, but we have vblanks
	 * disabled during the mode set. The proper fix would be to push the
	 * rest of the setup into a vblank work item, queued here, but the
	 * infrastructure is not there yet.
	 */
571

572
	if (HAS_PCH_IBX(dev_priv)) {
573
574
575
576
		hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
		aud_config = IBX_AUD_CFG(pipe);
		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
577
578
	} else if (IS_VALLEYVIEW(dev_priv) ||
		   IS_CHERRYVIEW(dev_priv)) {
579
580
581
582
583
584
585
586
587
588
589
		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
		aud_config = VLV_AUD_CFG(pipe);
		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
	} else {
		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
		aud_config = CPT_AUD_CFG(pipe);
		aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
		aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
	}

590
	eldv = IBX_ELD_VALID(port);
591

592
	/* Invalidate ELD */
593
594
595
	tmp = I915_READ(aud_cntrl_st2);
	tmp &= ~eldv;
	I915_WRITE(aud_cntrl_st2, tmp);
596

597
	/* Reset ELD write address */
598
	tmp = I915_READ(aud_cntl_st);
599
	tmp &= ~IBX_ELD_ADDRESS_MASK;
600
	I915_WRITE(aud_cntl_st, tmp);
601

602
	/* Up to 84 bytes of hw ELD buffer */
603
604
	len = min(drm_eld_size(eld), 84);
	for (i = 0; i < len / 4; i++)
605
		I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i));
606

607
	/* ELD valid */
608
609
610
	tmp = I915_READ(aud_cntrl_st2);
	tmp |= eldv;
	I915_WRITE(aud_cntrl_st2, tmp);
611
612
613
614
615
616

	/* Enable timestamps */
	tmp = I915_READ(aud_config);
	tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
	tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
	tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
617
	if (intel_crtc_has_dp_encoder(crtc_state))
618
619
		tmp |= AUD_CONFIG_N_VALUE_INDEX;
	else
620
		tmp |= audio_config_hdmi_pixel_clock(crtc_state);
621
	I915_WRITE(aud_config, tmp);
622
623
}

624
625
/**
 * intel_audio_codec_enable - Enable the audio codec for HD audio
626
 * @encoder: encoder on which to enable audio
627
628
 * @crtc_state: pointer to the current crtc state.
 * @conn_state: pointer to the current connector state.
629
630
631
632
 *
 * The enable sequences may only be performed after enabling the transcoder and
 * port, and after completed link training.
 */
633
void intel_audio_codec_enable(struct intel_encoder *encoder,
634
635
			      const struct intel_crtc_state *crtc_state,
			      const struct drm_connector_state *conn_state)
636
{
637
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
638
	struct i915_audio_component *acomp = dev_priv->audio_component;
639
640
641
642
643
644
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
	struct drm_connector *connector = conn_state->connector;
	const struct drm_display_mode *adjusted_mode =
		&crtc_state->base.adjusted_mode;
	enum port port = encoder->port;
	enum pipe pipe = crtc->pipe;
645

646
	if (!connector->eld[0])
647
648
649
650
651
652
653
654
		return;

	DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
			 connector->base.id,
			 connector->name,
			 connector->encoder->base.id,
			 connector->encoder->name);

655
	connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
656

657
	if (dev_priv->display.audio_codec_enable)
658
659
660
		dev_priv->display.audio_codec_enable(encoder,
						     crtc_state,
						     conn_state);
661

662
	mutex_lock(&dev_priv->av_mutex);
663
	encoder->audio_connector = connector;
664

665
	/* referred in audio callbacks */
666
	dev_priv->av_enc_map[pipe] = encoder;
667
668
	mutex_unlock(&dev_priv->av_mutex);

669
670
	if (acomp && acomp->base.audio_ops &&
	    acomp->base.audio_ops->pin_eld_notify) {
671
		/* audio drivers expect pipe = -1 to indicate Non-MST cases */
672
		if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
673
			pipe = -1;
674
		acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
675
						 (int) port, (int) pipe);
676
677
	}

678
	intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
679
			       crtc_state->port_clock,
680
			       intel_crtc_has_dp_encoder(crtc_state));
681
682
683
684
}

/**
 * intel_audio_codec_disable - Disable the audio codec for HD audio
685
 * @encoder: encoder on which to disable audio
686
687
 * @old_crtc_state: pointer to the old crtc state.
 * @old_conn_state: pointer to the old connector state.
688
689
690
691
 *
 * The disable sequences must be performed before disabling the transcoder or
 * port.
 */
692
693
694
void intel_audio_codec_disable(struct intel_encoder *encoder,
			       const struct intel_crtc_state *old_crtc_state,
			       const struct drm_connector_state *old_conn_state)
695
{
696
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
697
	struct i915_audio_component *acomp = dev_priv->audio_component;
698
699
	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
	enum port port = encoder->port;
700
	enum pipe pipe = crtc->pipe;
701
702

	if (dev_priv->display.audio_codec_disable)
703
704
705
		dev_priv->display.audio_codec_disable(encoder,
						      old_crtc_state,
						      old_conn_state);
706

707
	mutex_lock(&dev_priv->av_mutex);
708
	encoder->audio_connector = NULL;
709
	dev_priv->av_enc_map[pipe] = NULL;
710
711
	mutex_unlock(&dev_priv->av_mutex);

712
713
	if (acomp && acomp->base.audio_ops &&
	    acomp->base.audio_ops->pin_eld_notify) {
714
		/* audio drivers expect pipe = -1 to indicate Non-MST cases */
715
		if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
716
			pipe = -1;
717
		acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
718
						 (int) port, (int) pipe);
719
	}
720

721
	intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
722
723
724
}

/**
725
726
 * intel_init_audio_hooks - Set up chip specific audio hooks
 * @dev_priv: device private
727
 */
728
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
729
{
730
	if (IS_G4X(dev_priv)) {
731
		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
732
		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
733
	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
734
		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
735
		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
736
	} else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
737
738
		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
739
	} else if (HAS_PCH_SPLIT(dev_priv)) {
740
		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
741
		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
742
	}
743
}
Imre Deak's avatar
Imre Deak committed
744

745
static void i915_audio_component_get_power(struct device *kdev)
Imre Deak's avatar
Imre Deak committed
746
{
747
	intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
Imre Deak's avatar
Imre Deak committed
748
749
}

750
static void i915_audio_component_put_power(struct device *kdev)
Imre Deak's avatar
Imre Deak committed
751
{
752
	intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
Imre Deak's avatar
Imre Deak committed
753
754
}

755
static void i915_audio_component_codec_wake_override(struct device *kdev,
756
757
						     bool enable)
{
758
	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
759
760
	u32 tmp;

761
	if (!IS_GEN9(dev_priv))
762
763
		return;

764
	i915_audio_component_get_power(kdev);
765

766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
	/*
	 * Enable/disable generating the codec wake signal, overriding the
	 * internal logic to generate the codec wake to controller.
	 */
	tmp = I915_READ(HSW_AUD_CHICKENBIT);
	tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
	I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
	usleep_range(1000, 1500);

	if (enable) {
		tmp = I915_READ(HSW_AUD_CHICKENBIT);
		tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
		I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
		usleep_range(1000, 1500);
	}
781

782
	i915_audio_component_put_power(kdev);
783
784
}

Imre Deak's avatar
Imre Deak committed
785
/* Get CDCLK in kHz  */
786
static int i915_audio_component_get_cdclk_freq(struct device *kdev)
Imre Deak's avatar
Imre Deak committed
787
{
788
	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
Imre Deak's avatar
Imre Deak committed
789
790
791
792

	if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
		return -ENODEV;

793
	return dev_priv->cdclk.hw.cdclk;
Imre Deak's avatar
Imre Deak committed
794
795
}

796
797
798
799
800
801
802
803
804
805
/*
 * get the intel_encoder according to the parameter port and pipe
 * intel_encoder is saved by the index of pipe
 * MST & (pipe >= 0): return the av_enc_map[pipe],
 *   when port is matched
 * MST & (pipe < 0): this is invalid
 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
 *   will get the right intel_encoder with port matched
 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
 */
806
807
808
static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
					       int port, int pipe)
{
809
	struct intel_encoder *encoder;
810
811

	/* MST */
812
	if (pipe >= 0) {
813
814
815
		if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
			return NULL;

816
817
818
819
820
821
822
823
824
825
		encoder = dev_priv->av_enc_map[pipe];
		/*
		 * when bootup, audio driver may not know it is
		 * MST or not. So it will poll all the port & pipe
		 * combinations
		 */
		if (encoder != NULL && encoder->port == port &&
		    encoder->type == INTEL_OUTPUT_DP_MST)
			return encoder;
	}
826
827

	/* Non-MST */
828
829
	if (pipe > 0)
		return NULL;
830

831
	for_each_pipe(dev_priv, pipe) {
832
833
834
835
		encoder = dev_priv->av_enc_map[pipe];
		if (encoder == NULL)
			continue;

836
837
838
		if (encoder->type == INTEL_OUTPUT_DP_MST)
			continue;

839
840
841
842
843
844
845
846
847
		if (port == encoder->port)
			return encoder;
	}

	return NULL;
}

static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
						int pipe, int rate)
848
{
849
	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
850
	struct i915_audio_component *acomp = dev_priv->audio_component;
851
852
	struct intel_encoder *encoder;
	struct intel_crtc *crtc;
853
	int err = 0;
854

855
	if (!HAS_DDI(dev_priv))
856
857
		return 0;

858
	i915_audio_component_get_power(kdev);
859
	mutex_lock(&dev_priv->av_mutex);
860

861
	/* 1. get the pipe */
862
863
	encoder = get_saved_enc(dev_priv, port, pipe);
	if (!encoder || !encoder->base.crtc) {
864
		DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
865
866
		err = -ENODEV;
		goto unlock;
867
	}
868

869
	crtc = to_intel_crtc(encoder->base.crtc);
870

871
872
873
	/* port must be valid now, otherwise the pipe will be invalid */
	acomp->aud_sample_rate[port] = rate;

874
	hsw_audio_config_update(encoder, crtc->config);
875

876
 unlock:
877
	mutex_unlock(&dev_priv->av_mutex);
878
	i915_audio_component_put_power(kdev);
879
	return err;
880
881
}

882
static int i915_audio_component_get_eld(struct device *kdev, int port,
883
					int pipe, bool *enabled,
884
885
					unsigned char *buf, int max_bytes)
{
886
	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
887
888
889
890
891
	struct intel_encoder *intel_encoder;
	const u8 *eld;
	int ret = -EINVAL;

	mutex_lock(&dev_priv->av_mutex);
892
893
894
895
896
897
898
899
900
901
902
903
904
905

	intel_encoder = get_saved_enc(dev_priv, port, pipe);
	if (!intel_encoder) {
		DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
		mutex_unlock(&dev_priv->av_mutex);
		return ret;
	}

	ret = 0;
	*enabled = intel_encoder->audio_connector != NULL;
	if (*enabled) {
		eld = intel_encoder->audio_connector->eld;
		ret = drm_eld_size(eld);
		memcpy(buf, eld, min(max_bytes, ret));
906
907
908
909
	}

	mutex_unlock(&dev_priv->av_mutex);
	return ret;
910
911
}

912
static const struct drm_audio_component_ops i915_audio_component_ops = {
Imre Deak's avatar
Imre Deak committed
913
914
915
	.owner		= THIS_MODULE,
	.get_power	= i915_audio_component_get_power,
	.put_power	= i915_audio_component_put_power,
916
	.codec_wake_override = i915_audio_component_codec_wake_override,
Imre Deak's avatar
Imre Deak committed
917
	.get_cdclk_freq	= i915_audio_component_get_cdclk_freq,
918
	.sync_audio_rate = i915_audio_component_sync_audio_rate,
919
	.get_eld	= i915_audio_component_get_eld,
Imre Deak's avatar
Imre Deak committed
920
921
};

922
923
static int i915_audio_component_bind(struct device *i915_kdev,
				     struct device *hda_kdev, void *data)
Imre Deak's avatar
Imre Deak committed
924
925
{
	struct i915_audio_component *acomp = data;
926
	struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
927
	int i;
Imre Deak's avatar
Imre Deak committed
928

929
	if (WARN_ON(acomp->base.ops || acomp->base.dev))
Imre Deak's avatar
Imre Deak committed
930
931
		return -EEXIST;

932
933
934
	if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS)))
		return -ENOMEM;

935
	drm_modeset_lock_all(&dev_priv->drm);
936
937
	acomp->base.ops = &i915_audio_component_ops;
	acomp->base.dev = i915_kdev;
938
939
940
	BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
	for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
		acomp->aud_sample_rate[i] = 0;
941
	dev_priv->audio_component = acomp;
942
	drm_modeset_unlock_all(&dev_priv->drm);
Imre Deak's avatar
Imre Deak committed
943
944
945
946

	return 0;
}

947
948
static void i915_audio_component_unbind(struct device *i915_kdev,
					struct device *hda_kdev, void *data)
Imre Deak's avatar
Imre Deak committed
949
950
{
	struct i915_audio_component *acomp = data;
951
	struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
Imre Deak's avatar
Imre Deak committed
952

953
	drm_modeset_lock_all(&dev_priv->drm);
954
955
	acomp->base.ops = NULL;
	acomp->base.dev = NULL;
956
	dev_priv->audio_component = NULL;
957
	drm_modeset_unlock_all(&dev_priv->drm);
958
959

	device_link_remove(hda_kdev, i915_kdev);
Imre Deak's avatar
Imre Deak committed
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
}

static const struct component_ops i915_audio_component_bind_ops = {
	.bind	= i915_audio_component_bind,
	.unbind	= i915_audio_component_unbind,
};

/**
 * i915_audio_component_init - initialize and register the audio component
 * @dev_priv: i915 device instance
 *
 * This will register with the component framework a child component which
 * will bind dynamically to the snd_hda_intel driver's corresponding master
 * component when the latter is registered. During binding the child
 * initializes an instance of struct i915_audio_component which it receives
 * from the master. The master can then start to use the interface defined by
 * this struct. Each side can break the binding at any point by deregistering
 * its own component after which each side's component unbind callback is
 * called.
 *
 * We ignore any error during registration and continue with reduced
 * functionality (i.e. without HDMI audio).
 */
void i915_audio_component_init(struct drm_i915_private *dev_priv)
{
	int ret;

987
	ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
Imre Deak's avatar
Imre Deak committed
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
	if (ret < 0) {
		DRM_ERROR("failed to add audio component (%d)\n", ret);
		/* continue with reduced functionality */
		return;
	}

	dev_priv->audio_component_registered = true;
}

/**
 * i915_audio_component_cleanup - deregister the audio component
 * @dev_priv: i915 device instance
 *
 * Deregisters the audio component, breaking any existing binding to the
 * corresponding snd_hda_intel driver's master component.
 */
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
{
	if (!dev_priv->audio_component_registered)
		return;

1009
	component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
Imre Deak's avatar
Imre Deak committed
1010
1011
	dev_priv->audio_component_registered = false;
}
1012
1013
1014
1015
1016
1017
1018
1019