s626.c 102 KB
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/*
  comedi/drivers/s626.c
  Sensoray s626 Comedi driver

  COMEDI - Linux Control and Measurement Device Interface
  Copyright (C) 2000 David A. Schleef <ds@schleef.org>

  Based on Sensoray Model 626 Linux driver Version 0.2
  Copyright (C) 2002-2004 Sensoray Co., Inc.

  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; if not, write to the Free Software
  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

*/

/*
Driver: s626
Description: Sensoray 626 driver
Devices: [Sensoray] 626 (s626)
Authors: Gianluca Palli <gpalli@deis.unibo.it>,
Updated: Fri, 15 Feb 2008 10:28:42 +0000
Status: experimental

Configuration options:
  [0] - PCI bus of device (optional)
  [1] - PCI slot of device (optional)
  If bus/slot is not specified, the first supported
  PCI device found will be used.

INSN_CONFIG instructions:
  analog input:
   none

  analog output:
   none

  digital channel:
   s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
   supported configuration options:
   INSN_CONFIG_DIO_QUERY
   COMEDI_INPUT
   COMEDI_OUTPUT

  encoder:
   Every channel must be configured before reading.

   Example code

   insn.insn=INSN_CONFIG;   //configuration instruction
   insn.n=1;                //number of operation (must be 1)
   insn.data=&initialvalue; //initial value loaded into encoder
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				//during configuration
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   insn.subdev=5;           //encoder subdevice
   insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
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							//to configure
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   comedi_do_insn(cf,&insn); //executing configuration
*/

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#include <linux/interrupt.h>
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#include <linux/kernel.h>
#include <linux/types.h>

#include "../comedidev.h"

#include "comedi_fc.h"
#include "s626.h"

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#define PCI_VENDOR_ID_S626 0x1131
#define PCI_DEVICE_ID_S626 0x7146
#define PCI_SUBVENDOR_ID_S626 0x6000
#define PCI_SUBDEVICE_ID_S626 0x0272

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struct s626_board {
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	const char *name;
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	int vendor_id;
	int device_id;
	int subvendor_id;
	int subdevice_id;
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	int ai_chans;
	int ai_bits;
	int ao_chans;
	int ao_bits;
	int dio_chans;
	int dio_banks;
	int enc_chans;
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};
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static const struct s626_board s626_boards[] = {
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	{
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	 .name = "s626",
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	 .vendor_id = PCI_VENDOR_ID_S626,
	 .device_id = PCI_DEVICE_ID_S626,
	 .subvendor_id = PCI_SUBVENDOR_ID_S626,
	 .subdevice_id = PCI_SUBDEVICE_ID_S626,
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	 .ai_chans = S626_ADC_CHANNELS,
	 .ai_bits = 14,
	 .ao_chans = S626_DAC_CHANNELS,
	 .ao_bits = 13,
	 .dio_chans = S626_DIO_CHANNELS,
	 .dio_banks = S626_DIO_BANKS,
	 .enc_chans = S626_ENCODER_CHANNELS,
	 }
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};

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#define thisboard ((const struct s626_board *)dev->board_ptr)
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struct s626_private {
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	struct pci_dev *pdev;
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	void __iomem *base_addr;
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	int got_regions;
	short allocatedBuf;
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	uint8_t ai_cmd_running;	/*  ai_cmd is running */
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	uint8_t ai_continous;	/*  continous acquisition */
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	int ai_sample_count;	/*  number of samples to acquire */
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	unsigned int ai_sample_timer;
	/*  time between samples in  units of the timer */
	int ai_convert_count;	/*  conversion counter */
	unsigned int ai_convert_timer;
	/*  time between conversion in  units of the timer */
	uint16_t CounterIntEnabs;
	/* Counter interrupt enable  mask for MISC2 register. */
	uint8_t AdcItems;	/* Number of items in ADC poll  list. */
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	struct bufferDMA RPSBuf;	/* DMA buffer used to hold ADC (RPS1) program. */
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	struct bufferDMA ANABuf;
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	/* DMA buffer used to receive ADC data and hold DAC data. */
	uint32_t *pDacWBuf;
	/* Pointer to logical adrs of DMA buffer used to hold DAC  data. */
	uint16_t Dacpol;	/* Image of DAC polarity register. */
	uint8_t TrimSetpoint[12];	/* Images of TrimDAC setpoints */
	uint16_t ChargeEnabled;	/* Image of MISC2 Battery */
	/* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
	uint16_t WDInterval;	/* Image of MISC2 watchdog interval control bits. */
	uint32_t I2CAdrs;
	/* I2C device address for onboard EEPROM (board rev dependent). */
	/*   short         I2Cards; */
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	unsigned int ao_readback[S626_DAC_CHANNELS];
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};
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struct dio_private {
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	uint16_t RDDIn;
	uint16_t WRDOut;
	uint16_t RDEdgSel;
	uint16_t WREdgSel;
	uint16_t RDCapSel;
	uint16_t WRCapSel;
	uint16_t RDCapFlg;
	uint16_t RDIntSel;
	uint16_t WRIntSel;
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};
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static struct dio_private dio_private_A = {
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	.RDDIn = LP_RDDINA,
	.WRDOut = LP_WRDOUTA,
	.RDEdgSel = LP_RDEDGSELA,
	.WREdgSel = LP_WREDGSELA,
	.RDCapSel = LP_RDCAPSELA,
	.WRCapSel = LP_WRCAPSELA,
	.RDCapFlg = LP_RDCAPFLGA,
	.RDIntSel = LP_RDINTSELA,
	.WRIntSel = LP_WRINTSELA,
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};

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static struct dio_private dio_private_B = {
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	.RDDIn = LP_RDDINB,
	.WRDOut = LP_WRDOUTB,
	.RDEdgSel = LP_RDEDGSELB,
	.WREdgSel = LP_WREDGSELB,
	.RDCapSel = LP_RDCAPSELB,
	.WRCapSel = LP_WRCAPSELB,
	.RDCapFlg = LP_RDCAPFLGB,
	.RDIntSel = LP_RDINTSELB,
	.WRIntSel = LP_WRINTSELB,
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};

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static struct dio_private dio_private_C = {
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	.RDDIn = LP_RDDINC,
	.WRDOut = LP_WRDOUTC,
	.RDEdgSel = LP_RDEDGSELC,
	.WREdgSel = LP_WREDGSELC,
	.RDCapSel = LP_RDCAPSELC,
	.WRCapSel = LP_WRCAPSELC,
	.RDCapFlg = LP_RDCAPFLGC,
	.RDIntSel = LP_RDINTSELC,
	.WRIntSel = LP_WRINTSELC,
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};

/* to group dio devices (48 bits mask and data are not allowed ???)
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static struct dio_private *dio_private_word[]={
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  &dio_private_A,
  &dio_private_B,
  &dio_private_C,
};
*/

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#define devpriv ((struct s626_private *)dev->private)
#define diopriv ((struct dio_private *)s->private)
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static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan);
static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int gruop,
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			      unsigned int mask);
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static int s626_dio_clear_irq(struct comedi_device *dev);
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static int s626_ns_to_timer(int *nanosec, int round_mode);

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/* internal routines */
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static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
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			 uint8_t DacData);
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static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr);
static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val);
static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata);
static void SendDAC(struct comedi_device *dev, uint32_t val);
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/*  COUNTER OBJECT ------------------------------------------------ */
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struct enc_private {
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	/*  Pointers to functions that differ for A and B counters: */
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	uint16_t(*GetEnable) (struct comedi_device *dev, struct enc_private *);	/* Return clock enable. */
	uint16_t(*GetIntSrc) (struct comedi_device *dev, struct enc_private *);	/* Return interrupt source. */
	uint16_t(*GetLoadTrig) (struct comedi_device *dev, struct enc_private *);	/* Return preload trigger source. */
	uint16_t(*GetMode) (struct comedi_device *dev, struct enc_private *);	/* Return standardized operating mode. */
	void (*PulseIndex) (struct comedi_device *dev, struct enc_private *);	/* Generate soft index strobe. */
	void (*SetEnable) (struct comedi_device *dev, struct enc_private *, uint16_t enab);	/* Program clock enable. */
	void (*SetIntSrc) (struct comedi_device *dev, struct enc_private *, uint16_t IntSource);	/* Program interrupt source. */
	void (*SetLoadTrig) (struct comedi_device *dev, struct enc_private *, uint16_t Trig);	/* Program preload trigger source. */
	void (*SetMode) (struct comedi_device *dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc);	/* Program standardized operating mode. */
	void (*ResetCapFlags) (struct comedi_device *dev, struct enc_private *);	/* Reset event capture flags. */
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	uint16_t MyCRA;		/*    Address of CRA register. */
	uint16_t MyCRB;		/*    Address of CRB register. */
	uint16_t MyLatchLsw;	/*    Address of Latch least-significant-word */
	/*    register. */
	uint16_t MyEventBits[4];	/*    Bit translations for IntSrc -->RDMISC2. */
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};
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#define encpriv ((struct enc_private *)(dev->subdevices+5)->private)
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static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
			    int tick);
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static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k);
static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k);
static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k);
static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k);
static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k);
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static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
		      uint16_t Setup, uint16_t DisableIntSrc);
static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
		      uint16_t Setup, uint16_t DisableIntSrc);
static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
			uint16_t enab);
static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
			uint16_t enab);
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static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k);
static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k);
static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
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			   uint16_t value);
static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
			  uint16_t Trig);
static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
			  uint16_t Trig);
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static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k);
static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k);
static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
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			uint16_t IntSource);
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static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
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			uint16_t IntSource);
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static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k);
static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k);
static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k);
static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k);
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static void Preload(struct comedi_device *dev, struct enc_private *k,
		    uint32_t value);
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/*  Counter objects constructor. */
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/*  Counter overflow/index event flag masks for RDMISC2. */
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#define INDXMASK(C)		(1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 +  4)))
#define OVERMASK(C)		(1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
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#define EVBITS(C)		{ 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }

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/*  Translation table to map IntSrc into equivalent RDMISC2 event flag  bits. */
/* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
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/* struct enc_private; */
static struct enc_private enc_private_data[] = {
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	{
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	 .GetEnable = GetEnable_A,
	 .GetIntSrc = GetIntSrc_A,
	 .GetLoadTrig = GetLoadTrig_A,
	 .GetMode = GetMode_A,
	 .PulseIndex = PulseIndex_A,
	 .SetEnable = SetEnable_A,
	 .SetIntSrc = SetIntSrc_A,
	 .SetLoadTrig = SetLoadTrig_A,
	 .SetMode = SetMode_A,
	 .ResetCapFlags = ResetCapFlags_A,
	 .MyCRA = LP_CR0A,
	 .MyCRB = LP_CR0B,
	 .MyLatchLsw = LP_CNTR0ALSW,
	 .MyEventBits = EVBITS(0),
	 },
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	{
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	 .GetEnable = GetEnable_A,
	 .GetIntSrc = GetIntSrc_A,
	 .GetLoadTrig = GetLoadTrig_A,
	 .GetMode = GetMode_A,
	 .PulseIndex = PulseIndex_A,
	 .SetEnable = SetEnable_A,
	 .SetIntSrc = SetIntSrc_A,
	 .SetLoadTrig = SetLoadTrig_A,
	 .SetMode = SetMode_A,
	 .ResetCapFlags = ResetCapFlags_A,
	 .MyCRA = LP_CR1A,
	 .MyCRB = LP_CR1B,
	 .MyLatchLsw = LP_CNTR1ALSW,
	 .MyEventBits = EVBITS(1),
	 },
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	{
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	 .GetEnable = GetEnable_A,
	 .GetIntSrc = GetIntSrc_A,
	 .GetLoadTrig = GetLoadTrig_A,
	 .GetMode = GetMode_A,
	 .PulseIndex = PulseIndex_A,
	 .SetEnable = SetEnable_A,
	 .SetIntSrc = SetIntSrc_A,
	 .SetLoadTrig = SetLoadTrig_A,
	 .SetMode = SetMode_A,
	 .ResetCapFlags = ResetCapFlags_A,
	 .MyCRA = LP_CR2A,
	 .MyCRB = LP_CR2B,
	 .MyLatchLsw = LP_CNTR2ALSW,
	 .MyEventBits = EVBITS(2),
	 },
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	{
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	 .GetEnable = GetEnable_B,
	 .GetIntSrc = GetIntSrc_B,
	 .GetLoadTrig = GetLoadTrig_B,
	 .GetMode = GetMode_B,
	 .PulseIndex = PulseIndex_B,
	 .SetEnable = SetEnable_B,
	 .SetIntSrc = SetIntSrc_B,
	 .SetLoadTrig = SetLoadTrig_B,
	 .SetMode = SetMode_B,
	 .ResetCapFlags = ResetCapFlags_B,
	 .MyCRA = LP_CR0A,
	 .MyCRB = LP_CR0B,
	 .MyLatchLsw = LP_CNTR0BLSW,
	 .MyEventBits = EVBITS(3),
	 },
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	{
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	 .GetEnable = GetEnable_B,
	 .GetIntSrc = GetIntSrc_B,
	 .GetLoadTrig = GetLoadTrig_B,
	 .GetMode = GetMode_B,
	 .PulseIndex = PulseIndex_B,
	 .SetEnable = SetEnable_B,
	 .SetIntSrc = SetIntSrc_B,
	 .SetLoadTrig = SetLoadTrig_B,
	 .SetMode = SetMode_B,
	 .ResetCapFlags = ResetCapFlags_B,
	 .MyCRA = LP_CR1A,
	 .MyCRB = LP_CR1B,
	 .MyLatchLsw = LP_CNTR1BLSW,
	 .MyEventBits = EVBITS(4),
	 },
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	{
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	 .GetEnable = GetEnable_B,
	 .GetIntSrc = GetIntSrc_B,
	 .GetLoadTrig = GetLoadTrig_B,
	 .GetMode = GetMode_B,
	 .PulseIndex = PulseIndex_B,
	 .SetEnable = SetEnable_B,
	 .SetIntSrc = SetIntSrc_B,
	 .SetLoadTrig = SetLoadTrig_B,
	 .SetMode = SetMode_B,
	 .ResetCapFlags = ResetCapFlags_B,
	 .MyCRA = LP_CR2A,
	 .MyCRB = LP_CR2B,
	 .MyLatchLsw = LP_CNTR2BLSW,
	 .MyEventBits = EVBITS(5),
	 },
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};

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/*  enab/disable a function or test status bit(s) that are accessed */
/*  through Main Control Registers 1 or 2. */
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#define MC_ENABLE(REGADRS, CTRLWORD)	writel(((uint32_t)(CTRLWORD) << 16) | (uint32_t)(CTRLWORD), devpriv->base_addr+(REGADRS))
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#define MC_DISABLE(REGADRS, CTRLWORD)	writel((uint32_t)(CTRLWORD) << 16 , devpriv->base_addr+(REGADRS))
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#define MC_TEST(REGADRS, CTRLWORD)	((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0)
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/* #define WR7146(REGARDS,CTRLWORD)
    writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
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#define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
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/* #define RR7146(REGARDS)
    readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
#define RR7146(REGARDS)		readl(devpriv->base_addr+(REGARDS))

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#define BUGFIX_STREG(REGADRS)   (REGADRS - 4)
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/*  Write a time slot control record to TSL2. */
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#define VECTPORT(VECTNUM)		(P_TSL2 + ((VECTNUM) << 2))
#define SETVECT(VECTNUM, VECTVAL)	WR7146(VECTPORT(VECTNUM), (VECTVAL))
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/*  Code macros used for constructing I2C command bytes. */
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#define I2C_B2(ATTR, VAL)	(((ATTR) << 6) | ((VAL) << 24))
#define I2C_B1(ATTR, VAL)	(((ATTR) << 4) | ((VAL) << 16))
#define I2C_B0(ATTR, VAL)	(((ATTR) << 2) | ((VAL) <<  8))
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static const struct comedi_lrange s626_range_table = { 2, {
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							   RANGE(-5, 5),
							   RANGE(-10, 10),
							   }
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};

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/*  Execute a DEBI transfer.  This must be called from within a */
/*  critical section. */
static void DEBItransfer(struct comedi_device *dev)
{
	/*  Initiate upload of shadow RAM to DEBI control register. */
	MC_ENABLE(P_MC2, MC2_UPLD_DEBI);

	/*  Wait for completion of upload from shadow RAM to DEBI control */
	/*  register. */
	while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
		;

	/*  Wait until DEBI transfer is done. */
	while (RR7146(P_PSR) & PSR_DEBI_S)
		;
}

/*  Initialize the DEBI interface for all transfers. */

static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
{
	uint16_t retval;

	/*  Set up DEBI control register value in shadow RAM. */
	WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);

	/*  Execute the DEBI transfer. */
	DEBItransfer(dev);

	/*  Fetch target register value. */
	retval = (uint16_t) RR7146(P_DEBIAD);

	/*  Return register value. */
	return retval;
}

/*  Write a value to a gate array register. */
static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
{

	/*  Set up DEBI control register value in shadow RAM. */
	WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
	WR7146(P_DEBIAD, wdata);

	/*  Execute the DEBI transfer. */
	DEBItransfer(dev);
}

/* Replace the specified bits in a gate array register.  Imports: mask
 * specifies bits that are to be preserved, wdata is new value to be
 * or'd with the masked original.
 */
static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
			uint16_t wdata)
{

	/*  Copy target gate array register into P_DEBIAD register. */
	WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
	/* Set up DEBI control reg value in shadow RAM. */
	DEBItransfer(dev);	/*  Execute the DEBI Read transfer. */

	/*  Write back the modified image. */
	WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
	/* Set up DEBI control reg value in shadow  RAM. */

	WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask));
	/* Modify the register image. */
	DEBItransfer(dev);	/*  Execute the DEBI Write transfer. */
}

496
static unsigned int s626_ai_reg_to_uint(int data)
497
{
498
	unsigned int tempdata;
499

500
501
502
503
504
	tempdata = (data >> 18);
	if (tempdata & 0x2000)
		tempdata &= 0x1fff;
	else
		tempdata += (1 << 13);
505

506
507
	return tempdata;
}
508

509
510
511
/* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data){ */
/*   return 0; */
/* } */
512

513
514
515
516
517
518
519
520
521
522
523
524
525
static irqreturn_t s626_irq_handler(int irq, void *d)
{
	struct comedi_device *dev = d;
	struct comedi_subdevice *s;
	struct comedi_cmd *cmd;
	struct enc_private *k;
	unsigned long flags;
	int32_t *readaddr;
	uint32_t irqtype, irqstatus;
	int i = 0;
	short tempdata;
	uint8_t group;
	uint16_t irqbit;
526

527
	DEBUG("s626_irq_handler: interrupt request received!!!\n");
528

529
530
531
532
	if (dev->attached == 0)
		return IRQ_NONE;
	/*  lock to avoid race with comedi_poll */
	spin_lock_irqsave(&dev->spinlock, flags);
533

534
535
	/* save interrupt enable register state */
	irqstatus = readl(devpriv->base_addr + P_IER);
536

537
538
	/* read interrupt type */
	irqtype = readl(devpriv->base_addr + P_ISR);
539

540
541
	/* disable master interrupt */
	writel(0, devpriv->base_addr + P_IER);
542

543
544
	/* clear interrupt */
	writel(irqtype, devpriv->base_addr + P_ISR);
545

546
547
	/* do somethings */
	DEBUG("s626_irq_handler: interrupt type %d\n", irqtype);
548

549
550
	switch (irqtype) {
	case IRQ_RPS1:		/*  end_of_scan occurs */
551

552
		DEBUG("s626_irq_handler: RPS1 irq detected\n");
553

554
555
556
		/*  manage ai subdevice */
		s = dev->subdevices;
		cmd = &(s->async->cmd);
557

558
559
560
561
562
		/* Init ptr to DMA buffer that holds new ADC data.  We skip the
		 * first uint16_t in the buffer because it contains junk data from
		 * the final ADC of the previous poll list scan.
		 */
		readaddr = (int32_t *) devpriv->ANABuf.LogicalBase + 1;
563

564
565
566
567
568
569
		/*  get the data and hand it over to comedi */
		for (i = 0; i < (s->async->cmd.chanlist_len); i++) {
			/*  Convert ADC data to 16-bit integer values and copy to application */
			/*  buffer. */
			tempdata = s626_ai_reg_to_uint((int)*readaddr);
			readaddr++;
570

571
572
573
574
575
			/* put data into read buffer */
			/*  comedi_buf_put(s->async, tempdata); */
			if (cfc_write_to_buffer(s, tempdata) == 0)
				printk
				    ("s626_irq_handler: cfc_write_to_buffer error!\n");
576

577
578
			DEBUG("s626_irq_handler: ai channel %d acquired: %d\n",
			      i, tempdata);
579
580
		}

581
582
		/* end of scan occurs */
		s->async->events |= COMEDI_CB_EOS;
583

584
585
586
587
		if (!(devpriv->ai_continous))
			devpriv->ai_sample_count--;
		if (devpriv->ai_sample_count <= 0) {
			devpriv->ai_cmd_running = 0;
588

589
590
			/*  Stop RPS program. */
			MC_DISABLE(P_MC1, MC1_ERPS1);
591

592
593
			/* send end of acquisition */
			s->async->events |= COMEDI_CB_EOA;
594

595
596
597
			/* disable master interrupt */
			irqstatus = 0;
		}
598

599
600
601
602
		if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) {
			DEBUG
			    ("s626_irq_handler: enable interrupt on dio channel %d\n",
			     cmd->scan_begin_arg);
603

604
			s626_dio_set_irq(dev, cmd->scan_begin_arg);
605

606
			DEBUG("s626_irq_handler: External trigger is set!!!\n");
607
		}
608
609
610
611
612
		/*  tell comedi that data is there */
		DEBUG("s626_irq_handler: events %d\n", s->async->events);
		comedi_event(dev, s);
		break;
	case IRQ_GPIO3:	/* check dio and conter interrupt */
613

614
		DEBUG("s626_irq_handler: GPIO3 irq detected\n");
615

616
617
618
		/*  manage ai subdevice */
		s = dev->subdevices;
		cmd = &(s->async->cmd);
619

620
		/* s626_dio_clear_irq(dev); */
621

622
623
624
625
626
627
628
629
630
		for (group = 0; group < S626_DIO_BANKS; group++) {
			irqbit = 0;
			/* read interrupt type */
			irqbit = DEBIread(dev,
					  ((struct dio_private *)(dev->
								  subdevices +
								  2 +
								  group)->
					   private)->RDCapFlg);
631

632
633
634
635
636
637
638
639
640
641
642
643
644
645
			/* check if interrupt is generated from dio channels */
			if (irqbit) {
				s626_dio_reset_irq(dev, group, irqbit);
				DEBUG
				    ("s626_irq_handler: check interrupt on dio group %d %d\n",
				     group, i);
				if (devpriv->ai_cmd_running) {
					/* check if interrupt is an ai acquisition start trigger */
					if ((irqbit >> (cmd->start_arg -
							(16 * group)))
					    == 1 && cmd->start_src == TRIG_EXT) {
						DEBUG
						    ("s626_irq_handler: Edge capture interrupt received from channel %d\n",
						     cmd->start_arg);
646

647
648
						/*  Start executing the RPS program. */
						MC_ENABLE(P_MC1, MC1_ERPS1);
649

650
651
						DEBUG
						    ("s626_irq_handler: acquisition start triggered!!!\n");
652

653
654
655
656
657
658
						if (cmd->scan_begin_src ==
						    TRIG_EXT) {
							DEBUG
							    ("s626_ai_cmd: enable interrupt on dio channel %d\n",
							     cmd->
							     scan_begin_arg);
659

660
661
							s626_dio_set_irq(dev,
									 cmd->scan_begin_arg);
662

663
664
665
666
667
668
669
670
671
672
673
674
							DEBUG
							    ("s626_irq_handler: External scan trigger is set!!!\n");
						}
					}
					if ((irqbit >> (cmd->scan_begin_arg -
							(16 * group)))
					    == 1
					    && cmd->scan_begin_src ==
					    TRIG_EXT) {
						DEBUG
						    ("s626_irq_handler: Edge capture interrupt received from channel %d\n",
						     cmd->scan_begin_arg);
675

676
677
						/*  Trigger ADC scan loop start by setting RPS Signal 0. */
						MC_ENABLE(P_MC2, MC2_ADC_RPS);
678

679
680
681
682
683
						DEBUG
						    ("s626_irq_handler: scan triggered!!! %d\n",
						     devpriv->ai_sample_count);
						if (cmd->convert_src ==
						    TRIG_EXT) {
684

685
686
687
688
689
							DEBUG
							    ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n",
							     cmd->convert_arg -
							     (16 * group),
							     group);
690

691
692
							devpriv->ai_convert_count
							    = cmd->chanlist_len;
693

694
695
							s626_dio_set_irq(dev,
									 cmd->convert_arg);
696

697
698
699
							DEBUG
							    ("s626_irq_handler: External convert trigger is set!!!\n");
						}
700

701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
						if (cmd->convert_src ==
						    TRIG_TIMER) {
							k = &encpriv[5];
							devpriv->ai_convert_count
							    = cmd->chanlist_len;
							k->SetEnable(dev, k,
								     CLKENAB_ALWAYS);
						}
					}
					if ((irqbit >> (cmd->convert_arg -
							(16 * group)))
					    == 1
					    && cmd->convert_src == TRIG_EXT) {
						DEBUG
						    ("s626_irq_handler: Edge capture interrupt received from channel %d\n",
						     cmd->convert_arg);
717

718
719
						/*  Trigger ADC scan loop start by setting RPS Signal 0. */
						MC_ENABLE(P_MC2, MC2_ADC_RPS);
720

721
722
						DEBUG
						    ("s626_irq_handler: adc convert triggered!!!\n");
723

724
						devpriv->ai_convert_count--;
725

726
727
						if (devpriv->ai_convert_count >
						    0) {
728

729
730
731
732
733
							DEBUG
							    ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n",
							     cmd->convert_arg -
							     (16 * group),
							     group);
734

735
736
							s626_dio_set_irq(dev,
									 cmd->convert_arg);
737

738
739
740
741
742
743
744
745
							DEBUG
							    ("s626_irq_handler: External trigger is set!!!\n");
						}
					}
				}
				break;
			}
		}
746

747
748
		/* read interrupt type */
		irqbit = DEBIread(dev, LP_RDMISC2);
749

750
751
752
		/* check interrupt on counters */
		DEBUG("s626_irq_handler: check counters interrupt %d\n",
		      irqbit);
753

754
755
756
757
		if (irqbit & IRQ_COINT1A) {
			DEBUG
			    ("s626_irq_handler: interrupt on counter 1A overflow\n");
			k = &encpriv[0];
758

759
760
761
762
763
764
765
			/* clear interrupt capture flag */
			k->ResetCapFlags(dev, k);
		}
		if (irqbit & IRQ_COINT2A) {
			DEBUG
			    ("s626_irq_handler: interrupt on counter 2A overflow\n");
			k = &encpriv[1];
766

767
768
769
770
771
772
773
			/* clear interrupt capture flag */
			k->ResetCapFlags(dev, k);
		}
		if (irqbit & IRQ_COINT3A) {
			DEBUG
			    ("s626_irq_handler: interrupt on counter 3A overflow\n");
			k = &encpriv[2];
774

775
776
777
778
779
780
781
			/* clear interrupt capture flag */
			k->ResetCapFlags(dev, k);
		}
		if (irqbit & IRQ_COINT1B) {
			DEBUG
			    ("s626_irq_handler: interrupt on counter 1B overflow\n");
			k = &encpriv[3];
782

783
784
785
786
787
788
789
			/* clear interrupt capture flag */
			k->ResetCapFlags(dev, k);
		}
		if (irqbit & IRQ_COINT2B) {
			DEBUG
			    ("s626_irq_handler: interrupt on counter 2B overflow\n");
			k = &encpriv[4];
790

791
792
			/* clear interrupt capture flag */
			k->ResetCapFlags(dev, k);
793

794
795
796
797
			if (devpriv->ai_convert_count > 0) {
				devpriv->ai_convert_count--;
				if (devpriv->ai_convert_count == 0)
					k->SetEnable(dev, k, CLKENAB_INDEX);
798

799
800
801
802
				if (cmd->convert_src == TRIG_TIMER) {
					DEBUG
					    ("s626_irq_handler: conver timer trigger!!! %d\n",
					     devpriv->ai_convert_count);
803

804
805
806
807
808
809
810
811
812
					/*  Trigger ADC scan loop start by setting RPS Signal 0. */
					MC_ENABLE(P_MC2, MC2_ADC_RPS);
				}
			}
		}
		if (irqbit & IRQ_COINT3B) {
			DEBUG
			    ("s626_irq_handler: interrupt on counter 3B overflow\n");
			k = &encpriv[5];
813

814
815
			/* clear interrupt capture flag */
			k->ResetCapFlags(dev, k);
816

817
818
819
			if (cmd->scan_begin_src == TRIG_TIMER) {
				DEBUG
				    ("s626_irq_handler: scan timer trigger!!!\n");
820

821
822
823
				/*  Trigger ADC scan loop start by setting RPS Signal 0. */
				MC_ENABLE(P_MC2, MC2_ADC_RPS);
			}
824

825
826
827
828
829
830
831
832
833
			if (cmd->convert_src == TRIG_TIMER) {
				DEBUG
				    ("s626_irq_handler: convert timer trigger is set\n");
				k = &encpriv[4];
				devpriv->ai_convert_count = cmd->chanlist_len;
				k->SetEnable(dev, k, CLKENAB_ALWAYS);
			}
		}
	}
834

835
836
	/* enable interrupt */
	writel(irqstatus, devpriv->base_addr + P_IER);
837

838
	DEBUG("s626_irq_handler: exit interrupt service routine.\n");
839

840
841
842
	spin_unlock_irqrestore(&dev->spinlock, flags);
	return IRQ_HANDLED;
}
843

844
845
846
847
848
849
850
851
852
853
854
/*
 * this functions build the RPS program for hardware driven acquistion
 */
static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
{
	register uint32_t *pRPS;
	uint32_t JmpAdrs;
	uint16_t i;
	uint16_t n;
	uint32_t LocalPPL;
	struct comedi_cmd *cmd = &(dev->subdevices->async->cmd);
855

856
857
	/*  Stop RPS program in case it is currently running. */
	MC_DISABLE(P_MC1, MC1_ERPS1);
858

859
860
	/*  Set starting logical address to write RPS commands. */
	pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
861

862
863
	/*  Initialize RPS instruction pointer. */
	WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
864

865
	/*  Construct RPS program in RPSBuf DMA buffer */
866

867
868
869
870
871
872
	if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
		DEBUG("ResetADC: scan_begin pause inserted\n");
		/*  Wait for Start trigger. */
		*pRPS++ = RPS_PAUSE | RPS_SIGADC;
		*pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
	}
873

874
875
876
877
878
879
880
881
882
	/* SAA7146 BUG WORKAROUND Do a dummy DEBI Write.  This is necessary
	 * because the first RPS DEBI Write following a non-RPS DEBI write
	 * seems to always fail.  If we don't do this dummy write, the ADC
	 * gain might not be set to the value required for the first slot in
	 * the poll list; the ADC gain would instead remain unchanged from
	 * the previously programmed value.
	 */
	*pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
	/* Write DEBI Write command and address to shadow RAM. */
883

884
885
886
	*pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
	*pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
	/*  Write DEBI immediate data  to shadow RAM: */
887

888
889
	*pRPS++ = GSEL_BIPOLAR5V;
	/*  arbitrary immediate data  value. */
890

891
892
893
894
	*pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
	/*  Reset "shadow RAM  uploaded" flag. */
	*pRPS++ = RPS_UPLOAD | RPS_DEBI;	/*  Invoke shadow RAM upload. */
	*pRPS++ = RPS_PAUSE | RPS_DEBI;	/*  Wait for shadow upload to finish. */
895

896
897
898
899
900
901
902
903
904
	/* Digitize all slots in the poll list. This is implemented as a
	 * for loop to limit the slot count to 16 in case the application
	 * forgot to set the EOPL flag in the final slot.
	 */
	for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
		/* Convert application's poll list item to private board class
		 * format.  Each app poll list item is an uint8_t with form
		 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
		 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
905
		 */
906
907
908
		LocalPPL =
		    (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
				   GSEL_BIPOLAR10V);
909

910
911
912
913
914
915
916
917
918
919
920
921
922
923
		/*  Switch ADC analog gain. */
		*pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);	/*  Write DEBI command */
		/*  and address to */
		/*  shadow RAM. */
		*pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
		*pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);	/*  Write DEBI */
		/*  immediate data to */
		/*  shadow RAM. */
		*pRPS++ = LocalPPL;
		*pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;	/*  Reset "shadow RAM uploaded" */
		/*  flag. */
		*pRPS++ = RPS_UPLOAD | RPS_DEBI;	/*  Invoke shadow RAM upload. */
		*pRPS++ = RPS_PAUSE | RPS_DEBI;	/*  Wait for shadow upload to */
		/*  finish. */
924

925
926
927
928
929
930
931
932
933
		/*  Select ADC analog input channel. */
		*pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
		/*  Write DEBI command and address to  shadow RAM. */
		*pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
		*pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
		/*  Write DEBI immediate data to shadow RAM. */
		*pRPS++ = LocalPPL;
		*pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
		/*  Reset "shadow RAM uploaded"  flag. */
934

935
936
		*pRPS++ = RPS_UPLOAD | RPS_DEBI;
		/*  Invoke shadow RAM upload. */
937

938
939
		*pRPS++ = RPS_PAUSE | RPS_DEBI;
		/*  Wait for shadow upload to finish. */
940

941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
		/* Delay at least 10 microseconds for analog input settling.
		 * Instead of padding with NOPs, we use RPS_JUMP instructions
		 * here; this allows us to produce a longer delay than is
		 * possible with NOPs because each RPS_JUMP flushes the RPS'
		 * instruction prefetch pipeline.
		 */
		JmpAdrs =
		    (uint32_t) devpriv->RPSBuf.PhysicalBase +
		    (uint32_t) ((unsigned long)pRPS -
				(unsigned long)devpriv->RPSBuf.LogicalBase);
		for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
			JmpAdrs += 8;	/*  Repeat to implement time delay: */
			*pRPS++ = RPS_JUMP;	/*  Jump to next RPS instruction. */
			*pRPS++ = JmpAdrs;
		}
956

957
958
959
960
961
962
963
964
965
966
967
968
969
		if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
			DEBUG("ResetADC: convert pause inserted\n");
			/*  Wait for Start trigger. */
			*pRPS++ = RPS_PAUSE | RPS_SIGADC;
			*pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
		}
		/*  Start ADC by pulsing GPIO1. */
		*pRPS++ = RPS_LDREG | (P_GPIO >> 2);	/*  Begin ADC Start pulse. */
		*pRPS++ = GPIO_BASE | GPIO1_LO;
		*pRPS++ = RPS_NOP;
		/*  VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
		*pRPS++ = RPS_LDREG | (P_GPIO >> 2);	/*  End ADC Start pulse. */
		*pRPS++ = GPIO_BASE | GPIO1_HI;
970

971
972
973
974
975
		/* Wait for ADC to complete (GPIO2 is asserted high when ADC not
		 * busy) and for data from previous conversion to shift into FB
		 * BUFFER 1 register.
		 */
		*pRPS++ = RPS_PAUSE | RPS_GPIO2;	/*  Wait for ADC done. */
976

977
978
979
980
981
		/*  Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
		*pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
		*pRPS++ =
		    (uint32_t) devpriv->ANABuf.PhysicalBase +
		    (devpriv->AdcItems << 2);
982

983
984
985
986
987
988
989
990
		/*  If this slot's EndOfPollList flag is set, all channels have */
		/*  now been processed. */
		if (*ppl++ & EOPL) {
			devpriv->AdcItems++;	/*  Adjust poll list item count. */
			break;	/*  Exit poll list processing loop. */
		}
	}
	DEBUG("ResetADC: ADC items %d\n", devpriv->AdcItems);
991

992
993
994
995
996
997
998
999
1000
	/* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US.  Allow the
	 * ADC to stabilize for 2 microseconds before starting the final
	 * (dummy) conversion.  This delay is necessary to allow sufficient
	 * time between last conversion finished and the start of the dummy
	 * conversion.  Without this delay, the last conversion's data value
	 * is sometimes set to the previous conversion's data value.
	 */
	for (n = 0; n < (2 * RPSCLK_PER_US); n++)
		*pRPS++ = RPS_NOP;
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