fsl_msi.c 8.46 KB
Newer Older
1
/*
2
 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
 *
 * Author: Tony Li <tony.li@freescale.com>
 *	   Jason Jin <Jason.jin@freescale.com>
 *
 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2 of the
 * License.
 *
 */
#include <linux/irq.h>
#include <linux/bootmem.h>
#include <linux/msi.h>
#include <linux/pci.h>
19
#include <linux/slab.h>
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#include <asm/prom.h>
#include <asm/hw_irq.h>
#include <asm/ppc-pci.h>
#include "fsl_msi.h"

struct fsl_msi_feature {
	u32 fsl_pic_ip;
	u32 msiir_offset;
};


static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
{
	return in_be32(base + (reg >> 2));
}

/*
 * We do not need this actually. The MSIR register has been read once
 * in the cascade interrupt. So, this MSI interrupt has been acked
*/
static void fsl_msi_end_irq(unsigned int virq)
{
}

static struct irq_chip fsl_msi_chip = {
	.mask		= mask_msi_irq,
	.unmask		= unmask_msi_irq,
	.ack		= fsl_msi_end_irq,
50
	.name		= "FSL-MSI",
51
52
53
54
55
};

static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
				irq_hw_number_t hw)
{
56
	struct fsl_msi *msi_data = h->host_data;
57
58
	struct irq_chip *chip = &fsl_msi_chip;

59
	irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
60

61
	set_irq_chip_data(virq, msi_data);
62
	set_irq_chip_and_handler(virq, chip, handle_edge_irq);
63
64
65
66
67
68
69
70
71
72

	return 0;
}

static struct irq_host_ops fsl_msi_host_ops = {
	.map = fsl_msi_host_map,
};

static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
{
73
	int rc;
74

75
76
77
78
	rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
			      msi_data->irqhost->of_node);
	if (rc)
		return rc;
79

80
81
82
83
	rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
	if (rc < 0) {
		msi_bitmap_free(&msi_data->bitmap);
		return rc;
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
	}

	return 0;
}

static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
{
	if (type == PCI_CAP_ID_MSIX)
		pr_debug("fslmsi: MSI-X untested, trying anyway.\n");

	return 0;
}

static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
{
	struct msi_desc *entry;
100
	struct fsl_msi *msi_data;
101
102
103
104

	list_for_each_entry(entry, &pdev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;
105
		msi_data = get_irq_chip_data(entry->irq);
106
		set_irq_msi(entry->irq, NULL);
107
108
		msi_bitmap_free_hwirqs(&msi_data->bitmap,
				       virq_to_hw(entry->irq), 1);
109
110
111
112
113
114
115
		irq_dispose_mapping(entry->irq);
	}

	return;
}

static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
116
117
				struct msi_msg *msg,
				struct fsl_msi *fsl_msi_data)
118
{
119
	struct fsl_msi *msi_data = fsl_msi_data;
120
121
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	u32 base = 0;
122

123
124
125
126
	pci_bus_read_config_dword(hose->bus,
		PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);

	msg->address_lo = msi_data->msi_addr_lo + base;
127
128
129
130
131
132
133
134
135
	msg->address_hi = msi_data->msi_addr_hi;
	msg->data = hwirq;

	pr_debug("%s: allocated srs: %d, ibs: %d\n",
		__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
}

static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
{
136
	int rc, hwirq;
137
138
139
	unsigned int virq;
	struct msi_desc *entry;
	struct msi_msg msg;
140
	struct fsl_msi *msi_data;
141
142

	list_for_each_entry(entry, &pdev->msi_list, list) {
143
144
		msi_data = get_irq_chip_data(entry->irq);

145
		hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
146
147
148
149
150
151
152
153
154
155
		if (hwirq < 0) {
			rc = hwirq;
			pr_debug("%s: fail allocating msi interrupt\n",
					__func__);
			goto out_free;
		}

		virq = irq_create_mapping(msi_data->irqhost, hwirq);

		if (virq == NO_IRQ) {
156
			pr_debug("%s: fail mapping hwirq 0x%x\n",
157
					__func__, hwirq);
158
			msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
159
160
161
162
163
			rc = -ENOSPC;
			goto out_free;
		}
		set_irq_msi(virq, entry);

164
		fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
165
166
167
168
169
170
171
172
		write_msi_msg(virq, &msg);
	}
	return 0;

out_free:
	return rc;
}

173
static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
174
175
{
	unsigned int cascade_irq;
176
	struct fsl_msi *msi_data = get_irq_chip_data(irq);
177
178
179
180
181
	int msir_index = -1;
	u32 msir_value = 0;
	u32 intr_index;
	u32 have_shift = 0;

182
	raw_spin_lock(&desc->lock);
183
184
185
186
187
188
189
190
191
192
193
194
	if ((msi_data->feature &  FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
		if (desc->chip->mask_ack)
			desc->chip->mask_ack(irq);
		else {
			desc->chip->mask(irq);
			desc->chip->ack(irq);
		}
	}

	if (unlikely(desc->status & IRQ_INPROGRESS))
		goto unlock;

195
	msir_index = (int)desc->handler_data;
196
197
198
199
200

	if (msir_index >= NR_MSI_REG)
		cascade_irq = NO_IRQ;

	desc->status |= IRQ_INPROGRESS;
201
	switch (msi_data->feature & FSL_PIC_IP_MASK) {
202
203
204
205
206
207
208
209
210
211
212
213
214
	case FSL_PIC_IP_MPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs,
			msir_index * 0x10);
		break;
	case FSL_PIC_IP_IPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
		break;
	}

	while (msir_value) {
		intr_index = ffs(msir_value) - 1;

		cascade_irq = irq_linear_revmap(msi_data->irqhost,
215
216
				msir_index * IRQS_PER_MSI_REG +
					intr_index + have_shift);
217
218
		if (cascade_irq != NO_IRQ)
			generic_handle_irq(cascade_irq);
219
220
		have_shift += intr_index + 1;
		msir_value = msir_value >> (intr_index + 1);
221
222
223
224
225
226
227
228
229
230
231
232
233
	}
	desc->status &= ~IRQ_INPROGRESS;

	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	case FSL_PIC_IP_MPIC:
		desc->chip->eoi(irq);
		break;
	case FSL_PIC_IP_IPIC:
		if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
			desc->chip->unmask(irq);
		break;
	}
unlock:
234
	raw_spin_unlock(&desc->lock);
235
236
237
238
239
240
241
242
243
244
245
}

static int __devinit fsl_of_msi_probe(struct of_device *dev,
				const struct of_device_id *match)
{
	struct fsl_msi *msi;
	struct resource res;
	int err, i, count;
	int rc;
	int virt_msir;
	const u32 *p;
246
	struct fsl_msi_feature *features = match->data;
247
248
249
250
251
252
253
254
255
256

	printk(KERN_DEBUG "Setting up Freescale MSI support\n");

	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
	if (!msi) {
		dev_err(&dev->dev, "No memory for MSI structure\n");
		err = -ENOMEM;
		goto error_out;
	}

257
258
	msi->irqhost = irq_alloc_host(dev->node, IRQ_HOST_MAP_LINEAR,
				      NR_MSI_IRQS, &fsl_msi_host_ops, 0);
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279

	if (msi->irqhost == NULL) {
		dev_err(&dev->dev, "No memory for MSI irqhost\n");
		err = -ENOMEM;
		goto error_out;
	}

	/* Get the MSI reg base */
	err = of_address_to_resource(dev->node, 0, &res);
	if (err) {
		dev_err(&dev->dev, "%s resource error!\n",
				dev->node->full_name);
		goto error_out;
	}

	msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
	if (!msi->msi_regs) {
		dev_err(&dev->dev, "ioremap problem failed\n");
		goto error_out;
	}

280
	msi->feature = features->fsl_pic_ip;
281
282
283
284

	msi->irqhost->host_data = msi;

	msi->msi_addr_hi = 0x0;
285
	msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314

	rc = fsl_msi_init_allocator(msi);
	if (rc) {
		dev_err(&dev->dev, "Error allocating MSI bitmap\n");
		goto error_out;
	}

	p = of_get_property(dev->node, "interrupts", &count);
	if (!p) {
		dev_err(&dev->dev, "no interrupts property found on %s\n",
				dev->node->full_name);
		err = -ENODEV;
		goto error_out;
	}
	if (count % 8 != 0) {
		dev_err(&dev->dev, "Malformed interrupts property on %s\n",
				dev->node->full_name);
		err = -EINVAL;
		goto error_out;
	}

	count /= sizeof(u32);
	for (i = 0; i < count / 2; i++) {
		if (i > NR_MSI_REG)
			break;
		virt_msir = irq_of_parse_and_map(dev->node, i);
		if (virt_msir != NO_IRQ) {
			set_irq_data(virt_msir, (void *)i);
			set_irq_chained_handler(virt_msir, fsl_msi_cascade);
315
			set_irq_chip_data(virt_msir, msi);
316
317
318
		}
	}

319
320
321
322
323
324
325
326
327
328
	/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
	if (!ppc_md.setup_msi_irqs) {
		ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
		ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
		ppc_md.msi_check_device = fsl_msi_check_device;
	} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
		dev_err(&dev->dev, "Different MSI driver already installed!\n");
		err = -ENODEV;
		goto error_out;
	}
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
	return 0;
error_out:
	kfree(msi);
	return err;
}

static const struct fsl_msi_feature mpic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_MPIC,
	.msiir_offset = 0x140,
};

static const struct fsl_msi_feature ipic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_IPIC,
	.msiir_offset = 0x38,
};

static const struct of_device_id fsl_of_msi_ids[] = {
	{
		.compatible = "fsl,mpic-msi",
		.data = (void *)&mpic_msi_feature,
	},
	{
		.compatible = "fsl,ipic-msi",
		.data = (void *)&ipic_msi_feature,
	},
	{}
};

static struct of_platform_driver fsl_of_msi_driver = {
	.name = "fsl-msi",
	.match_table = fsl_of_msi_ids,
	.probe = fsl_of_msi_probe,
};

static __init int fsl_of_msi_init(void)
{
	return of_register_platform_driver(&fsl_of_msi_driver);
}

subsys_initcall(fsl_of_msi_init);