cadence_ttc_timer.c 12.9 KB
Newer Older
1
/*
2
 * This file contains driver for the Cadence Triple Timer Counter Rev 06
3
 *
4
 *  Copyright (C) 2011-2013 Xilinx
5
6
7
8
9
10
11
12
13
14
15
16
17
 *
 * based on arch/mips/kernel/time.c timer driver
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

18
#include <linux/clk.h>
19
20
#include <linux/interrupt.h>
#include <linux/clockchips.h>
21
22
23
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
24
#include <linux/sched_clock.h>
25

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
/*
 * This driver configures the 2 16-bit count-up timers as follows:
 *
 * T1: Timer 1, clocksource for generic timekeeping
 * T2: Timer 2, clockevent source for hrtimers
 * T3: Timer 3, <unused>
 *
 * The input frequency to the timer module for emulation is 2.5MHz which is
 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
 * the timers are clocked at 78.125KHz (12.8 us resolution).

 * The input frequency to the timer module in silicon is configurable and
 * obtained from device tree. The pre-scaler of 32 is used.
 */

41
42
43
44
/*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
45
46
47
48
49
50
#define TTC_CLK_CNTRL_OFFSET		0x00 /* Clock Control Reg, RW */
#define TTC_CNT_CNTRL_OFFSET		0x0C /* Counter Control Reg, RW */
#define TTC_COUNT_VAL_OFFSET		0x18 /* Counter Value Reg, RO */
#define TTC_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
#define TTC_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
#define TTC_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */
51

52
#define TTC_CNT_CNTRL_DISABLE_MASK	0x1
53

54
55
#define TTC_CLK_CNTRL_CSRC_MASK		(1 << 5)	/* clock source */

56
57
/*
 * Setup the timers to use pre-scaling, using a fixed value for now that will
58
59
60
61
62
63
 * work across most input frequency, but it may need to be more dynamic
 */
#define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
#define PRESCALE		2048	/* The exponent must match this */
#define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
#define CLK_CNTRL_PRESCALE_EN	1
64
#define CNT_CNTRL_RESET		(1 << 4)
65
66

/**
67
 * struct ttc_timer - This definition defines local timer structure
68
69
 *
 * @base_addr:	Base address of timer
70
 * @freq:	Timer input clock frequency
71
72
73
 * @clk:	Associated clock source
 * @clk_rate_change_nb	Notifier block for clock rate changes
 */
74
struct ttc_timer {
75
	void __iomem *base_addr;
76
	unsigned long freq;
77
78
	struct clk *clk;
	struct notifier_block clk_rate_change_nb;
79
80
};

81
82
#define to_ttc_timer(x) \
		container_of(x, struct ttc_timer, clk_rate_change_nb)
83

84
85
struct ttc_timer_clocksource {
	struct ttc_timer	ttc;
86
	struct clocksource	cs;
87
88
};

89
90
#define to_ttc_timer_clksrc(x) \
		container_of(x, struct ttc_timer_clocksource, cs)
91

92
93
struct ttc_timer_clockevent {
	struct ttc_timer		ttc;
94
95
96
	struct clock_event_device	ce;
};

97
98
#define to_ttc_timer_clkevent(x) \
		container_of(x, struct ttc_timer_clockevent, ce)
99

100
101
static void __iomem *ttc_sched_clock_val_reg;

102
/**
103
 * ttc_set_interval - Set the timer interval value
104
105
106
107
 *
 * @timer:	Pointer to the timer instance
 * @cycles:	Timer interval ticks
 **/
108
static void ttc_set_interval(struct ttc_timer *timer,
109
110
111
112
113
					unsigned long cycles)
{
	u32 ctrl_reg;

	/* Disable the counter, set the counter value  and re-enable counter */
114
115
116
	ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
	ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
117

118
	__raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
119

120
121
122
123
	/*
	 * Reset the counter (0x10) so that it starts from 0, one-shot
	 * mode makes this needed for timing to be right.
	 */
124
	ctrl_reg |= CNT_CNTRL_RESET;
125
126
	ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
127
128
129
}

/**
130
 * ttc_clock_event_interrupt - Clock event timer interrupt handler
131
132
 *
 * @irq:	IRQ number of the Timer
133
 * @dev_id:	void pointer to the ttc_timer instance
134
135
136
 *
 * returns: Always IRQ_HANDLED - success
 **/
137
static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
138
{
139
140
	struct ttc_timer_clockevent *ttce = dev_id;
	struct ttc_timer *timer = &ttce->ttc;
141
142

	/* Acknowledge the interrupt and call event handler */
143
	__raw_readl(timer->base_addr + TTC_ISR_OFFSET);
144

145
	ttce->ce.event_handler(&ttce->ce);
146
147
148
149
150

	return IRQ_HANDLED;
}

/**
151
 * __ttc_clocksource_read - Reads the timer counter register
152
153
154
 *
 * returns: Current timer counter register value
 **/
155
static cycle_t __ttc_clocksource_read(struct clocksource *cs)
156
{
157
	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
158
159

	return (cycle_t)__raw_readl(timer->base_addr +
160
				TTC_COUNT_VAL_OFFSET);
161
162
}

163
164
165
166
167
static u32 notrace ttc_sched_clock_read(void)
{
	return __raw_readl(ttc_sched_clock_val_reg);
}

168
/**
169
 * ttc_set_next_event - Sets the time interval for next event
170
171
172
173
174
175
 *
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
 * returns: Always 0 - success
 **/
176
static int ttc_set_next_event(unsigned long cycles,
177
178
					struct clock_event_device *evt)
{
179
180
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;
181

182
	ttc_set_interval(timer, cycles);
183
184
185
186
	return 0;
}

/**
187
 * ttc_set_mode - Sets the mode of timer
188
189
190
191
 *
 * @mode:	Mode to be set
 * @evt:	Address of clock event instance
 **/
192
static void ttc_set_mode(enum clock_event_mode mode,
193
194
					struct clock_event_device *evt)
{
195
196
	struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
	struct ttc_timer *timer = &ttce->ttc;
197
198
199
200
	u32 ctrl_reg;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
201
202
		ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,
						PRESCALE * HZ));
203
204
205
206
207
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		ctrl_reg = __raw_readl(timer->base_addr +
208
209
					TTC_CNT_CNTRL_OFFSET);
		ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
210
		__raw_writel(ctrl_reg,
211
				timer->base_addr + TTC_CNT_CNTRL_OFFSET);
212
213
214
		break;
	case CLOCK_EVT_MODE_RESUME:
		ctrl_reg = __raw_readl(timer->base_addr +
215
216
					TTC_CNT_CNTRL_OFFSET);
		ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
217
		__raw_writel(ctrl_reg,
218
				timer->base_addr + TTC_CNT_CNTRL_OFFSET);
219
220
221
222
		break;
	}
}

223
static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
224
225
226
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
227
228
229
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clocksource *ttccs = container_of(ttc,
			struct ttc_timer_clocksource, ttc);
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248

	switch (event) {
	case POST_RATE_CHANGE:
		/*
		 * Do whatever is necessary to maintain a proper time base
		 *
		 * I cannot find a way to adjust the currently used clocksource
		 * to the new frequency. __clocksource_updatefreq_hz() sounds
		 * good, but does not work. Not sure what's that missing.
		 *
		 * This approach works, but triggers two clocksource switches.
		 * The first after unregister to clocksource jiffies. And
		 * another one after the register to the newly registered timer.
		 *
		 * Alternatively we could 'waste' another HW timer to ping pong
		 * between clock sources. That would also use one register and
		 * one unregister call, but only trigger one clocksource switch
		 * for the cost of another HW timer used by the OS.
		 */
249
250
		clocksource_unregister(&ttccs->cs);
		clocksource_register_hz(&ttccs->cs,
251
252
253
254
255
256
257
258
259
				ndata->new_rate / PRESCALE);
		/* fall through */
	case PRE_RATE_CHANGE:
	case ABORT_RATE_CHANGE:
	default:
		return NOTIFY_DONE;
	}
}

260
static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
261
{
262
	struct ttc_timer_clocksource *ttccs;
263
264
265
266
267
268
	int err;

	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	if (WARN_ON(!ttccs))
		return;

269
	ttccs->ttc.clk = clk;
270

271
	err = clk_prepare_enable(ttccs->ttc.clk);
272
273
	if (WARN_ON(err)) {
		kfree(ttccs);
274
		return;
275
	}
276

277
278
	ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);

279
280
281
282
283
	ttccs->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clocksource_cb;
	ttccs->ttc.clk_rate_change_nb.next = NULL;
	if (clk_notifier_register(ttccs->ttc.clk,
				&ttccs->ttc.clk_rate_change_nb))
284
		pr_warn("Unable to register clock notifier.\n");
285

286
287
	ttccs->ttc.base_addr = base;
	ttccs->cs.name = "ttc_clocksource";
288
	ttccs->cs.rating = 200;
289
	ttccs->cs.read = __ttc_clocksource_read;
290
291
292
	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

293
294
295
296
297
	/*
	 * Setup the clock source counter to be an incrementing counter
	 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
	 * it by 32 also. Let it start running now.
	 */
298
	__raw_writel(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
299
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
300
		     ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
301
	__raw_writel(CNT_CNTRL_RESET,
302
		     ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
303

304
	err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
305
306
	if (WARN_ON(err)) {
		kfree(ttccs);
307
		return;
308
	}
309
310

	ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
311
	setup_sched_clock(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
312
313
}

314
static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
315
316
317
		unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
318
319
320
	struct ttc_timer *ttc = to_ttc_timer(nb);
	struct ttc_timer_clockevent *ttcce = container_of(ttc,
			struct ttc_timer_clockevent, ttc);
321
322
323
324
325
326
327
328
329
330
331
332
333

	switch (event) {
	case POST_RATE_CHANGE:
	{
		unsigned long flags;

		/*
		 * clockevents_update_freq should be called with IRQ disabled on
		 * the CPU the timer provides events for. The timer we use is
		 * common to both CPUs, not sure if we need to run on both
		 * cores.
		 */
		local_irq_save(flags);
334
		clockevents_update_freq(&ttcce->ce,
335
336
337
				ndata->new_rate / PRESCALE);
		local_irq_restore(flags);

338
339
340
		/* update cached frequency */
		ttc->freq = ndata->new_rate;

341
342
343
344
345
346
347
348
349
		/* fall through */
	}
	case PRE_RATE_CHANGE:
	case ABORT_RATE_CHANGE:
	default:
		return NOTIFY_DONE;
	}
}

350
static void __init ttc_setup_clockevent(struct clk *clk,
351
						void __iomem *base, u32 irq)
352
{
353
	struct ttc_timer_clockevent *ttcce;
354
	int err;
355
356
357
358
359

	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	if (WARN_ON(!ttcce))
		return;

360
	ttcce->ttc.clk = clk;
361

362
	err = clk_prepare_enable(ttcce->ttc.clk);
363
364
	if (WARN_ON(err)) {
		kfree(ttcce);
365
		return;
366
	}
367

368
369
370
371
372
	ttcce->ttc.clk_rate_change_nb.notifier_call =
		ttc_rate_change_clockevent_cb;
	ttcce->ttc.clk_rate_change_nb.next = NULL;
	if (clk_notifier_register(ttcce->ttc.clk,
				&ttcce->ttc.clk_rate_change_nb))
373
		pr_warn("Unable to register clock notifier.\n");
374
	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
375

376
377
	ttcce->ttc.base_addr = base;
	ttcce->ce.name = "ttc_clockevent";
378
	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
379
380
	ttcce->ce.set_next_event = ttc_set_next_event;
	ttcce->ce.set_mode = ttc_set_mode;
381
382
	ttcce->ce.rating = 200;
	ttcce->ce.irq = irq;
383
	ttcce->ce.cpumask = cpu_possible_mask;
384

385
386
387
388
389
	/*
	 * Setup the clock event timer to be an interval timer which
	 * is prescaled by 32 using the interval interrupt. Leave it
	 * disabled for now.
	 */
390
	__raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
391
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
392
393
		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
	__raw_writel(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
394

395
	err = request_irq(irq, ttc_clock_event_interrupt,
396
397
			  IRQF_DISABLED | IRQF_TIMER,
			  ttcce->ce.name, ttcce);
398
399
	if (WARN_ON(err)) {
		kfree(ttcce);
400
		return;
401
	}
402
403

	clockevents_config_and_register(&ttcce->ce,
404
			ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
405
406
}

407
/**
408
 * ttc_timer_init - Initialize the timer
409
410
411
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
412
 */
413
static void __init ttc_timer_init(struct device_node *timer)
414
415
416
{
	unsigned int irq;
	void __iomem *timer_baseaddr;
417
	struct clk *clk_cs, *clk_ce;
418
	static int initialized;
419
	int clksel;
420
421
422
423
424

	if (initialized)
		return;

	initialized = 1;
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442

	/*
	 * Get the 1st Triple Timer Counter (TTC) block from the device tree
	 * and use it. Note that the event timer uses the interrupt and it's the
	 * 2nd TTC hence the irq_of_parse_and_map(,1)
	 */
	timer_baseaddr = of_iomap(timer, 0);
	if (!timer_baseaddr) {
		pr_err("ERROR: invalid timer base address\n");
		BUG();
	}

	irq = irq_of_parse_and_map(timer, 1);
	if (irq <= 0) {
		pr_err("ERROR: invalid interrupt number\n");
		BUG();
	}

443
444
445
446
447
448
449
450
451
452
453
454
	clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_cs = of_clk_get(timer, clksel);
	if (IS_ERR(clk_cs)) {
		pr_err("ERROR: timer input clock not found\n");
		BUG();
	}

	clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
	clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
	clk_ce = of_clk_get(timer, clksel);
	if (IS_ERR(clk_ce)) {
455
456
457
458
		pr_err("ERROR: timer input clock not found\n");
		BUG();
	}

459
460
	ttc_setup_clocksource(clk_cs, timer_baseaddr);
	ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
461
462
463
464

	pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
}

465
CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);