nouveau_dp.c 19.4 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
/*
 * Copyright 2009 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"
26

27
28
#include "nouveau_drv.h"
#include "nouveau_i2c.h"
29
#include "nouveau_connector.h"
30
#include "nouveau_encoder.h"
31
#include "nouveau_crtc.h"
32
#include "nouveau_gpio.h"
33

34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
/******************************************************************************
 * aux channel util functions
 *****************************************************************************/
#define AUX_DBG(fmt, args...) do {                                             \
	if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) {                     \
		NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args);     \
	}                                                                      \
} while (0)
#define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)

static void
auxch_fini(struct drm_device *dev, int ch)
{
	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
}

static int
auxch_init(struct drm_device *dev, int ch)
{
	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
	const u32 urep = unksel ? 0x01000000 : 0x02000000;
	u32 ctrl, timeout;

	/* wait up to 1ms for any previous transaction to be done... */
	timeout = 1000;
	do {
		ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
		udelay(1);
		if (!timeout--) {
			AUX_ERR("begin idle timeout 0x%08x", ctrl);
			return -EBUSY;
		}
	} while (ctrl & 0x03010000);

	/* set some magic, and wait up to 1ms for it to appear */
	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
	timeout = 1000;
	do {
		ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
		udelay(1);
		if (!timeout--) {
			AUX_ERR("magic wait 0x%08x\n", ctrl);
			auxch_fini(dev, ch);
			return -EBUSY;
		}
	} while ((ctrl & 0x03000000) != urep);

	return 0;
}

static int
auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
{
	u32 ctrl, stat, timeout, retries;
	u32 xbuf[4] = {};
	int ret, i;

	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);

	ret = auxch_init(dev, ch);
	if (ret)
		goto out;

	stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
	if (!(stat & 0x10000000)) {
		AUX_DBG("sink not detected\n");
		ret = -ENXIO;
		goto out;
	}

	if (!(type & 1)) {
		memcpy(xbuf, data, size);
		for (i = 0; i < 16; i += 4) {
			AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
			nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
		}
	}

	ctrl  = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
	ctrl &= ~0x0001f0ff;
	ctrl |= type << 12;
	ctrl |= size - 1;
	nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);

	/* retry transaction a number of times on failure... */
	ret = -EREMOTEIO;
	for (retries = 0; retries < 32; retries++) {
		/* reset, and delay a while if this is a retry */
		nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
		nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
		if (retries)
			udelay(400);

		/* transaction request, wait up to 1ms for it to complete */
		nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);

		timeout = 1000;
		do {
			ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
			udelay(1);
			if (!timeout--) {
				AUX_ERR("tx req timeout 0x%08x\n", ctrl);
				goto out;
			}
		} while (ctrl & 0x00010000);

		/* read status, and check if transaction completed ok */
		stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
		if (!(stat & 0x000f0f00)) {
			ret = 0;
			break;
		}

		AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
	}

	if (type & 1) {
		for (i = 0; i < 16; i += 4) {
			xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
			AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
		}
		memcpy(data, xbuf, size);
	}

out:
	auxch_fini(dev, ch);
	return ret;
}

164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
static u32
dp_link_bw_get(struct drm_device *dev, int or, int link)
{
	u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
	if (!(ctrl & 0x000c0000))
		return 162000;
	return 270000;
}

static int
dp_lane_count_get(struct drm_device *dev, int or, int link)
{
	u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
	switch (ctrl & 0x000f0000) {
	case 0x00010000: return 1;
	case 0x00030000: return 2;
	default:
		return 4;
	}
}

void
nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
{
	const u32 symbol = 100000;
	int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
	int TU, VTUi, VTUf, VTUa;
	u64 link_data_rate, link_ratio, unk;
	u32 best_diff = 64 * symbol;
	u32 link_nr, link_bw, r;

	/* calculate packed data rate for each lane */
	link_nr = dp_lane_count_get(dev, or, link);
	link_data_rate = (clk * bpp / 8) / link_nr;

	/* calculate ratio of packed data rate to link symbol rate */
	link_bw = dp_link_bw_get(dev, or, link);
	link_ratio = link_data_rate * symbol;
	r = do_div(link_ratio, link_bw);

	for (TU = 64; TU >= 32; TU--) {
		/* calculate average number of valid symbols in each TU */
		u32 tu_valid = link_ratio * TU;
		u32 calc, diff;

		/* find a hw representation for the fraction.. */
		VTUi = tu_valid / symbol;
		calc = VTUi * symbol;
		diff = tu_valid - calc;
		if (diff) {
			if (diff >= (symbol / 2)) {
				VTUf = symbol / (symbol - diff);
				if (symbol - (VTUf * diff))
					VTUf++;

				if (VTUf <= 15) {
					VTUa  = 1;
					calc += symbol - (symbol / VTUf);
				} else {
					VTUa  = 0;
					VTUf  = 1;
					calc += symbol;
				}
			} else {
				VTUa  = 0;
				VTUf  = min((int)(symbol / diff), 15);
				calc += symbol / VTUf;
			}

			diff = calc - tu_valid;
		} else {
			/* no remainder, but the hw doesn't like the fractional
			 * part to be zero.  decrement the integer part and
			 * have the fraction add a whole symbol back
			 */
			VTUa = 0;
			VTUf = 1;
			VTUi--;
		}

		if (diff < best_diff) {
			best_diff = diff;
			bestTU = TU;
			bestVTUa = VTUa;
			bestVTUf = VTUf;
			bestVTUi = VTUi;
			if (diff == 0)
				break;
		}
	}

	if (!bestTU) {
		NV_ERROR(dev, "DP: unable to find suitable config\n");
		return;
	}

	/* XXX close to vbios numbers, but not right */
	unk  = (symbol - link_ratio) * bestTU;
	unk *= link_ratio;
	r = do_div(unk, symbol);
	r = do_div(unk, symbol);
	unk += 6;

	nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
	nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
							     bestVTUf << 16 |
							     bestVTUi << 8 |
							     unk);
}

274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
u8 *
nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
{
	struct bit_entry d;
	u8 *table;
	int i;

	if (bit_table(dev, 'd', &d)) {
		NV_ERROR(dev, "BIT 'd' table not found\n");
		return NULL;
	}

	if (d.version != 1) {
		NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version);
		return NULL;
	}

291
	table = ROMPTR(dev, d.data[0]);
292
293
294
295
296
297
298
299
	if (!table) {
		NV_ERROR(dev, "displayport table pointer invalid\n");
		return NULL;
	}

	switch (table[0]) {
	case 0x20:
	case 0x21:
300
	case 0x30:
301
302
303
304
305
306
307
		break;
	default:
		NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]);
		return NULL;
	}

	for (i = 0; i < table[3]; i++) {
308
		*entry = ROMPTR(dev, table[table[1] + (i * table[2])]);
309
310
311
312
313
314
315
316
		if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
			return table;
	}

	NV_ERROR(dev, "displayport encoder table not found\n");
	return NULL;
}

317
318
319
320
321
/******************************************************************************
 * link training
 *****************************************************************************/
struct dp_state {
	struct dcb_entry *dcb;
322
323
	u8 *table;
	u8 *entry;
324
325
326
327
	int auxch;
	int crtc;
	int or;
	int link;
328
	u8 *dpcd;
329
330
331
332
333
	int link_nr;
	u32 link_bw;
	u8  stat[6];
	u8  conf[4];
};
334

335
336
static void
dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
337
{
338
	int or = dp->or, link = dp->link;
339
	u8 *entry, sink[2];
340
	u32 dp_ctrl;
341
	u16 script;
342

343
	NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
344

345
	/* set selected link rate on source */
346
347
	switch (dp->link_bw) {
	case 270000:
348
		nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000);
349
350
351
		sink[0] = DP_LINK_BW_2_7;
		break;
	default:
352
		nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000);
353
354
355
		sink[0] = DP_LINK_BW_1_62;
		break;
	}
356

357
358
359
360
	/* offset +0x0a of each dp encoder table entry is a pointer to another
	 * table, that has (among other things) pointers to more scripts that
	 * need to be executed, this time depending on link speed.
	 */
361
	entry = ROMPTR(dev, dp->entry[10]);
362
	if (entry) {
363
364
365
366
367
368
369
370
371
		if (dp->table[0] < 0x30) {
			while (dp->link_bw < (ROM16(entry[0]) * 10))
				entry += 4;
			script = ROM16(entry[2]);
		} else {
			while (dp->link_bw < (entry[0] * 27000))
				entry += 3;
			script = ROM16(entry[1]);
		}
372

373
		nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
374
375
376
	}

	/* configure lane count on the source */
377
378
	dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
	sink[1] = dp->link_nr;
379
	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) {
380
381
382
		dp_ctrl |= 0x00004000;
		sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	}
383

384
	nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);
385

386
	/* inform the sink of the new configuration */
387
	auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
388
389
}

390
391
static void
dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp)
392
{
393
394
	u8 sink_tp;

395
	NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
396

397
	nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
398
399
400
401
402

	auxch_tx(dev, dp->auxch, 9, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
	sink_tp |= tp;
	auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
403
404
}

405
406
407
static const u8 nv50_lane_map[] = { 16, 8, 0, 24 };
static const u8 nvaf_lane_map[] = { 24, 16, 8, 0 };

408
static int
409
dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
410
{
411
	struct drm_nouveau_private *dev_priv = dev->dev_private;
412
	u32 mask = 0, drv = 0, pre = 0, unk = 0;
413
	const u8 *shifts;
414
415
416
417
	int link = dp->link;
	int or = dp->or;
	int i;

418
419
420
421
422
	if (dev_priv->chipset != 0xaf)
		shifts = nv50_lane_map;
	else
		shifts = nvaf_lane_map;

423
	for (i = 0; i < dp->link_nr; i++) {
424
		u8 *conf = dp->entry + dp->table[4];
425
426
427
		u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
		u8 lpre = (lane & 0x0c) >> 2;
		u8 lvsw = (lane & 0x03) >> 0;
428

429
430
		mask |= 0xff << shifts[i];
		unk |= 1 << (shifts[i] >> 3);
431

432
433
		dp->conf[i] = (lpre << 3) | lvsw;
		if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
434
			dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
435
		if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
436
			dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
437

438
439
		NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);

440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
		if (dp->table[0] < 0x30) {
			u8 *last = conf + (dp->entry[4] * dp->table[5]);
			while (lvsw != conf[0] || lpre != conf[1]) {
				conf += dp->table[5];
				if (conf >= last)
					return -EINVAL;
			}

			conf += 2;
		} else {
			/* no lookup table anymore, set entries for each
			 * combination of voltage swing and pre-emphasis
			 * level allowed by the DP spec.
			 */
			switch (lvsw) {
			case 0: lpre += 0; break;
			case 1: lpre += 4; break;
			case 2: lpre += 7; break;
			case 3: lpre += 9; break;
			}

			conf = conf + (lpre * dp->table[5]);
			conf++;
		}

		drv |= conf[0] << shifts[i];
		pre |= conf[1] << shifts[i];
		unk  = (unk & ~0x0000ff00) | (conf[2] << 8);
468
469
	}

470
471
472
473
474
	nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
	nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
	nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);

	return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
475
476
}

477
478
static int
dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
479
{
480
	int ret;
481

482
	udelay(delay);
483

484
	ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
485
	if (ret)
486
		return ret;
487

488
489
490
491
492
	NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
		     dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
		     dp->stat[4], dp->stat[5]);
	return 0;
}
493

494
495
496
497
498
499
static int
dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
{
	bool cr_done = false, abort = false;
	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	int tries = 0, i;
500

501
	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
502

503
504
505
506
	do {
		if (dp_link_train_commit(dev, dp) ||
		    dp_link_train_update(dev, dp, 100))
			break;
507

508
509
510
511
512
513
514
515
516
517
		cr_done = true;
		for (i = 0; i < dp->link_nr; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE)) {
				cr_done = false;
				if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
					abort = true;
				break;
			}
		}
518

519
520
521
522
523
		if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
			voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
			tries = 0;
		}
	} while (!cr_done && !abort && ++tries < 5);
524

525
	return cr_done ? 0 : -1;
526
527
}

528
529
static int
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
530
{
531
532
	bool eq_done, cr_done = true;
	int tries = 0, i;
533

534
	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
535

536
537
	do {
		if (dp_link_train_update(dev, dp, 400))
538
539
			break;

540
541
542
543
544
545
546
547
548
		eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
		for (i = 0; i < dp->link_nr && eq_done; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE))
				cr_done = false;
			if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
			    !(lane & DP_LANE_SYMBOL_LOCKED))
				eq_done = false;
		}
549

550
551
552
553
554
		if (dp_link_train_commit(dev, dp))
			break;
	} while (!eq_done && cr_done && ++tries <= 5);

	return eq_done ? 0 : -1;
555
556
}

557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
static void
dp_set_downspread(struct drm_device *dev, struct dp_state *dp, bool enable)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30) {
			if (enable)
				script = ROM16(entry[12]);
			else
				script = ROM16(entry[14]);
		}
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

static void
dp_link_train_init(struct drm_device *dev, struct dp_state *dp)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30)
			script = ROM16(entry[6]);
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

static void
dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30)
			script = ROM16(entry[8]);
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

600
bool
601
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
602
603
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
604
605
606
607
608
609
610
611
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nouveau_connector *nv_connector =
		nouveau_encoder_connector_get(nv_encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_i2c_chan *auxch;
	const u32 bw_list[] = { 270000, 162000, 0 };
	const u32 *link_bw = bw_list;
	struct dp_state dp;
612

613
614
	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	if (!auxch)
615
616
		return false;

617
618
	dp.table = nouveau_dp_bios_data(dev, nv_encoder->dcb, &dp.entry);
	if (!dp.table)
619
		return -EINVAL;
620

621
622
	dp.dcb = nv_encoder->dcb;
	dp.crtc = nv_crtc->index;
623
	dp.auxch = auxch->drive;
624
625
	dp.or = nv_encoder->or;
	dp.link = !(nv_encoder->dcb->sorconf.link & 1);
626
	dp.dpcd = nv_encoder->dp.dpcd;
627

628
629
630
631
	/* some sinks toggle hotplug in response to some of the actions
	 * we take during link training (DP_SET_POWER is one), we need
	 * to ignore them for the moment to avoid races.
	 */
632
	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false);
633

634
	/* enable down-spreading, if possible */
635
	dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
636

637
	/* execute pre-train script from vbios */
638
	dp_link_train_init(dev, &dp);
639

640
	/* start off at highest link rate supported by encoder and display */
641
	while (*link_bw > nv_encoder->dp.link_bw)
642
		link_bw++;
643

644
645
646
647
648
	while (link_bw[0]) {
		/* find minimum required lane count at this link rate */
		dp.link_nr = nv_encoder->dp.link_nr;
		while ((dp.link_nr >> 1) * link_bw[0] > datarate)
			dp.link_nr >>= 1;
649

650
651
652
653
		/* drop link rate to minimum with this lane count */
		while ((link_bw[1] * dp.link_nr) > datarate)
			link_bw++;
		dp.link_bw = link_bw[0];
654

655
656
		/* program selected link configuration */
		dp_set_link_config(dev, &dp);
657

658
659
660
661
		/* attempt to train the link at this configuration */
		memset(dp.stat, 0x00, sizeof(dp.stat));
		if (!dp_link_train_cr(dev, &dp) &&
		    !dp_link_train_eq(dev, &dp))
662
663
			break;

664
665
		/* retry at lower rate */
		link_bw++;
666
667
	}

668
669
	/* finish link training */
	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
670

671
	/* execute post-train script from vbios */
672
	dp_link_train_fini(dev, &dp);
673

674
	/* re-enable hotplug detect */
675
	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true);
676
	return true;
677
678
679
680
681
682
683
}

bool
nouveau_dp_detect(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_device *dev = encoder->dev;
684
685
	struct nouveau_i2c_chan *auxch;
	u8 *dpcd = nv_encoder->dp.dpcd;
686
687
	int ret;

688
689
690
691
	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return false;

692
	ret = auxch_tx(dev, auxch->drive, 9, DP_DPCD_REV, dpcd, 8);
693
694
695
	if (ret)
		return false;

696
697
	nv_encoder->dp.link_bw = 27000 * dpcd[1];
	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
698

699
700
701
702
703
	NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
	NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
		     nv_encoder->dcb->dpconf.link_nr,
		     nv_encoder->dcb->dpconf.link_bw);
704

705
	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
706
		nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
707
708
	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
		nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
709

710
711
	NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
712

713
714
715
716
717
718
719
	return true;
}

int
nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
		 uint8_t *data, int data_nr)
{
720
	return auxch_tx(auxch->dev, auxch->drive, cmd, addr, data, data_nr);
721
722
}

723
724
static int
nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
725
{
726
727
728
	struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
	struct i2c_msg *msg = msgs;
	int ret, mcnt = num;
729

730
731
732
	while (mcnt--) {
		u8 remaining = msg->len;
		u8 *ptr = msg->buf;
733

734
735
736
		while (remaining) {
			u8 cnt = (remaining > 16) ? 16 : remaining;
			u8 cmd;
737

738
739
740
741
742
743
744
745
746
747
748
749
750
751
			if (msg->flags & I2C_M_RD)
				cmd = AUX_I2C_READ;
			else
				cmd = AUX_I2C_WRITE;

			if (mcnt || remaining > 16)
				cmd |= AUX_I2C_MOT;

			ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
			if (ret < 0)
				return ret;

			ptr += cnt;
			remaining -= cnt;
752
		}
753
754

		msg++;
755
	}
756
757
758
759
760
761
762
763

	return num;
}

static u32
nouveau_dp_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
764
765
}

766
767
768
769
const struct i2c_algorithm nouveau_dp_i2c_algo = {
	.master_xfer = nouveau_dp_i2c_xfer,
	.functionality = nouveau_dp_i2c_func
};