bnxt_hsi.h 128 KB
Newer Older
1
2
/* Broadcom NetXtreme-C/E network driver.
 *
3
 * Copyright (c) 2014-2016 Broadcom Corporation
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation.
 */

#ifndef BNXT_HSI_H
#define BNXT_HSI_H

/* per-context HW statistics -- chip view */
struct ctx_hw_stats  {
	__le64 rx_ucast_pkts;
	__le64 rx_mcast_pkts;
	__le64 rx_bcast_pkts;
	__le64 rx_discard_pkts;
	__le64 rx_drop_pkts;
	__le64 rx_ucast_bytes;
	__le64 rx_mcast_bytes;
	__le64 rx_bcast_bytes;
	__le64 tx_ucast_pkts;
	__le64 tx_mcast_pkts;
	__le64 tx_bcast_pkts;
	__le64 tx_discard_pkts;
	__le64 tx_drop_pkts;
	__le64 tx_ucast_bytes;
	__le64 tx_mcast_bytes;
	__le64 tx_bcast_bytes;
	__le64 tpa_pkts;
	__le64 tpa_bytes;
	__le64 tpa_events;
	__le64 tpa_aborts;
};

/* Statistics Ejection Buffer Completion Record (16 bytes) */
struct eject_cmpl {
	__le16 type;
	#define EJECT_CMPL_TYPE_MASK				    0x3fUL
	#define EJECT_CMPL_TYPE_SFT				    0
	#define EJECT_CMPL_TYPE_STAT_EJECT			   (0x1aUL << 0)
	__le16 len;
	__le32 opaque;
	__le32 v;
	#define EJECT_CMPL_V					    0x1UL
	__le32 unused_2;
};

/* HWRM Completion Record (16 bytes) */
struct hwrm_cmpl {
	__le16 type;
	#define HWRM_CMPL_TYPE_MASK				    0x3fUL
	#define HWRM_CMPL_TYPE_SFT				    0
	#define HWRM_CMPL_TYPE_HWRM_DONE			   (0x20UL << 0)
	__le16 sequence_id;
	__le32 unused_1;
	__le32 v;
	#define HWRM_CMPL_V					    0x1UL
	__le32 unused_3;
};

/* HWRM Forwarded Request (16 bytes) */
struct hwrm_fwd_req_cmpl {
	__le16 req_len_type;
	#define HWRM_FWD_REQ_CMPL_TYPE_MASK			    0x3fUL
	#define HWRM_FWD_REQ_CMPL_TYPE_SFT			    0
	#define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ		   (0x22UL << 0)
	#define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK			    0xffc0UL
	#define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT			    6
	__le16 source_id;
	__le32 unused_0;
	__le32 req_buf_addr_v[2];
	#define HWRM_FWD_REQ_CMPL_V				    0x1UL
	#define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK		    0xfffffffeUL
	#define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT		    1
};

/* HWRM Forwarded Response (16 bytes) */
struct hwrm_fwd_resp_cmpl {
	__le16 type;
	#define HWRM_FWD_RESP_CMPL_TYPE_MASK			    0x3fUL
	#define HWRM_FWD_RESP_CMPL_TYPE_SFT			    0
	#define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP		   (0x24UL << 0)
	__le16 source_id;
	__le16 resp_len;
	__le16 unused_1;
	__le32 resp_buf_addr_v[2];
	#define HWRM_FWD_RESP_CMPL_V				    0x1UL
	#define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK		    0xfffffffeUL
	#define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT		    1
};

/* HWRM Asynchronous Event Completion Record (16 bytes) */
struct hwrm_async_event_cmpl {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK		    0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT			    0
	#define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT       (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE    (0x1UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE  (0x2UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE  (0x3UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
106
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0)
107
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0)
108
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE (0x7UL << 0)
109
110
111
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD   (0x10UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD     (0x11UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD     (0x20UL << 0)
112
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD       (0x21UL << 0)
113
114
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR		   (0x30UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
115
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0)
116
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE      (0x33UL << 0)
117
118
119
120
121
122
	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR	   (0xffUL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_V			    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK		    0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT		    1
123
124
	u8 timestamp_lo;
	__le16 timestamp_hi;
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
	__le32 event_data1;
};

/* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */
struct hwrm_async_event_cmpl_link_status_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT  0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
141
142
	u8 timestamp_lo;
	__le16 timestamp_hi;
143
	__le32 event_data1;
144
145
146
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0)
147
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST    HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
148
149
150
151
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
};

/* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */
struct hwrm_async_event_cmpl_link_mtu_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK    0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT     0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK  0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT   1
167
168
	u8 timestamp_lo;
	__le16 timestamp_hi;
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
};

/* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */
struct hwrm_async_event_cmpl_link_speed_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK  0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT   0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
187
188
	u8 timestamp_lo;
	__le16 timestamp_hi;
189
190
191
192
193
194
195
196
197
198
199
200
201
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1)
202
203
204
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB (0xffffUL << 1)
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST    HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
};

/* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */
struct hwrm_async_event_cmpl_dcb_config_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK  0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT   0
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
222
223
	u8 timestamp_lo;
	__le16 timestamp_hi;
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
struct hwrm_async_event_cmpl_port_conn_not_allowed {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V      0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
242
243
	u8 timestamp_lo;
	__le16 timestamp_hi;
244
245
246
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16)
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16)
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16)
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16)
	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST    HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
};

/* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */
struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */
struct hwrm_async_event_cmpl_link_speed_cfg_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V      0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL
	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
};

/* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */
struct hwrm_async_event_cmpl_func_drvr_unload {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK   0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT    0
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT  1
311
312
	u8 timestamp_lo;
	__le16 timestamp_hi;
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */
struct hwrm_async_event_cmpl_func_drvr_load {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK     0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT      0
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK   0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT    1
331
332
	u8 timestamp_lo;
	__le16 timestamp_hi;
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */
struct hwrm_async_event_cmpl_pf_drvr_unload {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK     0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT      0
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK   0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT    1
351
352
	u8 timestamp_lo;
	__le16 timestamp_hi;
353
354
355
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
356
357
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
358
359
360
361
362
363
364
365
366
};

/* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */
struct hwrm_async_event_cmpl_pf_drvr_load {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK       0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT	    0
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
367
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0)
368
369
370
371
372
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK     0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT      1
373
374
	u8 timestamp_lo;
	__le16 timestamp_hi;
375
376
377
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
378
379
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
};

/* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */
struct hwrm_async_event_cmpl_vf_flr {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK		    0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT		    0
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR      (0x30UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V			    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK	    0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT	    1
395
396
	u8 timestamp_lo;
	__le16 timestamp_hi;
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
};

/* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */
struct hwrm_async_event_cmpl_vf_mac_addr_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT  0
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V	    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
415
416
	u8 timestamp_lo;
	__le16 timestamp_hi;
417
418
419
420
421
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
};

422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
/* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */
struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V   0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL
};

/* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */
struct hwrm_async_event_cmpl_vf_cfg_change {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK      0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT       0
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE (0x33UL << 0)
	__le32 event_data2;
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK    0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT     1
	u8 timestamp_lo;
	__le16 timestamp_hi;
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL
	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL
};

463
464
465
466
467
468
469
470
471
472
473
474
475
476
/* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */
struct hwrm_async_event_cmpl_hwrm_error {
	__le16 type;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK	    0x3fUL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT	    0
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
	__le16 event_id;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR (0xffUL << 0)
	__le32 event_data2;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING (0x0UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL (0x1UL << 0)
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL (0x2UL << 0)
477
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST    HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
478
479
480
481
	u8 opaque_v;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V		    0x1UL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK       0xfeUL
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT	    1
482
483
	u8 timestamp_lo;
	__le16 timestamp_hi;
484
485
486
487
	__le32 event_data1;
	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
};

488
/* HW Resource Manager Specification 1.3.0 */
489
#define HWRM_VERSION_MAJOR	1
490
491
#define HWRM_VERSION_MINOR	3
#define HWRM_VERSION_UPDATE	0
492

493
#define HWRM_VERSION_STR	"1.3.0"
494
495
/*
 * Following is the signature for HWRM message field that indicates not
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
 * applicable (All F's). Need to cast it the size of the field if needed.
 */
#define HWRM_NA_SIGNATURE	((__le32)(-1))
#define HWRM_MAX_REQ_LEN    (128)  /* hwrm_func_buf_rgtr */
#define HWRM_MAX_RESP_LEN    (176)  /* hwrm_func_qstats */
#define HW_HASH_INDEX_SIZE      0x80    /* 7 bit indirection table index. */
#define HW_HASH_KEY_SIZE	40
#define HWRM_RESP_VALID_KEY      1 /* valid key for HWRM response */
/* Input (16 bytes) */
struct input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

/* Output (8 bytes) */
struct output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
};

/* Command numbering (8 bytes) */
struct cmd_nums {
	__le16 req_type;
	#define HWRM_VER_GET					   (0x0UL)
525
526
527
	#define HWRM_FUNC_BUF_UNRGTR				   (0xeUL)
	#define HWRM_FUNC_VF_CFG				   (0xfUL)
	#define RESERVED1					   (0x10UL)
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
	#define HWRM_FUNC_RESET				   (0x11UL)
	#define HWRM_FUNC_GETFID				   (0x12UL)
	#define HWRM_FUNC_VF_ALLOC				   (0x13UL)
	#define HWRM_FUNC_VF_FREE				   (0x14UL)
	#define HWRM_FUNC_QCAPS				   (0x15UL)
	#define HWRM_FUNC_QCFG					   (0x16UL)
	#define HWRM_FUNC_CFG					   (0x17UL)
	#define HWRM_FUNC_QSTATS				   (0x18UL)
	#define HWRM_FUNC_CLR_STATS				   (0x19UL)
	#define HWRM_FUNC_DRV_UNRGTR				   (0x1aUL)
	#define HWRM_FUNC_VF_RESC_FREE				   (0x1bUL)
	#define HWRM_FUNC_VF_VNIC_IDS_QUERY			   (0x1cUL)
	#define HWRM_FUNC_DRV_RGTR				   (0x1dUL)
	#define HWRM_FUNC_DRV_QVER				   (0x1eUL)
	#define HWRM_FUNC_BUF_RGTR				   (0x1fUL)
	#define HWRM_PORT_PHY_CFG				   (0x20UL)
	#define HWRM_PORT_MAC_CFG				   (0x21UL)
545
	#define HWRM_PORT_TS_QUERY				   (0x22UL)
546
547
548
549
550
551
552
	#define HWRM_PORT_QSTATS				   (0x23UL)
	#define HWRM_PORT_LPBK_QSTATS				   (0x24UL)
	#define HWRM_PORT_CLR_STATS				   (0x25UL)
	#define HWRM_PORT_LPBK_CLR_STATS			   (0x26UL)
	#define HWRM_PORT_PHY_QCFG				   (0x27UL)
	#define HWRM_PORT_MAC_QCFG				   (0x28UL)
	#define HWRM_PORT_BLINK_LED				   (0x29UL)
553
554
555
	#define HWRM_PORT_PHY_QCAPS				   (0x2aUL)
	#define HWRM_PORT_PHY_I2C_WRITE			   (0x2bUL)
	#define HWRM_PORT_PHY_I2C_READ				   (0x2cUL)
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
	#define HWRM_QUEUE_QPORTCFG				   (0x30UL)
	#define HWRM_QUEUE_QCFG				   (0x31UL)
	#define HWRM_QUEUE_CFG					   (0x32UL)
	#define HWRM_QUEUE_BUFFERS_QCFG			   (0x33UL)
	#define HWRM_QUEUE_BUFFERS_CFG				   (0x34UL)
	#define HWRM_QUEUE_PFCENABLE_QCFG			   (0x35UL)
	#define HWRM_QUEUE_PFCENABLE_CFG			   (0x36UL)
	#define HWRM_QUEUE_PRI2COS_QCFG			   (0x37UL)
	#define HWRM_QUEUE_PRI2COS_CFG				   (0x38UL)
	#define HWRM_QUEUE_COS2BW_QCFG				   (0x39UL)
	#define HWRM_QUEUE_COS2BW_CFG				   (0x3aUL)
	#define HWRM_VNIC_ALLOC				   (0x40UL)
	#define HWRM_VNIC_FREE					   (0x41UL)
	#define HWRM_VNIC_CFG					   (0x42UL)
	#define HWRM_VNIC_QCFG					   (0x43UL)
	#define HWRM_VNIC_TPA_CFG				   (0x44UL)
	#define HWRM_VNIC_TPA_QCFG				   (0x45UL)
	#define HWRM_VNIC_RSS_CFG				   (0x46UL)
	#define HWRM_VNIC_RSS_QCFG				   (0x47UL)
	#define HWRM_VNIC_PLCMODES_CFG				   (0x48UL)
	#define HWRM_VNIC_PLCMODES_QCFG			   (0x49UL)
	#define HWRM_RING_ALLOC				   (0x50UL)
	#define HWRM_RING_FREE					   (0x51UL)
	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS		   (0x52UL)
	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS		   (0x53UL)
	#define HWRM_RING_RESET				   (0x5eUL)
	#define HWRM_RING_GRP_ALLOC				   (0x60UL)
	#define HWRM_RING_GRP_FREE				   (0x61UL)
	#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC			   (0x70UL)
	#define HWRM_VNIC_RSS_COS_LB_CTX_FREE			   (0x71UL)
	#define HWRM_CFA_L2_FILTER_ALLOC			   (0x90UL)
	#define HWRM_CFA_L2_FILTER_FREE			   (0x91UL)
	#define HWRM_CFA_L2_FILTER_CFG				   (0x92UL)
	#define HWRM_CFA_L2_SET_RX_MASK			   (0x93UL)
590
	#define RESERVED3					   (0x94UL)
591
592
593
594
595
596
597
	#define HWRM_CFA_TUNNEL_FILTER_ALLOC			   (0x95UL)
	#define HWRM_CFA_TUNNEL_FILTER_FREE			   (0x96UL)
	#define HWRM_CFA_ENCAP_RECORD_ALLOC			   (0x97UL)
	#define HWRM_CFA_ENCAP_RECORD_FREE			   (0x98UL)
	#define HWRM_CFA_NTUPLE_FILTER_ALLOC			   (0x99UL)
	#define HWRM_CFA_NTUPLE_FILTER_FREE			   (0x9aUL)
	#define HWRM_CFA_NTUPLE_FILTER_CFG			   (0x9bUL)
598
599
600
	#define HWRM_CFA_EM_FLOW_ALLOC				   (0x9cUL)
	#define HWRM_CFA_EM_FLOW_FREE				   (0x9dUL)
	#define HWRM_CFA_EM_FLOW_CFG				   (0x9eUL)
601
602
603
604
605
606
607
608
609
610
611
612
613
614
	#define HWRM_TUNNEL_DST_PORT_QUERY			   (0xa0UL)
	#define HWRM_TUNNEL_DST_PORT_ALLOC			   (0xa1UL)
	#define HWRM_TUNNEL_DST_PORT_FREE			   (0xa2UL)
	#define HWRM_STAT_CTX_ALLOC				   (0xb0UL)
	#define HWRM_STAT_CTX_FREE				   (0xb1UL)
	#define HWRM_STAT_CTX_QUERY				   (0xb2UL)
	#define HWRM_STAT_CTX_CLR_STATS			   (0xb3UL)
	#define HWRM_FW_RESET					   (0xc0UL)
	#define HWRM_FW_QSTATUS				   (0xc1UL)
	#define HWRM_EXEC_FWD_RESP				   (0xd0UL)
	#define HWRM_REJECT_FWD_RESP				   (0xd1UL)
	#define HWRM_FWD_RESP					   (0xd2UL)
	#define HWRM_FWD_ASYNC_EVENT_CMPL			   (0xd3UL)
	#define HWRM_TEMP_MONITOR_QUERY			   (0xe0UL)
615
616
617
	#define HWRM_WOL_FILTER_ALLOC				   (0xf0UL)
	#define HWRM_WOL_FILTER_FREE				   (0xf1UL)
	#define HWRM_WOL_FILTER_QCFG				   (0xf2UL)
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
	#define HWRM_DBG_READ_DIRECT				   (0xff10UL)
	#define HWRM_DBG_READ_INDIRECT				   (0xff11UL)
	#define HWRM_DBG_WRITE_DIRECT				   (0xff12UL)
	#define HWRM_DBG_WRITE_INDIRECT			   (0xff13UL)
	#define HWRM_DBG_DUMP					   (0xff14UL)
	#define HWRM_NVM_MODIFY				   (0xfff4UL)
	#define HWRM_NVM_VERIFY_UPDATE				   (0xfff5UL)
	#define HWRM_NVM_GET_DEV_INFO				   (0xfff6UL)
	#define HWRM_NVM_ERASE_DIR_ENTRY			   (0xfff7UL)
	#define HWRM_NVM_MOD_DIR_ENTRY				   (0xfff8UL)
	#define HWRM_NVM_FIND_DIR_ENTRY			   (0xfff9UL)
	#define HWRM_NVM_GET_DIR_ENTRIES			   (0xfffaUL)
	#define HWRM_NVM_GET_DIR_INFO				   (0xfffbUL)
	#define HWRM_NVM_RAW_DUMP				   (0xfffcUL)
	#define HWRM_NVM_READ					   (0xfffdUL)
	#define HWRM_NVM_WRITE					   (0xfffeUL)
	#define HWRM_NVM_RAW_WRITE_BLK				   (0xffffUL)
	__le16 unused_0[3];
};

638
/* Return Codes (8 bytes) */
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
struct ret_codes {
	__le16 error_code;
	#define HWRM_ERR_CODE_SUCCESS				   (0x0UL)
	#define HWRM_ERR_CODE_FAIL				   (0x1UL)
	#define HWRM_ERR_CODE_INVALID_PARAMS			   (0x2UL)
	#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED		   (0x3UL)
	#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR		   (0x4UL)
	#define HWRM_ERR_CODE_INVALID_FLAGS			   (0x5UL)
	#define HWRM_ERR_CODE_INVALID_ENABLES			   (0x6UL)
	#define HWRM_ERR_CODE_HWRM_ERROR			   (0xfUL)
	#define HWRM_ERR_CODE_UNKNOWN_ERR			   (0xfffeUL)
	#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED		   (0xffffUL)
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_err_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 opaque_0;
	__le16 opaque_1;
662
	u8 cmd_err;
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
	u8 valid;
};

/* Port Tx Statistics Formats (408 bytes) */
struct tx_port_stats {
	__le64 tx_64b_frames;
	__le64 tx_65b_127b_frames;
	__le64 tx_128b_255b_frames;
	__le64 tx_256b_511b_frames;
	__le64 tx_512b_1023b_frames;
	__le64 tx_1024b_1518_frames;
	__le64 tx_good_vlan_frames;
	__le64 tx_1519b_2047_frames;
	__le64 tx_2048b_4095b_frames;
	__le64 tx_4096b_9216b_frames;
	__le64 tx_9217b_16383b_frames;
	__le64 tx_good_frames;
	__le64 tx_total_frames;
	__le64 tx_ucast_frames;
	__le64 tx_mcast_frames;
	__le64 tx_bcast_frames;
	__le64 tx_pause_frames;
	__le64 tx_pfc_frames;
	__le64 tx_jabber_frames;
	__le64 tx_fcs_err_frames;
	__le64 tx_control_frames;
	__le64 tx_oversz_frames;
	__le64 tx_single_dfrl_frames;
	__le64 tx_multi_dfrl_frames;
	__le64 tx_single_coll_frames;
	__le64 tx_multi_coll_frames;
	__le64 tx_late_coll_frames;
	__le64 tx_excessive_coll_frames;
	__le64 tx_frag_frames;
	__le64 tx_err;
	__le64 tx_tagged_frames;
	__le64 tx_dbl_tagged_frames;
	__le64 tx_runt_frames;
	__le64 tx_fifo_underruns;
	__le64 tx_pfc_ena_frames_pri0;
	__le64 tx_pfc_ena_frames_pri1;
	__le64 tx_pfc_ena_frames_pri2;
	__le64 tx_pfc_ena_frames_pri3;
	__le64 tx_pfc_ena_frames_pri4;
	__le64 tx_pfc_ena_frames_pri5;
	__le64 tx_pfc_ena_frames_pri6;
	__le64 tx_pfc_ena_frames_pri7;
	__le64 tx_eee_lpi_events;
	__le64 tx_eee_lpi_duration;
	__le64 tx_llfc_logical_msgs;
	__le64 tx_hcfc_msgs;
	__le64 tx_total_collisions;
	__le64 tx_bytes;
	__le64 tx_xthol_frames;
	__le64 tx_stat_discard;
	__le64 tx_stat_error;
};

/* Port Rx Statistics Formats (528 bytes) */
struct rx_port_stats {
	__le64 rx_64b_frames;
	__le64 rx_65b_127b_frames;
	__le64 rx_128b_255b_frames;
	__le64 rx_256b_511b_frames;
	__le64 rx_512b_1023b_frames;
	__le64 rx_1024b_1518_frames;
	__le64 rx_good_vlan_frames;
	__le64 rx_1519b_2047b_frames;
	__le64 rx_2048b_4095b_frames;
	__le64 rx_4096b_9216b_frames;
	__le64 rx_9217b_16383b_frames;
	__le64 rx_total_frames;
	__le64 rx_ucast_frames;
	__le64 rx_mcast_frames;
	__le64 rx_bcast_frames;
	__le64 rx_fcs_err_frames;
	__le64 rx_ctrl_frames;
	__le64 rx_pause_frames;
	__le64 rx_pfc_frames;
	__le64 rx_unsupported_opcode_frames;
	__le64 rx_unsupported_da_pausepfc_frames;
	__le64 rx_wrong_sa_frames;
	__le64 rx_align_err_frames;
	__le64 rx_oor_len_frames;
	__le64 rx_code_err_frames;
	__le64 rx_false_carrier_frames;
	__le64 rx_ovrsz_frames;
	__le64 rx_jbr_frames;
	__le64 rx_mtu_err_frames;
	__le64 rx_match_crc_frames;
	__le64 rx_promiscuous_frames;
	__le64 rx_tagged_frames;
	__le64 rx_double_tagged_frames;
	__le64 rx_trunc_frames;
	__le64 rx_good_frames;
	__le64 rx_pfc_xon2xoff_frames_pri0;
	__le64 rx_pfc_xon2xoff_frames_pri1;
	__le64 rx_pfc_xon2xoff_frames_pri2;
	__le64 rx_pfc_xon2xoff_frames_pri3;
	__le64 rx_pfc_xon2xoff_frames_pri4;
	__le64 rx_pfc_xon2xoff_frames_pri5;
	__le64 rx_pfc_xon2xoff_frames_pri6;
	__le64 rx_pfc_xon2xoff_frames_pri7;
	__le64 rx_pfc_ena_frames_pri0;
	__le64 rx_pfc_ena_frames_pri1;
	__le64 rx_pfc_ena_frames_pri2;
	__le64 rx_pfc_ena_frames_pri3;
	__le64 rx_pfc_ena_frames_pri4;
	__le64 rx_pfc_ena_frames_pri5;
	__le64 rx_pfc_ena_frames_pri6;
	__le64 rx_pfc_ena_frames_pri7;
	__le64 rx_sch_crc_err_frames;
	__le64 rx_undrsz_frames;
	__le64 rx_frag_frames;
	__le64 rx_eee_lpi_events;
	__le64 rx_eee_lpi_duration;
	__le64 rx_llfc_physical_msgs;
	__le64 rx_llfc_logical_msgs;
	__le64 rx_llfc_msgs_with_crc_err;
	__le64 rx_hcfc_msgs;
	__le64 rx_hcfc_msgs_with_crc_err;
	__le64 rx_bytes;
	__le64 rx_runt_bytes;
	__le64 rx_runt_frames;
	__le64 rx_stat_discard;
	__le64 rx_stat_err;
};

/* hwrm_ver_get */
/* Input (24 bytes) */
struct hwrm_ver_get_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	u8 hwrm_intf_maj;
	u8 hwrm_intf_min;
	u8 hwrm_intf_upd;
	u8 unused_0[5];
};

/* Output (128 bytes) */
struct hwrm_ver_get_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 hwrm_intf_maj;
	u8 hwrm_intf_min;
	u8 hwrm_intf_upd;
	u8 hwrm_intf_rsvd;
	u8 hwrm_fw_maj;
	u8 hwrm_fw_min;
	u8 hwrm_fw_bld;
	u8 hwrm_fw_rsvd;
819
820
821
822
823
824
825
826
827
828
829
830
831
	u8 mgmt_fw_maj;
	u8 mgmt_fw_min;
	u8 mgmt_fw_bld;
	u8 mgmt_fw_rsvd;
	u8 netctrl_fw_maj;
	u8 netctrl_fw_min;
	u8 netctrl_fw_bld;
	u8 netctrl_fw_rsvd;
	__le32 reserved1;
	u8 roce_fw_maj;
	u8 roce_fw_min;
	u8 roce_fw_bld;
	u8 roce_fw_rsvd;
832
	char hwrm_fw_name[16];
833
834
835
836
	char mgmt_fw_name[16];
	char netctrl_fw_name[16];
	__le32 reserved2[4];
	char roce_fw_name[16];
837
838
839
840
	__le16 chip_num;
	u8 chip_rev;
	u8 chip_metal;
	u8 chip_bond_id;
841
842
843
844
	u8 chip_platform_type;
	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC		   (0x0UL << 0)
	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA		   (0x1UL << 0)
	#define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM	   (0x2UL << 0)
845
846
847
	__le16 max_req_win_len;
	__le16 max_resp_len;
	__le16 def_req_timeout;
848
	u8 unused_0;
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_func_reset */
/* Input (24 bytes) */
struct hwrm_func_reset_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_RESET_REQ_ENABLES_VF_ID_VALID		    0x1UL
	__le16 vf_id;
865
866
867
868
869
870
	u8 func_reset_level;
	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL	   (0x0UL << 0)
	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME	   (0x1UL << 0)
	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN     (0x2UL << 0)
	#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF	   (0x3UL << 0)
	u8 unused_0;
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
};

/* Output (16 bytes) */
struct hwrm_func_reset_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_getfid */
/* Input (24 bytes) */
struct hwrm_func_getfid_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_GETFID_REQ_ENABLES_PCI_ID			    0x1UL
	__le16 pci_id;
	__le16 unused_0;
};

/* Output (16 bytes) */
struct hwrm_func_getfid_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 fid;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 unused_4;
	u8 valid;
};

/* hwrm_func_vf_alloc */
/* Input (24 bytes) */
struct hwrm_func_vf_alloc_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID		    0x1UL
	__le16 first_vf_id;
	__le16 num_vfs;
};

/* Output (16 bytes) */
struct hwrm_func_vf_alloc_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 first_vf_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 unused_4;
	u8 valid;
};

/* hwrm_func_vf_free */
/* Input (24 bytes) */
struct hwrm_func_vf_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID		    0x1UL
	__le16 first_vf_id;
	__le16 num_vfs;
};

/* Output (16 bytes) */
struct hwrm_func_vf_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_vf_cfg */
972
/* Input (32 bytes) */
973
974
975
976
977
978
979
980
981
struct hwrm_func_vf_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_VF_CFG_REQ_ENABLES_MTU			    0x1UL
	#define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN		    0x2UL
982
	#define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR		    0x4UL
983
	#define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR		    0x8UL
984
985
	__le16 mtu;
	__le16 guest_vlan;
986
	__le16 async_event_cr;
987
	u8 dflt_mac_addr[6];
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
};

/* Output (16 bytes) */
struct hwrm_func_vf_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_qcaps */
/* Input (24 bytes) */
struct hwrm_func_qcaps_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 fid;
	__le16 unused_0[3];
};

/* Output (80 bytes) */
struct hwrm_func_qcaps_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 fid;
	__le16 port_id;
	__le32 flags;
	#define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED	    0x1UL
	#define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING      0x2UL
1026
	#define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED		    0x4UL
1027
1028
1029
1030
	#define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED	    0x8UL
	#define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED	    0x10UL
	#define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED       0x20UL
	#define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED	    0x40UL
1031
	u8 mac_address[6];
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
	__le16 max_rsscos_ctx;
	__le16 max_cmpl_rings;
	__le16 max_tx_rings;
	__le16 max_rx_rings;
	__le16 max_l2_ctxs;
	__le16 max_vnics;
	__le16 first_vf_id;
	__le16 max_vfs;
	__le16 max_stat_ctx;
	__le32 max_encap_records;
	__le32 max_decap_records;
	__le32 max_tx_em_flows;
	__le32 max_tx_wm_flows;
	__le32 max_rx_em_flows;
	__le32 max_rx_wm_flows;
	__le32 max_mcast_filters;
	__le32 max_flow_id;
	__le32 max_hw_ring_grps;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
/* hwrm_func_qcfg */
/* Input (24 bytes) */
struct hwrm_func_qcfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 fid;
	__le16 unused_0[3];
};

/* Output (72 bytes) */
struct hwrm_func_qcfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 fid;
	__le16 port_id;
	__le16 vlan;
1077
1078
1079
	__le16 flags;
	#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED      0x1UL
	#define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED	    0x2UL
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
	u8 mac_address[6];
	__le16 pci_id;
	__le16 alloc_rsscos_ctx;
	__le16 alloc_cmpl_rings;
	__le16 alloc_tx_rings;
	__le16 alloc_rx_rings;
	__le16 alloc_l2_ctx;
	__le16 alloc_vnics;
	__le16 mtu;
	__le16 mru;
	__le16 stat_ctx_id;
	u8 port_partition_type;
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF		   (0x0UL << 0)
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS	   (0x1UL << 0)
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0	   (0x2UL << 0)
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5	   (0x3UL << 0)
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0	   (0x4UL << 0)
	#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN	   (0xffUL << 0)
1098
	u8 unused_0;
1099
	__le16 dflt_vnic_id;
1100
1101
	u8 unused_1;
	u8 unused_2;
1102
1103
1104
1105
1106
1107
	__le32 min_bw;
	__le32 max_bw;
	u8 evb_mode;
	#define FUNC_QCFG_RESP_EVB_MODE_NO_EVB			   (0x0UL << 0)
	#define FUNC_QCFG_RESP_EVB_MODE_VEB			   (0x1UL << 0)
	#define FUNC_QCFG_RESP_EVB_MODE_VEPA			   (0x2UL << 0)
1108
1109
	u8 unused_3;
	__le16 unused_4;
1110
1111
	__le32 alloc_mcast_filters;
	__le32 alloc_hw_ring_grps;
1112
1113
	u8 unused_5;
	u8 unused_6;
1114
1115
1116
1117
	u8 unused_7;
	u8 valid;
};

1118
1119
1120
1121
1122
1123
1124
1125
/* hwrm_func_cfg */
/* Input (88 bytes) */
struct hwrm_func_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
1126
	__le16 fid;
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
	u8 unused_0;
	u8 unused_1;
	__le32 flags;
	#define FUNC_CFG_REQ_FLAGS_PROM_MODE			    0x1UL
	#define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK		    0x2UL
	#define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK		    0x4UL
	#define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH		    0x8UL
	#define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH		    0x10UL
	#define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE		    0x20UL
	#define FUNC_CFG_REQ_FLAGS_DISABLE_STP			    0x40UL
	#define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP		    0x80UL
	#define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2		    0x100UL
	__le32 enables;
	#define FUNC_CFG_REQ_ENABLES_MTU			    0x1UL
	#define FUNC_CFG_REQ_ENABLES_MRU			    0x2UL
	#define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS		    0x4UL
	#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS		    0x8UL
	#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS		    0x10UL
	#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS		    0x20UL
	#define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS		    0x40UL
	#define FUNC_CFG_REQ_ENABLES_NUM_VNICS			    0x80UL
	#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS		    0x100UL
	#define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR		    0x200UL
	#define FUNC_CFG_REQ_ENABLES_DFLT_VLAN			    0x400UL
	#define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR		    0x800UL
	#define FUNC_CFG_REQ_ENABLES_MIN_BW			    0x1000UL
	#define FUNC_CFG_REQ_ENABLES_MAX_BW			    0x2000UL
	#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR		    0x4000UL
	#define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE	    0x8000UL
	#define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS		    0x10000UL
	#define FUNC_CFG_REQ_ENABLES_EVB_MODE			    0x20000UL
	#define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS		    0x40000UL
	#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS		    0x80000UL
	__le16 mtu;
	__le16 mru;
	__le16 num_rsscos_ctxs;
	__le16 num_cmpl_rings;
	__le16 num_tx_rings;
	__le16 num_rx_rings;
	__le16 num_l2_ctxs;
	__le16 num_vnics;
	__le16 num_stat_ctxs;
	__le16 num_hw_ring_grps;
	u8 dflt_mac_addr[6];
	__le16 dflt_vlan;
	__be32 dflt_ip_addr[4];
	__le32 min_bw;
	__le32 max_bw;
	__le16 async_event_cr;
	u8 vlan_antispoof_mode;
	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK	   (0x0UL << 0)
	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN    (0x1UL << 0)
	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE (0x2UL << 0)
	#define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0)
	u8 allowed_vlan_pris;
	u8 evb_mode;
	#define FUNC_CFG_REQ_EVB_MODE_NO_EVB			   (0x0UL << 0)
	#define FUNC_CFG_REQ_EVB_MODE_VEB			   (0x1UL << 0)
	#define FUNC_CFG_REQ_EVB_MODE_VEPA			   (0x2UL << 0)
	u8 unused_2;
	__le16 num_mcast_filters;
};

/* Output (16 bytes) */
struct hwrm_func_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_qstats */
/* Input (24 bytes) */
struct hwrm_func_qstats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 fid;
	__le16 unused_0[3];
};

/* Output (176 bytes) */
struct hwrm_func_qstats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le64 tx_ucast_pkts;
	__le64 tx_mcast_pkts;
	__le64 tx_bcast_pkts;
	__le64 tx_err_pkts;
	__le64 tx_drop_pkts;
	__le64 tx_ucast_bytes;
	__le64 tx_mcast_bytes;
	__le64 tx_bcast_bytes;
	__le64 rx_ucast_pkts;
	__le64 rx_mcast_pkts;
	__le64 rx_bcast_pkts;
	__le64 rx_err_pkts;
	__le64 rx_drop_pkts;
	__le64 rx_ucast_bytes;
	__le64 rx_mcast_bytes;
	__le64 rx_bcast_bytes;
	__le64 rx_agg_pkts;
	__le64 rx_agg_bytes;
	__le64 rx_agg_events;
	__le64 rx_agg_aborts;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_clr_stats */
/* Input (24 bytes) */
struct hwrm_func_clr_stats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 fid;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_func_clr_stats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_vf_resc_free */
/* Input (24 bytes) */
struct hwrm_func_vf_resc_free_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 vf_id;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_func_vf_resc_free_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_vf_vnic_ids_query */
/* Input (32 bytes) */
struct hwrm_func_vf_vnic_ids_query_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 vf_id;
	u8 unused_0;
	u8 unused_1;
	__le32 max_vnic_id_cnt;
	__le64 vnic_id_tbl_addr;
};

/* Output (16 bytes) */
struct hwrm_func_vf_vnic_ids_query_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 vnic_id_cnt;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_func_drv_rgtr */
/* Input (80 bytes) */
struct hwrm_func_drv_rgtr_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE		    0x1UL
	#define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE		    0x2UL
	__le32 enables;
	#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE		    0x1UL
	#define FUNC_DRV_RGTR_REQ_ENABLES_VER			    0x2UL
	#define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP		    0x4UL
	#define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD		    0x8UL
	#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD	    0x10UL
	__le16 os_type;
1344
1345
1346
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN		   (0x0UL << 0)
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER		   (0x1UL << 0)
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS		   (0xeUL << 0)
1347
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS		   (0x12UL << 0)
1348
1349
1350
1351
1352
1353
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS		   (0x1dUL << 0)
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX		   (0x24UL << 0)
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD		   (0x2aUL << 0)
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI			   (0x68UL << 0)
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864		   (0x73UL << 0)
	#define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2		   (0x74UL << 0)
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
	u8 ver_maj;
	u8 ver_min;
	u8 ver_upd;
	u8 unused_0;
	__le16 unused_1;
	__le32 timestamp;
	__le32 unused_2;
	__le32 vf_req_fwd[8];
	__le32 async_event_fwd[8];
};

/* Output (16 bytes) */
struct hwrm_func_drv_rgtr_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_drv_unrgtr */
/* Input (24 bytes) */
struct hwrm_func_drv_unrgtr_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN     0x1UL
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_func_drv_unrgtr_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_buf_rgtr */
/* Input (128 bytes) */
struct hwrm_func_buf_rgtr_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 enables;
	#define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID		    0x1UL
	#define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR		    0x2UL
	__le16 vf_id;
	__le16 req_buf_num_pages;
	__le16 req_buf_page_size;
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B	   (0x4UL << 0)
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K		   (0xcUL << 0)
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K		   (0xdUL << 0)
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K	   (0x10UL << 0)
1422
1423
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M		   (0x15UL << 0)
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M		   (0x16UL << 0)
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
	#define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G		   (0x1eUL << 0)
	__le16 req_buf_len;
	__le16 resp_buf_len;
	u8 unused_0;
	u8 unused_1;
	__le64 req_buf_page_addr0;
	__le64 req_buf_page_addr1;
	__le64 req_buf_page_addr2;
	__le64 req_buf_page_addr3;
	__le64 req_buf_page_addr4;
	__le64 req_buf_page_addr5;
	__le64 req_buf_page_addr6;
	__le64 req_buf_page_addr7;
	__le64 req_buf_page_addr8;
	__le64 req_buf_page_addr9;
	__le64 error_buf_addr;
	__le64 resp_buf_addr;
};

/* Output (16 bytes) */
struct hwrm_func_buf_rgtr_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_func_drv_qver */
/* Input (24 bytes) */
struct hwrm_func_drv_qver_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
1464
	__le32 reserved;
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
	__le16 fid;
	__le16 unused_0;
};

/* Output (16 bytes) */
struct hwrm_func_drv_qver_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 os_type;
1476
1477
1478
	#define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN		   (0x0UL << 0)
	#define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER		   (0x1UL << 0)
	#define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS		   (0xeUL << 0)
1479
	#define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS		   (0x12UL << 0)
1480
1481
1482
1483
1484
1485
	#define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS		   (0x1dUL << 0)
	#define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX		   (0x24UL << 0)
	#define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD		   (0x2aUL << 0)
	#define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI		   (0x68UL << 0)
	#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864		   (0x73UL << 0)
	#define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2		   (0x74UL << 0)
1486
1487
1488
1489
1490
1491
1492
1493
1494
	u8 ver_maj;
	u8 ver_min;
	u8 ver_upd;
	u8 unused_0;
	u8 unused_1;
	u8 valid;
};

/* hwrm_port_phy_cfg */
1495
/* Input (56 bytes) */
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
struct hwrm_port_phy_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY		    0x1UL
	#define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN		    0x2UL
	#define PORT_PHY_CFG_REQ_FLAGS_FORCE			    0x4UL
	#define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG		    0x8UL
1507
1508
1509
1510
	#define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE		    0x10UL
	#define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE		    0x20UL
	#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE	    0x40UL
	#define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE	    0x80UL
1511
1512
1513
1514
1515
1516
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE	    0x100UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE	    0x200UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE	    0x400UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE	    0x800UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE	    0x1000UL
	#define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE	    0x2000UL
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
	__le32 enables;
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE		    0x1UL
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX		    0x2UL
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE		    0x4UL
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED	    0x8UL
	#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK      0x10UL
	#define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED		    0x20UL
	#define PORT_PHY_CFG_REQ_ENABLES_LPBK			    0x40UL
	#define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS		    0x80UL
	#define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE		    0x100UL
1527
1528
	#define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK       0x200UL
	#define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER		    0x400UL
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
	__le16 port_id;
	__le16 force_link_speed;
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB	   (0x1UL << 0)
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB		   (0xaUL << 0)
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB		   (0x14UL << 0)
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB	   (0x19UL << 0)
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB		   (0x64UL << 0)
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB		   (0xc8UL << 0)
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB		   (0xfaUL << 0)
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB		   (0x190UL << 0)
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB		   (0x1f4UL << 0)
1540
1541
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB	   (0x3e8UL << 0)
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB		   (0xffffUL << 0)
1542
1543
1544
1545
1546
	u8 auto_mode;
	#define PORT_PHY_CFG_REQ_AUTO_MODE_NONE		   (0x0UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS		   (0x1UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED		   (0x2UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW	   (0x3UL << 0)
1547
	#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK		   (0x4UL << 0)
1548
1549
1550
1551
1552
1553
1554
	u8 auto_duplex;
	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF		   (0x0UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL		   (0x1UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH		   (0x2UL << 0)
	u8 auto_pause;
	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX			    0x1UL
	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX			    0x2UL
1555
	#define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE	    0x4UL
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
	u8 unused_0;
	__le16 auto_link_speed;
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB		   (0x1UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB		   (0xaUL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB		   (0x14UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB		   (0x19UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB		   (0x64UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB		   (0xc8UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB		   (0xfaUL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB		   (0x190UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB		   (0x1f4UL << 0)
1567
1568
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB		   (0x3e8UL << 0)
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB		   (0xffffUL << 0)
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
	__le16 auto_link_speed_mask;
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD      0x1UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB	    0x2UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD	    0x4UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB	    0x8UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB	    0x10UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB	    0x20UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB	    0x40UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB	    0x80UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB	    0x100UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB	    0x200UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB	    0x400UL
1581
1582
1583
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB	    0x800UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD       0x1000UL
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB	    0x2000UL
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
	u8 wirespeed;
	#define PORT_PHY_CFG_REQ_WIRESPEED_OFF			   (0x0UL << 0)
	#define PORT_PHY_CFG_REQ_WIRESPEED_ON			   (0x1UL << 0)
	u8 lpbk;
	#define PORT_PHY_CFG_REQ_LPBK_NONE			   (0x0UL << 0)
	#define PORT_PHY_CFG_REQ_LPBK_LOCAL			   (0x1UL << 0)
	#define PORT_PHY_CFG_REQ_LPBK_REMOTE			   (0x2UL << 0)
	u8 force_pause;
	#define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX		    0x1UL
	#define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX		    0x2UL
	u8 unused_1;
	__le32 preemphasis;
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
	__le16 eee_link_speed_mask;
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1	    0x1UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB	    0x2UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2	    0x4UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB	    0x8UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3	    0x10UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4	    0x20UL
	#define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB	    0x40UL
	u8 unused_2;
	u8 unused_3;
	__le32 tx_lpi_timer;
	__le32 unused_4;
	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK		    0xffffffUL
	#define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT		    0
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
};

/* Output (16 bytes) */
struct hwrm_port_phy_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_port_phy_qcfg */
/* Input (24 bytes) */
struct hwrm_port_phy_qcfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 port_id;
	__le16 unused_0[3];
};

1637
/* Output (96 bytes) */
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
struct hwrm_port_phy_qcfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 link;
	#define PORT_PHY_QCFG_RESP_LINK_NO_LINK		   (0x0UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SIGNAL			   (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_LINK			   (0x2UL << 0)
	u8 unused_0;
	__le16 link_speed;
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB		   (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB		   (0xaUL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB		   (0x14UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB		   (0x19UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB		   (0x64UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB		   (0xc8UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB		   (0xfaUL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB		   (0x190UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB		   (0x1f4UL << 0)
1658
1659
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB		   (0x3e8UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB		   (0xffffUL << 0)
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
	u8 duplex;
	#define PORT_PHY_QCFG_RESP_DUPLEX_HALF			   (0x0UL << 0)
	#define PORT_PHY_QCFG_RESP_DUPLEX_FULL			   (0x1UL << 0)
	u8 pause;
	#define PORT_PHY_QCFG_RESP_PAUSE_TX			    0x1UL
	#define PORT_PHY_QCFG_RESP_PAUSE_RX			    0x2UL
	__le16 support_speeds;
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD	    0x1UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB	    0x2UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD	    0x4UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB		    0x8UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB		    0x10UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB	    0x20UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB		    0x40UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB		    0x80UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB		    0x100UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB		    0x200UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB		    0x400UL
1678
1679
1680
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB	    0x800UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD	    0x1000UL
	#define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB		    0x2000UL
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
	__le16 force_link_speed;
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB	   (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB	   (0xaUL << 0)
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB	   (0x14UL << 0)
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB	   (0x19UL << 0)
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB	   (0x64UL << 0)
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB	   (0xc8UL << 0)
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB	   (0xfaUL << 0)
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB	   (0x190UL << 0)
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB	   (0x1f4UL << 0)
1691
1692
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB	   (0x3e8UL << 0)
	#define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB	   (0xffffUL << 0)
1693
1694
1695
1696
1697
	u8 auto_mode;
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE		   (0x0UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS	   (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED		   (0x2UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW	   (0x3UL << 0)
1698
	#define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK	   (0x4UL << 0)
1699
1700
1701
	u8 auto_pause;
	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX		    0x1UL
	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX		    0x2UL
1702
	#define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE	    0x4UL
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
	__le16 auto_link_speed;
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB	   (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB		   (0xaUL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB		   (0x14UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB	   (0x19UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB	   (0x64UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB	   (0xc8UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB	   (0xfaUL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB	   (0x190UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB	   (0x1f4UL << 0)
1713
1714
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB	   (0x3e8UL << 0)
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB	   (0xffffUL << 0)
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
	__le16 auto_link_speed_mask;
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD    0x1UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB      0x2UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD      0x4UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB	    0x8UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB	    0x10UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB      0x20UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB       0x40UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB       0x80UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB       0x100UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB       0x200UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB       0x400UL
1727
1728
1729
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB      0x800UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD     0x1000UL
	#define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB       0x2000UL
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
	u8 wirespeed;
	#define PORT_PHY_QCFG_RESP_WIRESPEED_OFF		   (0x0UL << 0)
	#define PORT_PHY_QCFG_RESP_WIRESPEED_ON		   (0x1UL << 0)
	u8 lpbk;
	#define PORT_PHY_QCFG_RESP_LPBK_NONE			   (0x0UL << 0)
	#define PORT_PHY_QCFG_RESP_LPBK_LOCAL			   (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_LPBK_REMOTE			   (0x2UL << 0)
	u8 force_pause;
	#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX		    0x1UL
	#define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX		    0x2UL
1740
1741
1742
1743
1744
1745
1746
	u8 module_status;
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE		   (0x0UL << 0)
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX	   (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG       (0x2UL << 0)
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN	   (0x3UL << 0)
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED      (0x4UL << 0)
	#define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE    (0xffUL << 0)
1747
1748
1749
1750
1751
	__le32 preemphasis;
	u8 phy_maj;
	u8 phy_min;
	u8 phy_bld;
	u8 phy_type;
1752
1753
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN		   (0x0UL << 0)
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR		   (0x1UL << 0)
1754
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4		   (0x2UL << 0)
1755
1756
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR		   (0x3UL << 0)
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR		   (0x4UL << 0)
1757
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2		   (0x5UL << 0)
1758
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX		   (0x6UL << 0)
1759
1760
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR		   (0x7UL << 0)
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET		   (0x8UL << 0)
1761
1762
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE		   (0x9UL << 0)
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY	   (0xaUL << 0)
1763
	u8 media_type;
1764
	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN		   (0x0UL << 0)
1765
1766
1767
	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP		   (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC		   (0x2UL << 0)
	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE		   (0x3UL << 0)
1768
1769
1770
1771
	u8 xcvr_pkg_type;
	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL    (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL    (0x2UL << 0)
	u8 eee_config_phy_addr;
1772
1773
	#define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK		    0x1fUL
	#define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT		    0
1774
1775
1776
1777
1778
1779
1780
1781
1782
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED	    0x20UL
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE	    0x40UL
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI	    0x80UL
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK		    0xe0UL
	#define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT		    5
	u8 parallel_detect;
	#define PORT_PHY_QCFG_RESP_PARALLEL_DETECT		    0x1UL
	#define PORT_PHY_QCFG_RESP_RESERVED_MASK		    0xfeUL
	#define PORT_PHY_QCFG_RESP_RESERVED_SFT		    1
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
	__le16 link_partner_adv_speeds;
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB   0x2UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD   0x4UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB     0x8UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB     0x10UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB   0x20UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB    0x40UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB    0x80UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB    0x100UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB    0x200UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB    0x400UL
1795
1796
1797
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB   0x800UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD  0x1000UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB    0x2000UL
1798
1799
1800
1801
1802
	u8 link_partner_adv_auto_mode;
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE (0x0UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED (0x2UL << 0)
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1803
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK (0x4UL << 0)
1804
1805
1806
	u8 link_partner_adv_pause;
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX       0x1UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX       0x2UL
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
	__le16 adv_eee_link_speed_mask;
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1   0x1UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB   0x2UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2   0x4UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB     0x8UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3   0x10UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4   0x20UL
	#define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB    0x40UL
	__le16 link_partner_adv_eee_link_speed_mask;
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL
	#define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL
	__le32 xcvr_identifier_type_tx_lpi_timer;
	#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK		    0xffffffUL
	#define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT		    0
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK       0xff000000UL
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT	    24
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN   (0x0UL << 24)
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP       (0x3UL << 24)
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP      (0xcUL << 24)
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS  (0xdUL << 24)
	#define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28    (0x11UL << 24)
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
	__le16 fec_cfg;
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED      0x1UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED   0x2UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED     0x4UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED  0x8UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED    0x10UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED  0x20UL
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED    0x40UL
	u8 unused_1;
	u8 unused_2;
1843
1844
	char phy_vendor_name[16];
	char phy_vendor_partnumber[16];
1845
	__le32 unused_3;
1846
1847
	u8 unused_4;
	u8 unused_5;
1848
	u8 unused_6;
1849
1850
1851
1852
	u8 valid;
};

/* hwrm_port_mac_cfg */
1853
/* Input (40 bytes) */
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
struct hwrm_port_mac_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK		    0x1UL
	#define PORT_MAC_CFG_REQ_FLAGS_COS_ASSIGNMENT_ENABLE       0x2UL
	#define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE       0x4UL
	#define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE	    0x8UL
1865
1866
1867
1868
	#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE    0x10UL
	#define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE   0x20UL
	#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE    0x40UL
	#define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE   0x80UL
1869
1870
	#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE		    0x100UL
	#define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE		    0x200UL
1871
1872
1873
1874
1875
1876
1877
	__le32 enables;
	#define PORT_MAC_CFG_REQ_ENABLES_IPG			    0x1UL
	#define PORT_MAC_CFG_REQ_ENABLES_LPBK			    0x2UL
	#define PORT_MAC_CFG_REQ_ENABLES_IVLAN_PRI2COS_MAP_PRI     0x4UL
	#define PORT_MAC_CFG_REQ_ENABLES_LCOS_MAP_PRI		    0x8UL
	#define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI    0x10UL
	#define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI	    0x20UL
1878
1879
	#define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL
	#define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
	__le16 port_id;
	u8 ipg;
	u8 lpbk;
	#define PORT_MAC_CFG_REQ_LPBK_NONE			   (0x0UL << 0)
	#define PORT_MAC_CFG_REQ_LPBK_LOCAL			   (0x1UL << 0)
	#define PORT_MAC_CFG_REQ_LPBK_REMOTE			   (0x2UL << 0)
	u8 ivlan_pri2cos_map_pri;
	u8 lcos_map_pri;
	u8 tunnel_pri2cos_map_pri;
	u8 dscp2pri_map_pri;
1890
1891
1892
	__le16 rx_ts_capture_ptp_msg_type;
	__le16 tx_ts_capture_ptp_msg_type;
	__le32 unused_0;
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
};

/* Output (16 bytes) */
struct hwrm_port_mac_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le16 mru;
	__le16 mtu;
	u8 ipg;
	u8 lpbk;
	#define PORT_MAC_CFG_RESP_LPBK_NONE			   (0x0UL << 0)
	#define PORT_MAC_CFG_RESP_LPBK_LOCAL			   (0x1UL << 0)
	#define PORT_MAC_CFG_RESP_LPBK_REMOTE			   (0x2UL << 0)
	u8 unused_0;
	u8 valid;
};

/* hwrm_port_qstats */
/* Input (40 bytes) */
struct hwrm_port_qstats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 port_id;
	u8 unused_0;
	u8 unused_1;
	u8 unused_2[3];
	u8 unused_3;
	__le64 tx_stat_host_addr;
	__le64 rx_stat_host_addr;
};

/* Output (16 bytes) */
struct hwrm_port_qstats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
1935
1936
1937
	__le16 tx_stat_size;
	__le16 rx_stat_size;
	u8 unused_0;
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
	u8 unused_1;
	u8 unused_2;
	u8 valid;
};

/* hwrm_port_lpbk_qstats */
/* Input (16 bytes) */
struct hwrm_port_lpbk_qstats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

1953
/* Output (96 bytes) */
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
struct hwrm_port_lpbk_qstats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le64 lpbk_ucast_frames;
	__le64 lpbk_mcast_frames;
	__le64 lpbk_bcast_frames;
	__le64 lpbk_ucast_bytes;
	__le64 lpbk_mcast_bytes;
	__le64 lpbk_bcast_bytes;
1965
1966
1967
1968
	__le64 tx_stat_discard;
	__le64 tx_stat_error;
	__le64 rx_stat_discard;
	__le64 rx_stat_error;
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_port_clr_stats */
/* Input (24 bytes) */
struct hwrm_port_clr_stats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 port_id;
	__le16 unused_0[3];
};

/* Output (16 bytes) */
struct hwrm_port_clr_stats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_port_lpbk_clr_stats */
/* Input (16 bytes) */
struct hwrm_port_lpbk_clr_stats_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
};

/* Output (16 bytes) */
struct hwrm_port_lpbk_clr_stats_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_port_blink_led */
/* Input (24 bytes) */
struct hwrm_port_blink_led_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 num_blinks;
	__le32 unused_0;
};

/* Output (16 bytes) */
struct hwrm_port_blink_led_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
/* hwrm_port_phy_qcaps */
/* Input (24 bytes) */
struct hwrm_port_phy_qcaps_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le16 port_id;
	__le16 unused_0[3];
};

/* Output (24 bytes) */
struct hwrm_port_phy_qcaps_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 eee_supported;
	#define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED		    0x1UL
	#define PORT_PHY_QCAPS_RESP_RSVD1_MASK			    0xfeUL
	#define PORT_PHY_QCAPS_RESP_RSVD1_SFT			    1
	u8 unused_0;
	__le16 supported_speeds_force_mode;
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL
	__le16 supported_speeds_auto_mode;
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL
	__le16 supported_speeds_eee_mode;
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB  0x8UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL
	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL
	__le32 tx_lpi_timer_low;
	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK	    0xffffffUL
	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT	    0
	#define PORT_PHY_QCAPS_RESP_RSVD2_MASK			    0xff000000UL
	#define PORT_PHY_QCAPS_RESP_RSVD2_SFT			    24
	__le32 valid_tx_lpi_timer_high;
	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK	    0xffffffUL
	#define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT	    0
	#define PORT_PHY_QCAPS_RESP_VALID_MASK			    0xff000000UL
	#define PORT_PHY_QCAPS_RESP_VALID_SFT			    24
};

2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
/* hwrm_port_phy_i2c_read */
/* Input (40 bytes) */
struct hwrm_port_phy_i2c_read_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	__le32 enables;
	#define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET	    0x1UL
	__le16 port_id;
	u8 i2c_slave_addr;
	u8 unused_0;
	__le16 page_number;
	__le16 page_offset;
	u8 data_length;
	u8 unused_1[7];
};

/* Output (80 bytes) */
struct hwrm_port_phy_i2c_read_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 data[16];
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

2156
/* hwrm_queue_qportcfg */
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
/* Input (24 bytes) */
struct hwrm_queue_qportcfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH			    0x1UL
	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX		   (0x0UL << 0)
	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX		   (0x1UL << 0)
2168
	#define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST    QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
	__le16 port_id;
	__le16 unused_0;
};

/* Output (32 bytes) */
struct hwrm_queue_qportcfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	u8 max_configurable_queues;
	u8 max_configurable_lossless_queues;
	u8 queue_cfg_allowed;
	u8 queue_buffers_cfg_allowed;
	u8 queue_pfcenable_cfg_allowed;
	u8 queue_pri2cos_cfg_allowed;
	u8 queue_cos2bw_cfg_allowed;
	u8 queue_id0;
	u8 queue_id0_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY (0x0UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
	u8 queue_id1;
	u8 queue_id1_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY (0x0UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
	u8 queue_id2;
	u8 queue_id2_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY (0x0UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
	u8 queue_id3;
	u8 queue_id3_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY (0x0UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
	u8 queue_id4;
	u8 queue_id4_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY (0x0UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
	u8 queue_id5;
	u8 queue_id5_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY (0x0UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
	u8 queue_id6;
	u8 queue_id6_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY (0x0UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
	u8 queue_id7;
	u8 queue_id7_service_profile;
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY (0x0UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
	#define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
	u8 valid;
};

/* hwrm_queue_cfg */
/* Input (40 bytes) */
struct hwrm_queue_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define QUEUE_CFG_REQ_FLAGS_PATH			    0x1UL
	#define QUEUE_CFG_REQ_FLAGS_PATH_TX			   (0x0UL << 0)
	#define QUEUE_CFG_REQ_FLAGS_PATH_RX			   (0x1UL << 0)
2241
	#define QUEUE_CFG_REQ_FLAGS_PATH_LAST    QUEUE_CFG_REQ_FLAGS_PATH_RX
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
	__le32 enables;
	#define QUEUE_CFG_REQ_ENABLES_DFLT_LEN			    0x1UL
	#define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE		    0x2UL
	__le32 queue_id;
	__le32 dflt_len;
	u8 service_profile;
	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY		   (0x0UL << 0)
	#define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS		   (0x1UL << 0)
	#define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN		   (0xffUL << 0)
	u8 unused_0[7];
};

/* Output (16 bytes) */
struct hwrm_queue_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_queue_buffers_cfg */
/* Input (56 bytes) */
struct hwrm_queue_buffers_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;
	__le32 flags;
	#define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH		    0x1UL
	#define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_TX		   (0x0UL << 0)
	#define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX		   (0x1UL << 0)
2279
	#define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_LAST    QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX
2280
2281
2282
	__le32 enables;
	#define QUEUE_BUFFERS_CFG_REQ_ENABLES_RESERVED		    0x1UL
	#define QUEUE_BUFFERS_CFG_REQ_ENABLES_SHARED		    0x2UL
2283
2284
2285
2286
2287
	#define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF		    0x4UL
	#define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON		    0x8UL
	#define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL		    0x10UL
	#define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL		    0x20UL
	#define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX		    0x40UL
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
	__le32 queue_id;
	__le32 reserved;
	__le32 shared;
	__le32 xoff;
	__le32 xon;
	__le32 full;
	__le32 notfull;
	__le32 max;
};

/* Output (16 bytes) */
struct hwrm_queue_buffers_cfg_output {
	__le16 error_code;
	__le16 req_type;
	__le16 seq_id;
	__le16 resp_len;
	__le32 unused_0;
	u8 unused_1;
	u8 unused_2;
	u8 unused_3;
	u8 valid;
};

/* hwrm_queue_pfcenable_cfg */
/* Input (24 bytes) */
struct hwrm_queue_pfcenable_cfg_input {
	__le16 req_type;
	__le16 cmpl_ring;
	__le16 seq_id;
	__le16 target_id;
	__le64 resp_addr;