ramgk104.c 48.5 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
/*
 * Copyright 2013 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
24
25
#define gk104_ram(p) container_of((p), struct gk104_ram, base)
#include "ram.h"
26
#include "ramfuc.h"
27

28
#include <core/option.h>
29
30
#include <subdev/bios.h>
#include <subdev/bios/init.h>
31
32
#include <subdev/bios/M0205.h>
#include <subdev/bios/M0209.h>
33
34
35
#include <subdev/bios/pll.h>
#include <subdev/bios/rammap.h>
#include <subdev/bios/timing.h>
36
37
#include <subdev/clk.h>
#include <subdev/clk/pll.h>
38
#include <subdev/gpio.h>
39

40
struct gk104_ramfuc {
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
	struct ramfuc base;

	struct nvbios_pll refpll;
	struct nvbios_pll mempll;

	struct ramfuc_reg r_gpioMV;
	u32 r_funcMV[2];
	struct ramfuc_reg r_gpio2E;
	u32 r_func2E[2];
	struct ramfuc_reg r_gpiotrig;

	struct ramfuc_reg r_0x132020;
	struct ramfuc_reg r_0x132028;
	struct ramfuc_reg r_0x132024;
	struct ramfuc_reg r_0x132030;
	struct ramfuc_reg r_0x132034;
	struct ramfuc_reg r_0x132000;
	struct ramfuc_reg r_0x132004;
	struct ramfuc_reg r_0x132040;

	struct ramfuc_reg r_0x10f248;
	struct ramfuc_reg r_0x10f290;
	struct ramfuc_reg r_0x10f294;
	struct ramfuc_reg r_0x10f298;
	struct ramfuc_reg r_0x10f29c;
	struct ramfuc_reg r_0x10f2a0;
	struct ramfuc_reg r_0x10f2a4;
	struct ramfuc_reg r_0x10f2a8;
	struct ramfuc_reg r_0x10f2ac;
	struct ramfuc_reg r_0x10f2cc;
	struct ramfuc_reg r_0x10f2e8;
	struct ramfuc_reg r_0x10f250;
	struct ramfuc_reg r_0x10f24c;
	struct ramfuc_reg r_0x10fec4;
	struct ramfuc_reg r_0x10fec8;
	struct ramfuc_reg r_0x10f604;
	struct ramfuc_reg r_0x10f614;
	struct ramfuc_reg r_0x10f610;
	struct ramfuc_reg r_0x100770;
	struct ramfuc_reg r_0x100778;
	struct ramfuc_reg r_0x10f224;

	struct ramfuc_reg r_0x10f870;
	struct ramfuc_reg r_0x10f698;
	struct ramfuc_reg r_0x10f694;
	struct ramfuc_reg r_0x10f6b8;
	struct ramfuc_reg r_0x10f808;
	struct ramfuc_reg r_0x10f670;
	struct ramfuc_reg r_0x10f60c;
	struct ramfuc_reg r_0x10f830;
	struct ramfuc_reg r_0x1373ec;
	struct ramfuc_reg r_0x10f800;
	struct ramfuc_reg r_0x10f82c;

	struct ramfuc_reg r_0x10f978;
	struct ramfuc_reg r_0x10f910;
	struct ramfuc_reg r_0x10f914;

	struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */

	struct ramfuc_reg r_0x62c000;
102

103
	struct ramfuc_reg r_0x10f200;
104

105
106
107
108
109
110
111
112
113
114
115
116
117
	struct ramfuc_reg r_0x10f210;
	struct ramfuc_reg r_0x10f310;
	struct ramfuc_reg r_0x10f314;
	struct ramfuc_reg r_0x10f318;
	struct ramfuc_reg r_0x10f090;
	struct ramfuc_reg r_0x10f69c;
	struct ramfuc_reg r_0x10f824;
	struct ramfuc_reg r_0x1373f0;
	struct ramfuc_reg r_0x1373f4;
	struct ramfuc_reg r_0x137320;
	struct ramfuc_reg r_0x10f65c;
	struct ramfuc_reg r_0x10f6bc;
	struct ramfuc_reg r_0x100710;
118
	struct ramfuc_reg r_0x100750;
119
120
};

121
122
123
struct gk104_ram {
	struct nvkm_ram base;
	struct gk104_ramfuc fuc;
124

125
	struct list_head cfg;
126
127
128
129
	u32 parts;
	u32 pmask;
	u32 pnuts;

130
	struct nvbios_ramcfg diff;
131
132
133
134
135
136
137
138
139
140
	int from;
	int mode;
	int N1, fN1, M1, P1;
	int N2, M2, P2;
};

/*******************************************************************************
 * GDDR5
 ******************************************************************************/
static void
141
gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data)
142
{
143
	struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
144
	u32 addr = 0x110974, i;
145

146
147
	ram_mask(fuc, 0x10f910, mask, data);
	ram_mask(fuc, 0x10f914, mask, data);
148

149
	for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
150
		if (ram->pmask & (1 << i))
151
			continue;
152
153
154
155
156
		ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
	}
}

static void
157
r1373f4_init(struct gk104_ramfuc *fuc)
158
{
159
	struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
	const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
	const u32 runk0 = ram->fN1 << 16;
	const u32 runk1 = ram->fN1;

	if (ram->from == 2) {
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
	} else {
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
	}

	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);

	/* (re)program refpll, if required */
	if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
	    (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
		ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
		ram_wr32(fuc, 0x137320, 0x00000000);
		ram_mask(fuc, 0x132030, 0xffff0000, runk0);
		ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
		ram_wr32(fuc, 0x132024, rcoef);
		ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
		ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
		ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
	}

	/* (re)program mempll, if required */
	if (ram->mode == 2) {
		ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
193
		ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
194
195
196
197
198
199
200
201
202
203
204
205
206
		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
		ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
		ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
		ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
	} else {
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
	}

	ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
}

static void
207
r1373f4_fini(struct gk104_ramfuc *fuc)
208
{
209
210
	struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
	struct nvkm_ram_data *next = ram->base.next;
211
212
	u8 v0 = next->bios.ramcfg_11_03_c0;
	u8 v1 = next->bios.ramcfg_11_03_30;
213
214
215
216
217
218
	u32 tmp;

	tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
	ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
	ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
	if (ram->mode == 2) {
219
220
		ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000002);
		ram_mask(fuc, 0x1373f4, 0x00001100, 0x00000000);
221
	} else {
222
223
		ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
		ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
224
225
226
227
	}
	ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
}

228
static void
229
230
gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg,
	       u32 _mask, u32 _data, u32 _copy)
231
{
232
	struct nvkm_fb *fb = ram->base.fb;
233
	struct ramfuc *fuc = &ram->fuc.base;
234
	struct nvkm_device *device = fb->subdev.device;
235
	u32 addr = 0x110000 + (reg->addr & 0xfff);
236
237
238
239
240
241
	u32 mask = _mask | _copy;
	u32 data = (_data & _mask) | (reg->data & _copy);
	u32 i;

	for (i = 0; i < 16; i++, addr += 0x1000) {
		if (ram->pnuts & (1 << i)) {
242
			u32 prev = nvkm_rd32(device, addr);
243
			u32 next = (prev & ~mask) | data;
244
			nvkm_memx_wr32(fuc->memx, addr, next);
245
246
247
248
		}
	}
}
#define ram_nuts(s,r,m,d,c)                                                    \
249
	gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
250

251
static int
252
gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq)
253
{
254
255
	struct gk104_ramfuc *fuc = &ram->fuc;
	struct nvkm_ram_data *next = ram->base.next;
256
257
	int vc = !next->bios.ramcfg_11_02_08;
	int mv = !next->bios.ramcfg_11_02_04;
258
	u32 mask, data;
259
260

	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
261
	ram_block(fuc);
262
263
264
	ram_wr32(fuc, 0x62c000, 0x0f0f0000);

	/* MR1: turn termination on early, for some reason.. */
265
	if ((ram->base.mr[1] & 0x03c) != 0x030) {
266
		ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
267
268
		ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
	}
269
270
271
272
273
274
275
276
277
278
279

	if (vc == 1 && ram_have(fuc, gpio2E)) {
		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
		if (temp != ram_rd32(fuc, gpio2E)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 20000);
		}
	}

	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);

280
	gk104_ram_train(fuc, 0x01020000, 0x000c0000);
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308

	ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
	ram_nsec(fuc, 1000);
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_nsec(fuc, 1000);

	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
	ram_wr32(fuc, 0x10f090, 0x00000061);
	ram_wr32(fuc, 0x10f090, 0xc000007f);
	ram_nsec(fuc, 1000);

	ram_wr32(fuc, 0x10f698, 0x00000000);
	ram_wr32(fuc, 0x10f69c, 0x00000000);

	/*XXX: there does appear to be some kind of condition here, simply
	 *     modifying these bits in the vbios from the default pl0
	 *     entries shows no change.  however, the data does appear to
	 *     be correct and may be required for the transition back
	 */
	mask = 0x800f07e0;
	data = 0x00030000;
	if (ram_rd32(fuc, 0x10f978) & 0x00800000)
		data |= 0x00040000;

	if (1) {
		data |= 0x800807e0;
309
310
311
312
313
		switch (next->bios.ramcfg_11_03_c0) {
		case 3: data &= ~0x00000040; break;
		case 2: data &= ~0x00000100; break;
		case 1: data &= ~0x80000000; break;
		case 0: data &= ~0x00000400; break;
314
315
		}

316
317
318
319
320
		switch (next->bios.ramcfg_11_03_30) {
		case 3: data &= ~0x00000020; break;
		case 2: data &= ~0x00000080; break;
		case 1: data &= ~0x00080000; break;
		case 0: data &= ~0x00000200; break;
321
322
323
		}
	}

324
	if (next->bios.ramcfg_11_02_80)
325
		mask |= 0x03000000;
326
	if (next->bios.ramcfg_11_02_40)
327
		mask |= 0x00002000;
328
	if (next->bios.ramcfg_11_07_10)
329
		mask |= 0x00004000;
330
	if (next->bios.ramcfg_11_07_08)
331
332
333
334
335
336
337
338
339
340
341
342
		mask |= 0x00000003;
	else {
		mask |= 0x34000000;
		if (ram_rd32(fuc, 0x10f978) & 0x00800000)
			mask |= 0x40000000;
	}
	ram_mask(fuc, 0x10f824, mask, data);

	ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);

	if (ram->from == 2 && ram->mode != 2) {
		ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
343
		ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
344
345
346
347
348
		ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
		ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
		r1373f4_init(fuc);
		ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
349
		r1373f4_fini(fuc);
350
351
352
353
		ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
	} else
	if (ram->from != 2 && ram->mode != 2) {
		r1373f4_init(fuc);
354
		r1373f4_fini(fuc);
355
356
357
358
359
360
361
362
363
364
	}

	if (ram_have(fuc, gpioMV)) {
		u32 temp  = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
		if (temp != ram_rd32(fuc, gpioMV)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 64000);
		}
	}

365
366
	if (next->bios.ramcfg_11_02_40 ||
	    next->bios.ramcfg_11_07_10) {
367
368
369
370
371
		ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
		ram_nsec(fuc, 20000);
	}

	if (ram->from != 2 && ram->mode == 2) {
372
373
		if (0 /*XXX: Titan */)
			ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
374
375
376
377
		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
		ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
		ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
		r1373f4_init(fuc);
378
		r1373f4_fini(fuc);
379
380
381
382
383
384
		ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
		ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
	} else
	if (ram->from == 2 && ram->mode == 2) {
		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
		r1373f4_init(fuc);
385
		r1373f4_fini(fuc);
386
387
388
	}

	if (ram->mode != 2) /*XXX*/ {
389
		if (next->bios.ramcfg_11_07_40)
390
391
392
			ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
	}

393
394
395
	ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
	ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
	ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
396

Ben Skeggs's avatar
Ben Skeggs committed
397
	if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
398
399
		ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
		ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
Ben Skeggs's avatar
Ben Skeggs committed
400
401
402
403
	} else
	if (!next->bios.ramcfg_11_07_08) {
		ram_wr32(fuc, 0x10f698, 0x00000000);
		ram_wr32(fuc, 0x10f69c, 0x00000000);
404
405
406
	}

	if (ram->mode != 2) {
407
408
409
		u32 data = 0x01000100 * next->bios.ramcfg_11_04;
		ram_nuke(fuc, 0x10f694);
		ram_mask(fuc, 0x10f694, 0xff00ff00, data);
410
411
	}

412
	if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
413
414
415
416
417
418
419
		data = 0x00000080;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f60c, 0x00000080, data);

	mask = 0x00070000;
	data = 0x00000000;
420
	if (!next->bios.ramcfg_11_02_80)
421
		data |= 0x03000000;
422
	if (!next->bios.ramcfg_11_02_40)
423
		data |= 0x00002000;
424
	if (!next->bios.ramcfg_11_07_10)
425
		data |= 0x00004000;
426
	if (!next->bios.ramcfg_11_07_08)
427
428
429
430
431
		data |= 0x00000003;
	else
		data |= 0x74000000;
	ram_mask(fuc, 0x10f824, mask, data);

432
	if (next->bios.ramcfg_11_01_08)
433
434
435
436
437
438
439
440
441
442
		data = 0x00000000;
	else
		data = 0x00001000;
	ram_mask(fuc, 0x10f200, 0x00001000, data);

	if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
		ram_nsec(fuc, 10000);
		ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
	}

443
	if (next->bios.ramcfg_11_08_01)
444
445
446
447
448
449
		data = 0x00100000;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f82c, 0x00100000, data);

	data = 0x00000000;
450
	if (next->bios.ramcfg_11_08_08)
451
		data |= 0x00002000;
452
	if (next->bios.ramcfg_11_08_04)
453
		data |= 0x00001000;
454
	if (next->bios.ramcfg_11_08_02)
455
456
457
458
		data |= 0x00004000;
	ram_mask(fuc, 0x10f830, 0x00007000, data);

	/* PFB timing */
459
460
461
462
463
464
465
466
467
468
469
	ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
	ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
	ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
	ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
	ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
	ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
	ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
	ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
	ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
	ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
	ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
470

471
	data = mask = 0x00000000;
472
	if (ram->diff.ramcfg_11_08_20) {
473
474
475
476
477
478
		if (next->bios.ramcfg_11_08_20)
			data |= 0x01000000;
		mask |= 0x01000000;
	}
	ram_mask(fuc, 0x10f200, mask, data);

479
	data = mask = 0x00000000;
480
	if (ram->diff.ramcfg_11_02_03) {
481
		data |= next->bios.ramcfg_11_02_03 << 8;
482
483
		mask |= 0x00000300;
	}
484
	if (ram->diff.ramcfg_11_01_10) {
485
		if (next->bios.ramcfg_11_01_10)
486
			data |= 0x70000000;
487
488
489
		mask |= 0x70000000;
	}
	ram_mask(fuc, 0x10f604, mask, data);
490

491
	data = mask = 0x00000000;
492
	if (ram->diff.timing_20_30_07) {
493
		data |= next->bios.timing_20_30_07 << 28;
494
495
		mask |= 0x70000000;
	}
496
	if (ram->diff.ramcfg_11_01_01) {
497
		if (next->bios.ramcfg_11_01_01)
498
			data |= 0x00000100;
499
500
501
		mask |= 0x00000100;
	}
	ram_mask(fuc, 0x10f614, mask, data);
502

503
	data = mask = 0x00000000;
504
	if (ram->diff.timing_20_30_07) {
505
		data |= next->bios.timing_20_30_07 << 28;
506
507
		mask |= 0x70000000;
	}
508
	if (ram->diff.ramcfg_11_01_02) {
509
		if (next->bios.ramcfg_11_01_02)
510
			data |= 0x00000100;
511
		mask |= 0x00000100;
512
	}
513
	ram_mask(fuc, 0x10f610, mask, data);
514
515
516

	mask = 0x33f00000;
	data = 0x00000000;
517
	if (!next->bios.ramcfg_11_01_04)
518
		data |= 0x20200000;
519
	if (!next->bios.ramcfg_11_07_80)
520
521
522
523
		data |= 0x12800000;
	/*XXX: see note above about there probably being some condition
	 *     for the 10f824 stuff that uses ramcfg 3...
	 */
524
	if (next->bios.ramcfg_11_03_f0) {
525
		if (next->bios.rammap_11_08_0c) {
526
			if (!next->bios.ramcfg_11_07_80)
527
528
529
530
531
532
533
534
535
536
537
538
				mask |= 0x00000020;
			else
				data |= 0x00000020;
			mask |= 0x00000004;
		}
	} else {
		mask |= 0x40000020;
		data |= 0x00000004;
	}

	ram_mask(fuc, 0x10f808, mask, data);

539
	ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
540

541
	data = mask = 0x00000000;
542
	if (ram->diff.ramcfg_11_02_03) {
543
		data |= next->bios.ramcfg_11_02_03;
544
545
		mask |= 0x00000003;
	}
546
	if (ram->diff.ramcfg_11_01_10) {
547
		if (next->bios.ramcfg_11_01_10)
548
549
550
551
552
553
			data |= 0x00000004;
		mask |= 0x00000004;
	}

	if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
		ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
554
555
556
557
		ram_wr32(fuc, 0x100710, 0x00000000);
		ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
	}

558
	data = next->bios.timing_20_30_07 << 8;
559
	if (next->bios.ramcfg_11_01_01)
560
561
562
		data |= 0x80000000;
	ram_mask(fuc, 0x100778, 0x00000700, data);

563
	ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
564
565
566
567
	data = (next->bios.timing[10] & 0x7f000000) >> 24;
	if (data < next->bios.timing_20_2c_1fc0)
		data = next->bios.timing_20_2c_1fc0;
	ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
568
	ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
569

570
571
572
573
574
575
	ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
					    next->bios.timing_20_31_0780 << 17 |
					    next->bios.timing_20_31_0078 << 8 |
					    next->bios.timing_20_31_0007);
	ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
					    next->bios.timing_20_31_7000);
576
577

	ram_wr32(fuc, 0x10f090, 0x4000007e);
578
	ram_nsec(fuc, 2000);
579
580
581
582
	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */

583
	if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
584
		u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
585
		gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
586
587
588
589
590
591
592
593
594
		ram_nsec(fuc, 1000);
		ram_wr32(fuc, 0x10f294, temp);
	}

	ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
	ram_wr32(fuc, mr[0], ram->base.mr[0]);
	ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
	ram_nsec(fuc, 1000);
	ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
595
	ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
	ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
	ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);

	if (vc == 0 && ram_have(fuc, gpio2E)) {
		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
		if (temp != ram_rd32(fuc, gpio2E)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 20000);
		}
	}

	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
	ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
	ram_nsec(fuc, 1000);
611
	ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
612
613
614
615

	data  = ram_rd32(fuc, 0x10f978);
	data &= ~0x00046144;
	data |=  0x0000000b;
616
617
	if (!next->bios.ramcfg_11_07_08) {
		if (!next->bios.ramcfg_11_07_04)
618
619
620
621
622
623
624
625
626
627
628
629
630
			data |= 0x0000200c;
		else
			data |= 0x00000000;
	} else {
		data |= 0x00040044;
	}
	ram_wr32(fuc, 0x10f978, data);

	if (ram->mode == 1) {
		data = ram_rd32(fuc, 0x10f830) | 0x00000001;
		ram_wr32(fuc, 0x10f830, data);
	}

631
	if (!next->bios.ramcfg_11_07_08) {
632
		data = 0x88020000;
633
		if ( next->bios.ramcfg_11_07_04)
634
			data |= 0x10000000;
635
		if (!next->bios.rammap_11_08_10)
636
637
638
639
			data |= 0x00080000;
	} else {
		data = 0xa40e0000;
	}
640
	gk104_ram_train(fuc, 0xbc0f0000, data);
641
642
	if (1) /* XXX: not always? */
		ram_nsec(fuc, 1000);
643
644
645
646
647

	if (ram->mode == 2) { /*XXX*/
		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
	}

648
649
650
	/* LP3 */
	if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
		ram_nsec(fuc, 1000);
651
652
653
654
655
656

	if (ram->mode != 2) {
		ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
	}

657
	if (next->bios.ramcfg_11_07_02)
658
		gk104_ram_train(fuc, 0x80020000, 0x01000000);
659

660
	ram_unblock(fuc);
661
662
	ram_wr32(fuc, 0x62c000, 0x0f0f0f00);

663
	if (next->bios.rammap_11_08_01)
664
665
666
667
		data = 0x00000800;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f200, 0x00000800, data);
668
	ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
669
670
671
672
673
674
675
	return 0;
}

/*******************************************************************************
 * DDR3
 ******************************************************************************/

676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
static void
nvkm_sddr3_dll_reset(struct gk104_ramfuc *fuc)
{
	ram_nuke(fuc, mr[0]);
	ram_mask(fuc, mr[0], 0x100, 0x100);
	ram_mask(fuc, mr[0], 0x100, 0x000);
}

static void
nvkm_sddr3_dll_disable(struct gk104_ramfuc *fuc)
{
	u32 mr1_old = ram_rd32(fuc, mr[1]);

	if (!(mr1_old & 0x1)) {
		ram_mask(fuc, mr[1], 0x1, 0x1);
		ram_nsec(fuc, 1000);
	}
}

695
static int
696
gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq)
697
{
698
	struct gk104_ramfuc *fuc = &ram->fuc;
699
700
701
	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
	const u32 runk0 = ram->fN1 << 16;
	const u32 runk1 = ram->fN1;
702
	struct nvkm_ram_data *next = ram->base.next;
703
704
	int vc = !next->bios.ramcfg_11_02_08;
	int mv = !next->bios.ramcfg_11_02_04;
705
706
707
	u32 mask, data;

	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
708
	ram_block(fuc);
709
710
711
712
713
714
715
716
717
718
719
	ram_wr32(fuc, 0x62c000, 0x0f0f0000);

	if (vc == 1 && ram_have(fuc, gpio2E)) {
		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
		if (temp != ram_rd32(fuc, gpio2E)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 20000);
		}
	}

	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
720
	if (next->bios.ramcfg_11_03_f0)
721
722
723
		ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);

	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
724
725
726
727

	if (next->bios.ramcfg_DLLoff)
		nvkm_sddr3_dll_disable(fuc);

728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
	ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
	ram_nsec(fuc, 1000);

	ram_wr32(fuc, 0x10f090, 0x00000060);
	ram_wr32(fuc, 0x10f090, 0xc000007e);

	/*XXX: there does appear to be some kind of condition here, simply
	 *     modifying these bits in the vbios from the default pl0
	 *     entries shows no change.  however, the data does appear to
	 *     be correct and may be required for the transition back
	 */
	mask = 0x00010000;
	data = 0x00010000;

	if (1) {
		mask |= 0x800807e0;
		data |= 0x800807e0;
749
750
751
752
753
		switch (next->bios.ramcfg_11_03_c0) {
		case 3: data &= ~0x00000040; break;
		case 2: data &= ~0x00000100; break;
		case 1: data &= ~0x80000000; break;
		case 0: data &= ~0x00000400; break;
754
755
		}

756
757
758
759
760
		switch (next->bios.ramcfg_11_03_30) {
		case 3: data &= ~0x00000020; break;
		case 2: data &= ~0x00000080; break;
		case 1: data &= ~0x00080000; break;
		case 0: data &= ~0x00000200; break;
761
762
763
		}
	}

764
	if (next->bios.ramcfg_11_02_80)
765
		mask |= 0x03000000;
766
	if (next->bios.ramcfg_11_02_40)
767
		mask |= 0x00002000;
768
	if (next->bios.ramcfg_11_07_10)
769
		mask |= 0x00004000;
770
	if (next->bios.ramcfg_11_07_08)
771
772
773
774
775
776
777
778
779
		mask |= 0x00000003;
	else
		mask |= 0x14000000;
	ram_mask(fuc, 0x10f824, mask, data);

	ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);

	ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
	data  = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
780
	data |= next->bios.ramcfg_11_03_30 << 16;
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
	ram_wr32(fuc, 0x1373ec, data);
	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);

	/* (re)program refpll, if required */
	if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
	    (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
		ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
		ram_wr32(fuc, 0x137320, 0x00000000);
		ram_mask(fuc, 0x132030, 0xffff0000, runk0);
		ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
		ram_wr32(fuc, 0x132024, rcoef);
		ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
		ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
		ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
	}

	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
	ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);

	if (ram_have(fuc, gpioMV)) {
		u32 temp  = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
		if (temp != ram_rd32(fuc, gpioMV)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 64000);
		}
	}

812
813
	if (next->bios.ramcfg_11_02_40 ||
	    next->bios.ramcfg_11_07_10) {
814
815
816
817
818
		ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
		ram_nsec(fuc, 20000);
	}

	if (ram->mode != 2) /*XXX*/ {
819
		if (next->bios.ramcfg_11_07_40)
820
821
822
			ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
	}

823
824
825
	ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
	ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
	ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
826
827
828

	mask = 0x00010000;
	data = 0x00000000;
829
	if (!next->bios.ramcfg_11_02_80)
830
		data |= 0x03000000;
831
	if (!next->bios.ramcfg_11_02_40)
832
		data |= 0x00002000;
833
	if (!next->bios.ramcfg_11_07_10)
834
		data |= 0x00004000;
835
	if (!next->bios.ramcfg_11_07_08)
836
837
838
839
840
841
		data |= 0x00000003;
	else
		data |= 0x14000000;
	ram_mask(fuc, 0x10f824, mask, data);
	ram_nsec(fuc, 1000);

842
	if (next->bios.ramcfg_11_08_01)
843
844
845
846
847
848
		data = 0x00100000;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f82c, 0x00100000, data);

	/* PFB timing */
849
850
851
852
853
854
855
856
857
858
859
	ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
	ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
	ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
	ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
	ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
	ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
	ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
	ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
	ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
	ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
	ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
860
861
862

	mask = 0x33f00000;
	data = 0x00000000;
863
	if (!next->bios.ramcfg_11_01_04)
864
		data |= 0x20200000;
865
	if (!next->bios.ramcfg_11_07_80)
866
867
868
869
		data |= 0x12800000;
	/*XXX: see note above about there probably being some condition
	 *     for the 10f824 stuff that uses ramcfg 3...
	 */
870
	if (next->bios.ramcfg_11_03_f0) {
871
		if (next->bios.rammap_11_08_0c) {
872
			if (!next->bios.ramcfg_11_07_80)
873
874
875
876
877
878
879
880
881
882
883
884
885
				mask |= 0x00000020;
			else
				data |= 0x00000020;
			mask |= 0x08000004;
		}
		data |= 0x04000000;
	} else {
		mask |= 0x44000020;
		data |= 0x08000004;
	}

	ram_mask(fuc, 0x10f808, mask, data);

886
	ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
887

888
	ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
889

890
	data = (next->bios.timing[10] & 0x7f000000) >> 24;
891
	if (data < next->bios.timing_20_2c_1fc0)
892
		data = next->bios.timing_20_2c_1fc0;
893
894
	ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);

895
	ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
896
897
898
899
900
901
902
903
904

	ram_wr32(fuc, 0x10f090, 0x4000007f);
	ram_nsec(fuc, 1000);

	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
	ram_nsec(fuc, 1000);

905
906
907
908
	if (!next->bios.ramcfg_DLLoff) {
		ram_mask(fuc, mr[1], 0x1, 0x0);
		nvkm_sddr3_dll_reset(fuc);
	}
909

910
911
	ram_mask(fuc, mr[2], 0x00000fff, ram->base.mr[2]);
	ram_mask(fuc, mr[1], 0xffffffff, ram->base.mr[1]);
912
913
914
	ram_wr32(fuc, mr[0], ram->base.mr[0]);
	ram_nsec(fuc, 1000);

915
916
917
918
	if (!next->bios.ramcfg_DLLoff) {
		nvkm_sddr3_dll_reset(fuc);
		ram_nsec(fuc, 1000);
	}
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937

	if (vc == 0 && ram_have(fuc, gpio2E)) {
		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
		if (temp != ram_rd32(fuc, gpio2E)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 20000);
		}
	}

	if (ram->mode != 2) {
		ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
	}

	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
	ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
	ram_nsec(fuc, 1000);

938
	ram_unblock(fuc);
939
940
	ram_wr32(fuc, 0x62c000, 0x0f0f0f00);

941
	if (next->bios.rammap_11_08_01)
942
943
944
945
946
947
948
949
950
951
952
953
		data = 0x00000800;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f200, 0x00000800, data);
	return 0;
}

/*******************************************************************************
 * main hooks
 ******************************************************************************/

static int
954
gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data)
955
{
956
	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
957
	struct nvkm_ram_data *cfg;
958
959
960
961
962
963
964
965
	u32 mhz = khz / 1000;

	list_for_each_entry(cfg, &ram->cfg, head) {
		if (mhz >= cfg->bios.rammap_min &&
		    mhz <= cfg->bios.rammap_max) {
			*data = *cfg;
			data->freq = khz;
			return 0;
966
967
968
		}
	}

969
	nvkm_error(subdev, "ramcfg data for %dMHz not found\n", mhz);
970
	return -EINVAL;
971
972
}

973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
static int
gk104_calc_pll_output(int fN, int M, int N, int P, int clk)
{
	return ((clk * N) + (((u16)(fN + 4096) * clk) >> 13)) / (M * P);
}

static int
gk104_pll_calc_hiclk(int target_khz, int crystal,
		int *N1, int *fN1, int *M1, int *P1,
		int *N2, int *M2, int *P2)
{
	int best_clk = 0, best_err = target_khz, p_ref, n_ref;
	bool upper = false;

	*M1 = 1;
	/* M has to be 1, otherwise it gets unstable */
	*M2 = 1;
	/* can be 1 or 2, sticking with 1 for simplicity */
	*P2 = 1;

	for (p_ref = 0x7; p_ref >= 0x5; --p_ref) {
		for (n_ref = 0x25; n_ref <= 0x2b; ++n_ref) {
			int cur_N, cur_clk, cur_err;

			cur_clk = gk104_calc_pll_output(0, 1, n_ref, p_ref, crystal);
			cur_N = target_khz / cur_clk;
			cur_err = target_khz
				- gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk);

			/* we found a better combination */
			if (cur_err < best_err) {
				best_err = cur_err;
				best_clk = cur_clk;
				*N2 = cur_N;
				*N1 = n_ref;
				*P1 = p_ref;
				upper = false;
			}

			cur_N += 1;
			cur_err = gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk)
				- target_khz;
			if (cur_err < best_err) {
				best_err = cur_err;
				best_clk = cur_clk;
				*N2 = cur_N;
				*N1 = n_ref;
				*P1 = p_ref;
				upper = true;
			}
		}
	}

	/* adjust fN to get closer to the target clock */
	*fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal);
	if (upper)
		*fN1 = (u16)(1 - *fN1);

	return gk104_calc_pll_output(*fN1, 1, *N1, *P1, crystal);
}

1034
static int
1035
gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next)
1036
{
1037
	struct gk104_ramfuc *fuc = &ram->fuc;
1038
	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
1039
1040
	int refclk, i;
	int ret;
1041

1042
	ret = ram_init(fuc, ram->base.fb);
1043
1044
1045
	if (ret)
		return ret;

1046
	ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
	ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;

	/* XXX: this is *not* what nvidia do.  on fermi nvidia generally
	 * select, based on some unknown condition, one of the two possible
	 * reference frequencies listed in the vbios table for mempll and
	 * program refpll to that frequency.
	 *
	 * so far, i've seen very weird values being chosen by nvidia on
	 * kepler boards, no idea how/why they're chosen.
	 */
1057
	refclk = next->freq;
1058
	if (ram->mode == 2) {
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
		ret = gk104_pll_calc_hiclk(next->freq, subdev->device->crystal,
				&ram->N1, &ram->fN1, &ram->M1, &ram->P1,
				&ram->N2, &ram->M2, &ram->P2);
		fuc->mempll.refclk = ret;
		if (ret <= 0) {
			nvkm_error(subdev, "unable to calc plls\n");
			return -EINVAL;
		}
		nvkm_debug(subdev, "sucessfully calced PLLs for clock %i kHz"
				" (refclock: %i kHz)\n", next->freq, ret);
	} else {
		/* calculate refpll coefficients */
		ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1,
				     &ram->fN1, &ram->M1, &ram->P1);
		fuc->mempll.refclk = ret;
1074
		if (ret <= 0) {
1075
			nvkm_error(subdev, "unable to calc refpll\n");
1076
1077
1078
1079
1080
1081
1082
1083
			return -EINVAL;
		}
	}

	for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
		if (ram_have(fuc, mr[i]))
			ram->base.mr[i] = ram_rd32(fuc, mr[i]);
	}
1084
	ram->base.freq = next->freq;
1085
1086

	switch (ram->base.type) {
1087
	case NVKM_RAM_TYPE_DDR3:
1088
		ret = nvkm_sddr3_calc(&ram->base);
1089
		if (ret == 0)
1090
			ret = gk104_ram_calc_sddr3(ram, next->freq);
1091
		break;
1092
	case NVKM_RAM_TYPE_GDDR5:
1093
		ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0);
1094
		if (ret == 0)
1095
			ret = gk104_ram_calc_gddr5(ram, next->freq);
1096
1097
1098
1099
1100
1101
1102
1103
1104
		break;
	default:
		ret = -ENOSYS;
		break;
	}

	return ret;
}

1105
static int
1106
gk104_ram_calc(struct nvkm_ram *base, u32 freq)
1107
{
1108
1109
	struct gk104_ram *ram = gk104_ram(base);
	struct nvkm_clk *clk = ram->base.fb->subdev.device->clk;
1110
1111
	struct nvkm_ram_data *xits = &ram->base.xition;
	struct nvkm_ram_data *copy;
1112
1113
1114
	int ret;

	if (ram->base.next == NULL) {
1115
1116
		ret = gk104_ram_calc_data(ram,
					  nvkm_clk_read(clk, nv_clk_src_mem),
1117
					  &ram->base.former);
1118
1119
1120
		if (ret)
			return ret;

1121
		ret = gk104_ram_calc_data(ram, freq, &ram->base.target);
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
		if (ret)
			return ret;

		if (ram->base.target.freq < ram->base.former.freq) {
			*xits = ram->base.target;
			copy = &ram->base.former;
		} else {
			*xits = ram->base.former;
			copy = &ram->base.target;
		}

		xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
		xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
		xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;

		ram->base.next = &ram->base.target;
		if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
			ram->base.next = &ram->base.xition;
	} else {
		BUG_ON(ram->base.next != &ram->base.xition);
		ram->base.next = &ram->base.target;
	}

1145
	return gk104_ram_calc_xits(ram, ram->base.next);
1146
1147
}

1148
static void
1149
gk104_ram_prog_0(struct gk104_ram *ram, u32 freq)
1150
{
1151
	struct nvkm_device *device = ram->base.fb->subdev.device;
1152
	struct nvkm_ram_data *cfg;
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
	u32 mhz = freq / 1000;
	u32 mask, data;

	list_for_each_entry(cfg, &ram->cfg, head) {
		if (mhz >= cfg->bios.rammap_min &&
		    mhz <= cfg->bios.rammap_max)
			break;
	}

	if (&cfg->head == &ram->cfg)
		return;

	if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) {
		data |= cfg->bios.rammap_11_0a_03fe << 12;
		mask |= 0x001ff000;
	}
	if (ram->diff.rammap_11_09_01ff) {
		data |= cfg->bios.rammap_11_09_01ff;
		mask |= 0x000001ff;
	}
1173
	nvkm_mask(device, 0x10f468, mask, data);
1174
1175
1176
1177
1178

	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) {
		data |= cfg->bios.rammap_11_0a_0400;
		mask |= 0x00000001;
	}
1179
	nvkm_mask(device, 0x10f420, mask, data);
1180
1181
1182
1183
1184

	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) {
		data |= cfg->bios.rammap_11_0a_0800;
		mask |= 0x00000001;
	}
1185
	nvkm_mask(device, 0x10f430, mask, data);
1186
1187
1188
1189
1190

	if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) {
		data |= cfg->bios.rammap_11_0b_01f0;
		mask |= 0x0000001f;
	}
1191
	nvkm_mask(device, 0x10f400, mask, data);
1192
1193
1194
1195
1196

	if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) {
		data |= cfg->bios.rammap_11_0b_0200 << 9;
<