bugs.c 33.3 KB
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// SPDX-License-Identifier: GPL-2.0
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/*
 *  Copyright (C) 1994  Linus Torvalds
 *
 *  Cyrix stuff, June 1998 by:
 *	- Rafael R. Reilova (moved everything from head.S),
 *        <rreilova@ececs.uc.edu>
 *	- Channing Corn (tests & fixes),
 *	- Andrew D. Balsa (code cleanup).
 */
#include <linux/init.h>
#include <linux/utsname.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <linux/nospec.h>
#include <linux/prctl.h>
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#include <linux/sched/smt.h>
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#include <asm/spec-ctrl.h>
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#include <asm/cmdline.h>
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#include <asm/bugs.h>
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#include <asm/processor.h>
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#include <asm/processor-flags.h>
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#include <asm/fpu/internal.h>
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#include <asm/msr.h>
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#include <asm/vmx.h>
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#include <asm/paravirt.h>
#include <asm/alternative.h>
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#include <asm/pgtable.h>
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#include <asm/set_memory.h>
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#include <asm/intel-family.h>
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#include <asm/e820/api.h>
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#include <asm/hypervisor.h>
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#include "cpu.h"

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static void __init spectre_v2_select_mitigation(void);
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static void __init ssb_select_mitigation(void);
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static void __init l1tf_select_mitigation(void);
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/* The base value of the SPEC_CTRL MSR that always has to be preserved. */
u64 x86_spec_ctrl_base;
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EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
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static DEFINE_MUTEX(spec_ctrl_mutex);
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/*
 * The vendor and possibly platform specific bits which can be modified in
 * x86_spec_ctrl_base.
 */
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static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
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/*
 * AMD specific MSR info for Speculative Store Bypass control.
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 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
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 */
u64 __ro_after_init x86_amd_ls_cfg_base;
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u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
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/* Control conditional STIBP in switch_to() */
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DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
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/* Control conditional IBPB in switch_mm() */
DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
/* Control unconditional IBPB in switch_mm() */
DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
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void __init check_bugs(void)
{
	identify_boot_cpu();
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	/*
	 * identify_boot_cpu() initialized SMT support information, let the
	 * core code know.
	 */
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	cpu_smt_check_topology_early();
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	if (!IS_ENABLED(CONFIG_SMP)) {
		pr_info("CPU: ");
		print_cpu_info(&boot_cpu_data);
	}

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	/*
	 * Read the SPEC_CTRL MSR to account for reserved bits which may
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	 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
	 * init code as it is not enumerated and depends on the family.
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	 */
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	if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
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		rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

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	/* Allow STIBP in MSR_SPEC_CTRL if supported */
	if (boot_cpu_has(X86_FEATURE_STIBP))
		x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;

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	/* Select the proper spectre mitigation before patching alternatives */
	spectre_v2_select_mitigation();

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	/*
	 * Select proper mitigation for any exposure to the Speculative Store
	 * Bypass vulnerability.
	 */
	ssb_select_mitigation();

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	l1tf_select_mitigation();

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#ifdef CONFIG_X86_32
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	/*
	 * Check whether we are able to run this kernel safely on SMP.
	 *
	 * - i386 is no longer supported.
	 * - In order to run on anything without a TSC, we need to be
	 *   compiled for a i486.
	 */
	if (boot_cpu_data.x86 < 4)
		panic("Kernel requires i486+ for 'invlpg' and other features");

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	init_utsname()->machine[1] =
		'0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
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	alternative_instructions();
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	fpu__init_check_bugs();
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#else /* CONFIG_X86_64 */
	alternative_instructions();

	/*
	 * Make sure the first 2MB area is not mapped by huge pages
	 * There are typically fixed size MTRRs in there and overlapping
	 * MTRRs into large pages causes slow downs.
	 *
	 * Right now we don't do that with gbpages because there seems
	 * very little benefit for that case.
	 */
	if (!direct_gbpages)
		set_memory_4k((unsigned long)__va(0), 1);
#endif
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}
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void
x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
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{
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	u64 msrval, guestval, hostval = x86_spec_ctrl_base;
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	struct thread_info *ti = current_thread_info();
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	/* Is MSR_SPEC_CTRL implemented ? */
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	if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
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		/*
		 * Restrict guest_spec_ctrl to supported values. Clear the
		 * modifiable bits in the host base value and or the
		 * modifiable bits from the guest value.
		 */
		guestval = hostval & ~x86_spec_ctrl_mask;
		guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;

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		/* SSBD controlled in MSR_SPEC_CTRL */
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		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
		    static_cpu_has(X86_FEATURE_AMD_SSBD))
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			hostval |= ssbd_tif_to_spec_ctrl(ti->flags);
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		/* Conditional STIBP enabled? */
		if (static_branch_unlikely(&switch_to_cond_stibp))
			hostval |= stibp_tif_to_spec_ctrl(ti->flags);

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		if (hostval != guestval) {
			msrval = setguest ? guestval : hostval;
			wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
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		}
	}
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	/*
	 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
	 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
	 */
	if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
	    !static_cpu_has(X86_FEATURE_VIRT_SSBD))
		return;

	/*
	 * If the host has SSBD mitigation enabled, force it in the host's
	 * virtual MSR value. If its not permanently enabled, evaluate
	 * current's TIF_SSBD thread flag.
	 */
	if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
		hostval = SPEC_CTRL_SSBD;
	else
		hostval = ssbd_tif_to_spec_ctrl(ti->flags);

	/* Sanitize the guest value */
	guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;

	if (hostval != guestval) {
		unsigned long tif;

		tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
				 ssbd_spec_ctrl_to_tif(hostval);

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		speculation_ctrl_update(tif);
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	}
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}
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EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
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static void x86_amd_ssb_disable(void)
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{
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	u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
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	if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
		wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
	else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
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		wrmsrl(MSR_AMD64_LS_CFG, msrval);
}

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#undef pr_fmt
#define pr_fmt(fmt)     "Spectre V2 : " fmt

static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
	SPECTRE_V2_NONE;

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static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init =
	SPECTRE_V2_USER_NONE;

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#ifdef CONFIG_RETPOLINE
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static bool spectre_v2_bad_module;

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bool retpoline_module_ok(bool has_retpoline)
{
	if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
		return true;

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	pr_err("System may be vulnerable to spectre v2\n");
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	spectre_v2_bad_module = true;
	return false;
}
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static inline const char *spectre_v2_module_string(void)
{
	return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
}
#else
static inline const char *spectre_v2_module_string(void) { return ""; }
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#endif
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static inline bool match_option(const char *arg, int arglen, const char *opt)
{
	int len = strlen(opt);

	return len == arglen && !strncmp(arg, opt, len);
}

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/* The kernel command line selection for spectre v2 */
enum spectre_v2_mitigation_cmd {
	SPECTRE_V2_CMD_NONE,
	SPECTRE_V2_CMD_AUTO,
	SPECTRE_V2_CMD_FORCE,
	SPECTRE_V2_CMD_RETPOLINE,
	SPECTRE_V2_CMD_RETPOLINE_GENERIC,
	SPECTRE_V2_CMD_RETPOLINE_AMD,
};

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enum spectre_v2_user_cmd {
	SPECTRE_V2_USER_CMD_NONE,
	SPECTRE_V2_USER_CMD_AUTO,
	SPECTRE_V2_USER_CMD_FORCE,
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	SPECTRE_V2_USER_CMD_PRCTL,
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	SPECTRE_V2_USER_CMD_PRCTL_IBPB,
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	SPECTRE_V2_USER_CMD_SECCOMP,
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	SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
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};

static const char * const spectre_v2_user_strings[] = {
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	[SPECTRE_V2_USER_NONE]			= "User space: Vulnerable",
	[SPECTRE_V2_USER_STRICT]		= "User space: Mitigation: STIBP protection",
	[SPECTRE_V2_USER_STRICT_PREFERRED]	= "User space: Mitigation: STIBP always-on protection",
	[SPECTRE_V2_USER_PRCTL]			= "User space: Mitigation: STIBP via prctl",
	[SPECTRE_V2_USER_SECCOMP]		= "User space: Mitigation: STIBP via seccomp and prctl",
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};

static const struct {
	const char			*option;
	enum spectre_v2_user_cmd	cmd;
	bool				secure;
} v2_user_options[] __initdata = {
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	{ "auto",		SPECTRE_V2_USER_CMD_AUTO,		false },
	{ "off",		SPECTRE_V2_USER_CMD_NONE,		false },
	{ "on",			SPECTRE_V2_USER_CMD_FORCE,		true  },
	{ "prctl",		SPECTRE_V2_USER_CMD_PRCTL,		false },
	{ "prctl,ibpb",		SPECTRE_V2_USER_CMD_PRCTL_IBPB,		false },
	{ "seccomp",		SPECTRE_V2_USER_CMD_SECCOMP,		false },
	{ "seccomp,ibpb",	SPECTRE_V2_USER_CMD_SECCOMP_IBPB,	false },
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};

static void __init spec_v2_user_print_cond(const char *reason, bool secure)
{
	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
		pr_info("spectre_v2_user=%s forced on command line.\n", reason);
}

static enum spectre_v2_user_cmd __init
spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd)
{
	char arg[20];
	int ret, i;

	switch (v2_cmd) {
	case SPECTRE_V2_CMD_NONE:
		return SPECTRE_V2_USER_CMD_NONE;
	case SPECTRE_V2_CMD_FORCE:
		return SPECTRE_V2_USER_CMD_FORCE;
	default:
		break;
	}

	ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
				  arg, sizeof(arg));
	if (ret < 0)
		return SPECTRE_V2_USER_CMD_AUTO;

	for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
		if (match_option(arg, ret, v2_user_options[i].option)) {
			spec_v2_user_print_cond(v2_user_options[i].option,
						v2_user_options[i].secure);
			return v2_user_options[i].cmd;
		}
	}

	pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
	return SPECTRE_V2_USER_CMD_AUTO;
}

static void __init
spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
{
	enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
	bool smt_possible = IS_ENABLED(CONFIG_SMP);
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	enum spectre_v2_user_cmd cmd;
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	if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
		return;

	if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
	    cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
		smt_possible = false;

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	cmd = spectre_v2_parse_user_cmdline(v2_cmd);
	switch (cmd) {
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	case SPECTRE_V2_USER_CMD_NONE:
		goto set_mode;
	case SPECTRE_V2_USER_CMD_FORCE:
		mode = SPECTRE_V2_USER_STRICT;
		break;
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	case SPECTRE_V2_USER_CMD_PRCTL:
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	case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
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		mode = SPECTRE_V2_USER_PRCTL;
		break;
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	case SPECTRE_V2_USER_CMD_AUTO:
	case SPECTRE_V2_USER_CMD_SECCOMP:
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	case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
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		if (IS_ENABLED(CONFIG_SECCOMP))
			mode = SPECTRE_V2_USER_SECCOMP;
		else
			mode = SPECTRE_V2_USER_PRCTL;
		break;
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	}

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	/*
	 * At this point, an STIBP mode other than "off" has been set.
	 * If STIBP support is not being forced, check if STIBP always-on
	 * is preferred.
	 */
	if (mode != SPECTRE_V2_USER_STRICT &&
	    boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
		mode = SPECTRE_V2_USER_STRICT_PREFERRED;

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	/* Initialize Indirect Branch Prediction Barrier */
	if (boot_cpu_has(X86_FEATURE_IBPB)) {
		setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
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		switch (cmd) {
		case SPECTRE_V2_USER_CMD_FORCE:
		case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
		case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
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			static_branch_enable(&switch_mm_always_ibpb);
			break;
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		case SPECTRE_V2_USER_CMD_PRCTL:
		case SPECTRE_V2_USER_CMD_AUTO:
		case SPECTRE_V2_USER_CMD_SECCOMP:
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			static_branch_enable(&switch_mm_cond_ibpb);
			break;
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		default:
			break;
		}

		pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
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			static_key_enabled(&switch_mm_always_ibpb) ?
			"always-on" : "conditional");
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	}

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	/* If enhanced IBRS is enabled no STIBP required */
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	if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
		return;

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	/*
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	 * If SMT is not possible or STIBP is not available clear the STIBP
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	 * mode.
	 */
	if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP))
		mode = SPECTRE_V2_USER_NONE;
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set_mode:
	spectre_v2_user = mode;
	/* Only print the STIBP mode when SMT possible */
	if (smt_possible)
		pr_info("%s\n", spectre_v2_user_strings[mode]);
}

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static const char * const spectre_v2_strings[] = {
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	[SPECTRE_V2_NONE]			= "Vulnerable",
	[SPECTRE_V2_RETPOLINE_GENERIC]		= "Mitigation: Full generic retpoline",
	[SPECTRE_V2_RETPOLINE_AMD]		= "Mitigation: Full AMD retpoline",
	[SPECTRE_V2_IBRS_ENHANCED]		= "Mitigation: Enhanced IBRS",
};

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static const struct {
	const char *option;
	enum spectre_v2_mitigation_cmd cmd;
	bool secure;
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} mitigation_options[] __initdata = {
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	{ "off",		SPECTRE_V2_CMD_NONE,		  false },
	{ "on",			SPECTRE_V2_CMD_FORCE,		  true  },
	{ "retpoline",		SPECTRE_V2_CMD_RETPOLINE,	  false },
	{ "retpoline,amd",	SPECTRE_V2_CMD_RETPOLINE_AMD,	  false },
	{ "retpoline,generic",	SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
	{ "auto",		SPECTRE_V2_CMD_AUTO,		  false },
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};

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static void __init spec_v2_print_cond(const char *reason, bool secure)
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{
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	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
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		pr_info("%s selected on command line.\n", reason);
}

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static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
{
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	enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
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	char arg[20];
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	int ret, i;

	if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
		return SPECTRE_V2_CMD_NONE;

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	ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
	if (ret < 0)
		return SPECTRE_V2_CMD_AUTO;

	for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
		if (!match_option(arg, ret, mitigation_options[i].option))
			continue;
		cmd = mitigation_options[i].cmd;
		break;
	}

	if (i >= ARRAY_SIZE(mitigation_options)) {
		pr_err("unknown option (%s). Switching to AUTO select\n", arg);
		return SPECTRE_V2_CMD_AUTO;
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	}

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	if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
	     cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
	     cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
	    !IS_ENABLED(CONFIG_RETPOLINE)) {
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		pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
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		return SPECTRE_V2_CMD_AUTO;
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	}

	if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
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	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON &&
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	    boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
		pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
		return SPECTRE_V2_CMD_AUTO;
	}

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	spec_v2_print_cond(mitigation_options[i].option,
			   mitigation_options[i].secure);
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	return cmd;
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}

static void __init spectre_v2_select_mitigation(void)
{
	enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
	enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;

	/*
	 * If the CPU is not affected and the command line mode is NONE or AUTO
	 * then nothing to do.
	 */
	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
	    (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
		return;

	switch (cmd) {
	case SPECTRE_V2_CMD_NONE:
		return;

	case SPECTRE_V2_CMD_FORCE:
	case SPECTRE_V2_CMD_AUTO:
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		if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
			mode = SPECTRE_V2_IBRS_ENHANCED;
			/* Force it so VMEXIT will restore correctly */
			x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
			wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
			goto specv2_set_mode;
		}
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		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_auto;
		break;
511
512
513
514
515
516
517
518
519
520
521
522
523
	case SPECTRE_V2_CMD_RETPOLINE_AMD:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_amd;
		break;
	case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_generic;
		break;
	case SPECTRE_V2_CMD_RETPOLINE:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_auto;
		break;
	}
524
	pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
525
526
527
	return;

retpoline_auto:
528
529
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
530
531
	retpoline_amd:
		if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
532
			pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
533
534
			goto retpoline_generic;
		}
535
		mode = SPECTRE_V2_RETPOLINE_AMD;
536
537
538
539
		setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	} else {
	retpoline_generic:
540
		mode = SPECTRE_V2_RETPOLINE_GENERIC;
541
542
543
		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	}

544
specv2_set_mode:
545
546
	spectre_v2_enabled = mode;
	pr_info("%s\n", spectre_v2_strings[mode]);
547
548

	/*
549
550
551
	 * If spectre v2 protection has been enabled, unconditionally fill
	 * RSB during a context switch; this protects against two independent
	 * issues:
552
	 *
553
554
	 *	- RSB underflow (and switch to BTB) on Skylake+
	 *	- SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs
555
	 */
556
557
	setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
	pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
558

559
560
	/*
	 * Retpoline means the kernel is safe because it has no indirect
561
562
563
564
565
566
567
568
	 * branches. Enhanced IBRS protects firmware too, so, enable restricted
	 * speculation around firmware calls only when Enhanced IBRS isn't
	 * supported.
	 *
	 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
	 * the user might select retpoline on the kernel command line and if
	 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
	 * enable IBRS around firmware calls.
569
	 */
570
	if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) {
571
572
573
		setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
		pr_info("Enabling Restricted Speculation for firmware calls\n");
	}
574

575
576
577
	/* Set up IBPB and STIBP depending on the general spectre V2 command */
	spectre_v2_user_select_mitigation(cmd);

578
579
	/* Enable STIBP if appropriate */
	arch_smt_update();
580
581
}

582
static void update_stibp_msr(void * __unused)
583
{
584
	wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
585
586
}

587
588
/* Update x86_spec_ctrl_base in case SMT state changed. */
static void update_stibp_strict(void)
589
{
590
591
592
593
594
595
596
597
598
599
600
601
	u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;

	if (sched_smt_active())
		mask |= SPEC_CTRL_STIBP;

	if (mask == x86_spec_ctrl_base)
		return;

	pr_info("Update user space SMT mitigation: STIBP %s\n",
		mask & SPEC_CTRL_STIBP ? "always-on" : "off");
	x86_spec_ctrl_base = mask;
	on_each_cpu(update_stibp_msr, NULL, 1);
602
603
}

604
605
606
607
608
609
610
611
612
/* Update the static key controlling the evaluation of TIF_SPEC_IB */
static void update_indir_branch_cond(void)
{
	if (sched_smt_active())
		static_branch_enable(&switch_to_cond_stibp);
	else
		static_branch_disable(&switch_to_cond_stibp);
}

613
614
void arch_smt_update(void)
{
615
616
	/* Enhanced IBRS implies STIBP. No update required. */
	if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
617
618
619
620
		return;

	mutex_lock(&spec_ctrl_mutex);

621
622
623
624
	switch (spectre_v2_user) {
	case SPECTRE_V2_USER_NONE:
		break;
	case SPECTRE_V2_USER_STRICT:
625
	case SPECTRE_V2_USER_STRICT_PREFERRED:
626
627
		update_stibp_strict();
		break;
628
	case SPECTRE_V2_USER_PRCTL:
629
	case SPECTRE_V2_USER_SECCOMP:
630
		update_indir_branch_cond();
631
		break;
632
	}
633

634
635
636
	mutex_unlock(&spec_ctrl_mutex);
}

637
638
639
#undef pr_fmt
#define pr_fmt(fmt)	"Speculative Store Bypass: " fmt

640
static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
641
642
643
644
645
646

/* The kernel command line selection */
enum ssb_mitigation_cmd {
	SPEC_STORE_BYPASS_CMD_NONE,
	SPEC_STORE_BYPASS_CMD_AUTO,
	SPEC_STORE_BYPASS_CMD_ON,
647
	SPEC_STORE_BYPASS_CMD_PRCTL,
648
	SPEC_STORE_BYPASS_CMD_SECCOMP,
649
650
};

651
static const char * const ssb_strings[] = {
652
	[SPEC_STORE_BYPASS_NONE]	= "Vulnerable",
653
	[SPEC_STORE_BYPASS_DISABLE]	= "Mitigation: Speculative Store Bypass disabled",
654
655
	[SPEC_STORE_BYPASS_PRCTL]	= "Mitigation: Speculative Store Bypass disabled via prctl",
	[SPEC_STORE_BYPASS_SECCOMP]	= "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
656
657
658
659
660
};

static const struct {
	const char *option;
	enum ssb_mitigation_cmd cmd;
661
} ssb_mitigation_options[]  __initdata = {
662
663
664
665
666
	{ "auto",	SPEC_STORE_BYPASS_CMD_AUTO },    /* Platform decides */
	{ "on",		SPEC_STORE_BYPASS_CMD_ON },      /* Disable Speculative Store Bypass */
	{ "off",	SPEC_STORE_BYPASS_CMD_NONE },    /* Don't touch Speculative Store Bypass */
	{ "prctl",	SPEC_STORE_BYPASS_CMD_PRCTL },   /* Disable Speculative Store Bypass via prctl */
	{ "seccomp",	SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
};

static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
{
	enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
	char arg[20];
	int ret, i;

	if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
		return SPEC_STORE_BYPASS_CMD_NONE;
	} else {
		ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
					  arg, sizeof(arg));
		if (ret < 0)
			return SPEC_STORE_BYPASS_CMD_AUTO;

		for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
			if (!match_option(arg, ret, ssb_mitigation_options[i].option))
				continue;

			cmd = ssb_mitigation_options[i].cmd;
			break;
		}

		if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
			pr_err("unknown option (%s). Switching to AUTO select\n", arg);
			return SPEC_STORE_BYPASS_CMD_AUTO;
		}
	}

	return cmd;
}

700
static enum ssb_mitigation __init __ssb_select_mitigation(void)
701
702
703
704
{
	enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
	enum ssb_mitigation_cmd cmd;

705
	if (!boot_cpu_has(X86_FEATURE_SSBD))
706
707
708
709
710
711
712
713
714
715
		return mode;

	cmd = ssb_parse_cmdline();
	if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
	    (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
	     cmd == SPEC_STORE_BYPASS_CMD_AUTO))
		return mode;

	switch (cmd) {
	case SPEC_STORE_BYPASS_CMD_AUTO:
716
717
718
719
720
721
722
723
724
	case SPEC_STORE_BYPASS_CMD_SECCOMP:
		/*
		 * Choose prctl+seccomp as the default mode if seccomp is
		 * enabled.
		 */
		if (IS_ENABLED(CONFIG_SECCOMP))
			mode = SPEC_STORE_BYPASS_SECCOMP;
		else
			mode = SPEC_STORE_BYPASS_PRCTL;
725
		break;
726
727
728
	case SPEC_STORE_BYPASS_CMD_ON:
		mode = SPEC_STORE_BYPASS_DISABLE;
		break;
729
730
731
	case SPEC_STORE_BYPASS_CMD_PRCTL:
		mode = SPEC_STORE_BYPASS_PRCTL;
		break;
732
733
734
735
	case SPEC_STORE_BYPASS_CMD_NONE:
		break;
	}

736
737
738
	/*
	 * We have three CPU feature flags that are in play here:
	 *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
739
	 *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
740
741
	 *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
	 */
742
	if (mode == SPEC_STORE_BYPASS_DISABLE) {
743
		setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
744
		/*
745
746
		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
		 * use a completely different MSR and bit dependent on family.
747
		 */
748
749
		if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
		    !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
750
			x86_amd_ssb_disable();
751
		} else {
752
			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
753
			x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
754
			wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
755
756
757
		}
	}

758
759
760
	return mode;
}

761
static void ssb_select_mitigation(void)
762
763
764
765
766
767
768
{
	ssb_mode = __ssb_select_mitigation();

	if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
		pr_info("%s\n", ssb_strings[ssb_mode]);
}

769
#undef pr_fmt
770
#define pr_fmt(fmt)     "Speculation prctl: " fmt
771

772
static void task_update_spec_tif(struct task_struct *tsk)
773
{
774
775
	/* Force the update of the real TIF bits */
	set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
776
777
778
779
780
781
782
783
784

	/*
	 * Immediately update the speculation control MSRs for the current
	 * task, but for a non-current task delay setting the CPU
	 * mitigation until it is scheduled next.
	 *
	 * This can only happen for SECCOMP mitigation. For PRCTL it's
	 * always the current task.
	 */
785
	if (tsk == current)
786
787
788
789
790
		speculation_ctrl_update_current();
}

static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
{
791
792
	if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
	    ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
793
794
		return -ENXIO;

795
796
797
798
799
800
	switch (ctrl) {
	case PR_SPEC_ENABLE:
		/* If speculation is force disabled, enable is not allowed */
		if (task_spec_ssb_force_disable(task))
			return -EPERM;
		task_clear_spec_ssb_disable(task);
801
		task_update_spec_tif(task);
802
803
804
		break;
	case PR_SPEC_DISABLE:
		task_set_spec_ssb_disable(task);
805
		task_update_spec_tif(task);
806
807
808
809
		break;
	case PR_SPEC_FORCE_DISABLE:
		task_set_spec_ssb_disable(task);
		task_set_spec_ssb_force_disable(task);
810
		task_update_spec_tif(task);
811
812
813
814
		break;
	default:
		return -ERANGE;
	}
815
816
817
	return 0;
}

818
819
820
821
822
823
824
825
826
827
static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
{
	switch (ctrl) {
	case PR_SPEC_ENABLE:
		if (spectre_v2_user == SPECTRE_V2_USER_NONE)
			return 0;
		/*
		 * Indirect branch speculation is always disabled in strict
		 * mode.
		 */
828
829
		if (spectre_v2_user == SPECTRE_V2_USER_STRICT ||
		    spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED)
830
831
832
833
834
835
836
837
838
839
840
841
			return -EPERM;
		task_clear_spec_ib_disable(task);
		task_update_spec_tif(task);
		break;
	case PR_SPEC_DISABLE:
	case PR_SPEC_FORCE_DISABLE:
		/*
		 * Indirect branch speculation is always allowed when
		 * mitigation is force disabled.
		 */
		if (spectre_v2_user == SPECTRE_V2_USER_NONE)
			return -EPERM;
842
843
		if (spectre_v2_user == SPECTRE_V2_USER_STRICT ||
		    spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED)
844
845
846
847
848
849
850
851
852
853
854
855
			return 0;
		task_set_spec_ib_disable(task);
		if (ctrl == PR_SPEC_FORCE_DISABLE)
			task_set_spec_ib_force_disable(task);
		task_update_spec_tif(task);
		break;
	default:
		return -ERANGE;
	}
	return 0;
}

856
857
858
859
860
861
int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
			     unsigned long ctrl)
{
	switch (which) {
	case PR_SPEC_STORE_BYPASS:
		return ssb_prctl_set(task, ctrl);
862
863
	case PR_SPEC_INDIRECT_BRANCH:
		return ib_prctl_set(task, ctrl);
864
865
866
867
868
869
870
871
	default:
		return -ENODEV;
	}
}

#ifdef CONFIG_SECCOMP
void arch_seccomp_spec_mitigate(struct task_struct *task)
{
872
873
	if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
		ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
874
875
	if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP)
		ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
876
877
878
}
#endif

879
static int ssb_prctl_get(struct task_struct *task)
880
881
882
883
{
	switch (ssb_mode) {
	case SPEC_STORE_BYPASS_DISABLE:
		return PR_SPEC_DISABLE;
884
	case SPEC_STORE_BYPASS_SECCOMP:
885
	case SPEC_STORE_BYPASS_PRCTL:
886
887
888
		if (task_spec_ssb_force_disable(task))
			return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
		if (task_spec_ssb_disable(task))
889
890
891
892
893
894
895
896
897
			return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
	default:
		if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
			return PR_SPEC_ENABLE;
		return PR_SPEC_NOT_AFFECTED;
	}
}

898
899
900
901
902
903
904
905
906
static int ib_prctl_get(struct task_struct *task)
{
	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
		return PR_SPEC_NOT_AFFECTED;

	switch (spectre_v2_user) {
	case SPECTRE_V2_USER_NONE:
		return PR_SPEC_ENABLE;
	case SPECTRE_V2_USER_PRCTL:
907
	case SPECTRE_V2_USER_SECCOMP:
908
909
910
911
912
913
		if (task_spec_ib_force_disable(task))
			return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
		if (task_spec_ib_disable(task))
			return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
	case SPECTRE_V2_USER_STRICT:
914
	case SPECTRE_V2_USER_STRICT_PREFERRED:
915
916
917
918
919
920
		return PR_SPEC_DISABLE;
	default:
		return PR_SPEC_NOT_AFFECTED;
	}
}

921
int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
922
923
924
{
	switch (which) {
	case PR_SPEC_STORE_BYPASS:
925
		return ssb_prctl_get(task);
926
927
	case PR_SPEC_INDIRECT_BRANCH:
		return ib_prctl_get(task);
928
929
930
931
932
	default:
		return -ENODEV;
	}
}

933
934
void x86_spec_ctrl_setup_ap(void)
{
935
	if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
936
		wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
937
938

	if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
939
		x86_amd_ssb_disable();
940
941
}

942
943
#undef pr_fmt
#define pr_fmt(fmt)	"L1TF: " fmt
944

945
946
/* Default mitigation for L1TF-affected CPUs */
enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
947
#if IS_ENABLED(CONFIG_KVM_INTEL)
948
EXPORT_SYMBOL_GPL(l1tf_mitigation);
949
#endif
950
enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
951
952
EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);

953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
/*
 * These CPUs all support 44bits physical address space internally in the
 * cache but CPUID can report a smaller number of physical address bits.
 *
 * The L1TF mitigation uses the top most address bit for the inversion of
 * non present PTEs. When the installed memory reaches into the top most
 * address bit due to memory holes, which has been observed on machines
 * which report 36bits physical address bits and have 32G RAM installed,
 * then the mitigation range check in l1tf_select_mitigation() triggers.
 * This is a false positive because the mitigation is still possible due to
 * the fact that the cache uses 44bit internally. Use the cache bits
 * instead of the reported physical bits and adjust them on the affected
 * machines to 44bit if the reported bits are less than 44.
 */
static void override_cache_bits(struct cpuinfo_x86 *c)
{
	if (c->x86 != 6)
		return;

	switch (c->x86_model) {
	case INTEL_FAM6_NEHALEM:
	case INTEL_FAM6_WESTMERE:
	case INTEL_FAM6_SANDYBRIDGE:
	case INTEL_FAM6_IVYBRIDGE:
	case INTEL_FAM6_HASWELL_CORE:
	case INTEL_FAM6_HASWELL_ULT:
	case INTEL_FAM6_HASWELL_GT3E:
	case INTEL_FAM6_BROADWELL_CORE:
	case INTEL_FAM6_BROADWELL_GT3E:
	case INTEL_FAM6_SKYLAKE_MOBILE:
	case INTEL_FAM6_SKYLAKE_DESKTOP:
	case INTEL_FAM6_KABYLAKE_MOBILE:
	case INTEL_FAM6_KABYLAKE_DESKTOP:
		if (c->x86_cache_bits < 44)
			c->x86_cache_bits = 44;
		break;
	}
}

992
993
994
995
996
997
998
static void __init l1tf_select_mitigation(void)
{
	u64 half_pa;

	if (!boot_cpu_has_bug(X86_BUG_L1TF))
		return;

999
1000
	override_cache_bits(&boot_cpu_data);

1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
	switch (l1tf_mitigation) {
	case L1TF_MITIGATION_OFF:
	case L1TF_MITIGATION_FLUSH_NOWARN:
	case L1TF_MITIGATION_FLUSH:
		break;
	case L1TF_MITIGATION_FLUSH_NOSMT:
	case L1TF_MITIGATION_FULL:
		cpu_smt_disable(false);
		break;
	case L1TF_MITIGATION_FULL_FORCE:
		cpu_smt_disable(true);
		break;
	}

1015
1016
1017
1018
1019
1020
#if CONFIG_PGTABLE_LEVELS == 2
	pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
	return;
#endif

	half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
1021
1022
	if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
			e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
1023
		pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
1024
1025
1026
1027
		pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
				half_pa);
		pr_info("However, doing so will make a part of your RAM unusable.\n");
		pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html might help you decide.\n");
1028
1029
1030
1031
1032
		return;
	}

	setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
}
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058

static int __init l1tf_cmdline(char *str)
{
	if (!boot_cpu_has_bug(X86_BUG_L1TF))
		return 0;

	if (!str)
		return -EINVAL;

	if (!strcmp(str, "off"))
		l1tf_mitigation = L1TF_MITIGATION_OFF;
	else if (!strcmp(str, "flush,nowarn"))
		l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
	else if (!strcmp(str, "flush"))
		l1tf_mitigation = L1TF_MITIGATION_FLUSH;
	else if (!strcmp(str, "flush,nosmt"))
		l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
	else if (!strcmp(str, "full"))
		l1tf_mitigation = L1TF_MITIGATION_FULL;
	else if (!strcmp(str, "full,force"))
		l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;

	return 0;
}
early_param("l1tf", l1tf_cmdline);

1059
1060
#undef pr_fmt

1061
#ifdef CONFIG_SYSFS
1062

1063
1064
1065
#define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"

#if IS_ENABLED(CONFIG_KVM_INTEL)
1066
static const char * const l1tf_vmx_states[] = {
1067
1068
1069
1070
1071
	[VMENTER_L1D_FLUSH_AUTO]		= "auto",
	[VMENTER_L1D_FLUSH_NEVER]		= "vulnerable",
	[VMENTER_L1D_FLUSH_COND]		= "conditional cache flushes",
	[VMENTER_L1D_FLUSH_ALWAYS]		= "cache flushes",
	[VMENTER_L1D_FLUSH_EPT_DISABLED]	= "EPT disabled",
1072
	[VMENTER_L1D_FLUSH_NOT_REQUIRED]	= "flush not necessary"
1073
1074
1075
1076
1077
1078
1079
};

static ssize_t l1tf_show_state(char *buf)
{
	if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
		return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);

1080
1081
	if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
	    (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
1082
	     sched_smt_active())) {
1083
1084
		return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
			       l1tf_vmx_states[l1tf_vmx_mitigation]);
1085
	}
1086
1087
1088

	return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
		       l1tf_vmx_states[l1tf_vmx_mitigation],
1089
		       sched_smt_active() ? "vulnerable" : "disabled");
1090
1091
1092
1093
1094
1095
1096
1097
}
#else
static ssize_t l1tf_show_state(char *buf)
{
	return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
}
#endif

1098
1099
static char *stibp_state(void)
{
1100
1101
1102
	if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED)
		return "";

1103
1104
1105
1106
1107
	switch (spectre_v2_user) {
	case SPECTRE_V2_USER_NONE:
		return ", STIBP: disabled";
	case SPECTRE_V2_USER_STRICT:
		return ", STIBP: forced";
1108
1109
	case SPECTRE_V2_USER_STRICT_PREFERRED:
		return ", STIBP: always-on";
1110
	case SPECTRE_V2_USER_PRCTL:
1111
	case SPECTRE_V2_USER_SECCOMP:
1112
1113
		if (static_key_enabled(&switch_to_cond_stibp))
			return ", STIBP: conditional";
1114
1115
	}
	return "";
1116
1117
1118
1119
}

static char *ibpb_state(void)
{
1120
	if (boot_cpu_has(X86_FEATURE_IBPB)) {
1121
		if (static_key_enabled(&switch_mm_always_ibpb))
1122
			return ", IBPB: always-on";
1123
1124
1125
		if (static_key_enabled(&switch_mm_cond_ibpb))
			return ", IBPB: conditional";
		return ", IBPB: disabled";
1126
1127
	}
	return "";
1128
1129
}

1130
static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
1131
			       char *buf, unsigned int bug)
1132
{
1133
	if (!boot_cpu_has_bug(bug))
1134
		return sprintf(buf, "Not affected\n");
1135
1136
1137
1138
1139
1140

	switch (bug) {
	case X86_BUG_CPU_MELTDOWN:
		if (boot_cpu_has(X86_FEATURE_PTI))
			return sprintf(buf, "Mitigation: PTI\n");

1141
1142
1143
		if (hypervisor_is_type(X86_HYPER_XEN_PV))
			return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");

1144
1145
1146
1147
1148
1149
		break;

	case X86_BUG_SPECTRE_V1:
		return sprintf(buf, "Mitigation: __user pointer sanitization\n");

	case X86_BUG_SPECTRE_V2:
1150
		return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
1151
			       ibpb_state(),
1152
			       boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
1153
			       stibp_state(),
1154
			       boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
1155
1156
			       spectre_v2_module_string());

1157
1158
1159
	case X86_BUG_SPEC_STORE_BYPASS:
		return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);

1160
1161
	case X86_BUG_L1TF:
		if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
1162
			return l1tf_show_state(buf);
1163
		break;
1164
1165
1166
1167
	default:
		break;
	}

1168
1169
1170
	return sprintf(buf, "Vulnerable\n");
}

1171
1172
1173
1174
1175
ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
}

1176
ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
1177
{
1178
	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
1179
1180
}

1181
ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
1182
{
1183
	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
1184
}
1185
1186
1187
1188
1189

ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
}
1190
1191
1192
1193
1194

ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
}
1195
#endif