Skip to content
  • Rob Herring's avatar
    ARM: highbank: fix cache flush ordering for cpu hotplug · 73053d97
    Rob Herring authored
    
    
    The L1 data cache flush needs to be after highbank_set_cpu_jump call which
    pollutes the cache with the l2x0_lock. This causes other cores to deadlock
    waiting for the l2x0_lock. Moving the flush of the entire data cache after
    highbank_set_cpu_jump fixes the problem. Use flush_cache_louis instead of
    flush_cache_all are that is sufficient to flush only the L1 data cache.
    flush_cache_louis did not exist when highbank_cpu_die was originally
    written.
    
    With PL310 errata 769419 enabled, a wmb is inserted into idle which takes
    the l2x0_lock. This makes the problem much more easily hit and causes
    reset to hang.
    
    Reported-by: default avatarPaolo Pisati <p.pisati@gmail.com>
    Signed-off-by: default avatarRob Herring <rob.herring@calxeda.com>
    Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
    73053d97