• Stephane Eranian's avatar
    perf/x86/intel: Update event constraints when HT is off · 9010ae4a
    Stephane Eranian authored
    This patch updates the event constraints for non-PEBS mode for
    Intel Broadwell and Skylake processors. When HT is off, each
    CPU gets 8 generic counters. However, not all events can be
    programmed on any of the 8 counters.  This patch adds the
    constraints for the MEM_* events which can only be measured on the
    bottom 4 counters. The constraints are also valid when HT is off
    because, then, there are only 4 generic counters and they are the
    bottom counters.
    Signed-off-by: default avatarStephane Eranian <eranian@google.com>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Vince Weaver <vincent.weaver@maine.edu>
    Cc: kan.liang@intel.com
    Link: http://lkml.kernel.org/r/1467411742-13245-1-git-send-email-eranian@google.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
core.c 111 KB