• Arnd Bergmann's avatar
    powerpc/cell/axon-msi: Retry on missing interrupt · d015fe99
    Arnd Bergmann authored
    
    
    The MSI capture logic for the axon bridge can sometimes
    lose interrupts in case of high DMA and interrupt load,
    when it signals an MSI interrupt to the MPIC interrupt
    controller while we are already handling another MSI.
    
    Each MSI vector gets written into a FIFO buffer in main
    memory using DMA, and that DMA access is normally flushed
    by the actual interrupt packet on the IOIF.  An MMIO
    register in the MSIC holds the position of the last
    entry in the FIFO buffer that was written.  However,
    reading that position does not flush the DMA, so that
    we can observe stale data in the buffer.
    
    In a stress test, we have observed the DMA to arrive
    up to 14 microseconds after reading the register.
    
    This patch works around this problem by retrying the
    access to the FIFO buffer.
    
    We can reliably detect the conditioning by writing
    an invalid MSI vector into the FIFO buffer after
    reading from it, assuming that all MSIs we get
    are valid.  After detecting an invalid MSI vector,
    we udelay(1) in the interrupt cascade for up to
    100 times before giving up.
    Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
    Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
    d015fe99
axon_msi.c 11.4 KB