• Kan Liang's avatar
    perf/x86/intel: Add Goldmont Plus CPU PMU support · dd0b06b5
    Kan Liang authored
    Add perf core PMU support for Intel Goldmont Plus CPU cores:
     - The init code is based on Goldmont.
     - There is a new cache event list, based on the Goldmont cache event
     - All four general-purpose performance counters support PEBS.
     - The first general-purpose performance counter is for reduced skid
       PEBS mechanism. Using :ppp to indicate the event which want to do
       reduced skid PEBS.
     - Goldmont Plus has 4-wide pipeline for Topdown
    Signed-off-by: default avatarKan Liang <kan.liang@intel.com>
    Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
    Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
    Cc: Jiri Olsa <jolsa@redhat.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Stephane Eranian <eranian@google.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Vince Weaver <vincent.weaver@maine.edu>
    Cc: acme@kernel.org
    Link: http://lkml.kernel.org/r/20170712134423.17766-1-kan.liang@intel.comSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
core.c 121 KB