Commit 00e3d2ef authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'wireless-drivers-next-for-davem-2016-03-09' of...

Merge tag 'wireless-drivers-next-for-davem-2016-03-09' of git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next



Kalle Valo says:

====================
wireless-drivers patches for 4.6

Major changes:

ath10k

* dt: add bindings for ipq4019 wifi block
* start adding support for qca4019 chip

ath9k

* add device ID for Toshiba WLM-20U2/GN-1080
* allow more than one interface on DFS channels

bcma

* move flash detection code to ChipCommon core driver

brcmfmac

* IPv6 Neighbor discovery offload
* driver settings that can be populated from different sources
* country code setting in firmware
* length checks to validate firmware events
* new way to determine device memory size needed for BCM4366
* various offloads during Wake on Wireless LAN (WoWLAN)
* full Management Frame Protection (MFP) support

iwlwifi

* add support for thermal device / cooling device
* improvements in scheduled scan without profiles
* new firmware support (-21.ucode)
* add MSIX support for 9000 devices
* enable MU-MIMO and take care of firmware restart
* add support for large SKBs in mvm to reach A-MSDU
* add support for filtering frames from a BA session
* start implementing the new Rx path for 9000 devices
* enable the new Radio Resource Management (RRM) nl80211 feature flag
* add a new module paramater to disable VHT
* build infrastructure for Dynamic Queue Allocation
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f22f5f60 836856e3
* Qualcomm Atheros ath10k wireless devices
For ath10k devices the calibration data can be provided through Device
Tree. The node is a child node of the PCI controller.
Required properties:
-compatible : Should be "qcom,ath10k"
- compatible: Should be one of the following:
* "qcom,ath10k"
* "qcom,ipq4019-wifi"
PCI based devices uses compatible string "qcom,ath10k" and takes only
calibration data via "qcom,ath10k-calibration-data". Rest of the properties
are not applicable for PCI based devices.
AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi"
and also uses most of the properties defined in this doc.
Optional properties:
- reg: Address and length of the register set for the device.
- resets: Must contain an entry for each entry in reset-names.
See ../reset/reseti.txt for details.
- reset-names: Must include the list of following reset names,
"wifi_cpu_init"
"wifi_radio_srif"
"wifi_radio_warm"
"wifi_radio_cold"
"wifi_core_warm"
"wifi_core_cold"
- clocks: List of clock specifiers, must contain an entry for each required
entry in clock-names.
- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref",
"wifi_wcss_rtc".
- interrupts: List of interrupt lines. Must contain an entry
for each entry in the interrupt-names property.
- interrupt-names: Must include the entries for MSI interrupt
names ("msi0" to "msi15") and legacy interrupt
name ("legacy"),
- qcom,msi_addr: MSI interrupt address.
- qcom,msi_base: Base value to add before writing MSI data into
MSI address register.
- qcom,ath10k-calibration-data : calibration data as an array, the
length can vary between hw versions
Example (to supply the calibration data alone):
Example:
In this example, the node is defined as child node of the PCI controller.
pci {
pcie@0 {
......@@ -28,3 +57,53 @@ pci {
};
};
};
Example (to supply ipq4019 SoC wifi block details):
wifi0: wifi@a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
resets = <&gcc WIFI0_CPU_INIT_RESET>,
<&gcc WIFI0_RADIO_SRIF_RESET>,
<&gcc WIFI0_RADIO_WARM_RESET>,
<&gcc WIFI0_RADIO_COLD_RESET>,
<&gcc WIFI0_CORE_WARM_RESET>,
<&gcc WIFI0_CORE_COLD_RESET>;
reset-names = "wifi_cpu_init",
"wifi_radio_srif",
"wifi_radio_warm",
"wifi_radio_cold",
"wifi_core_warm",
"wifi_core_cold";
clocks = <&gcc GCC_WCSS2G_CLK>,
<&gcc GCC_WCSS2G_REF_CLK>,
<&gcc GCC_WCSS2G_RTC_CLK>;
clock-names = "wifi_wcss_cmd",
"wifi_wcss_ref",
"wifi_wcss_rtc";
interrupts = <0 0x20 0x1>,
<0 0x21 0x1>,
<0 0x22 0x1>,
<0 0x23 0x1>,
<0 0x24 0x1>,
<0 0x25 0x1>,
<0 0x26 0x1>,
<0 0x27 0x1>,
<0 0x28 0x1>,
<0 0x29 0x1>,
<0 0x2a 0x1>,
<0 0x2b 0x1>,
<0 0x2c 0x1>,
<0 0x2d 0x1>,
<0 0x2e 0x1>,
<0 0x2f 0x1>,
<0 0xa8 0x0>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
"msi12", "msi13", "msi14", "msi15",
"legacy";
qcom,msi_addr = <0x0b006040>;
qcom,msi_base = <0x40>;
qcom,ath10k-calibration-data = [ 01 02 03 ... ];
};
......@@ -70,6 +70,11 @@ config BCMA_DRIVER_MIPS
If unsure, say N
config BCMA_PFLASH
bool
depends on BCMA_DRIVER_MIPS
default y
config BCMA_SFLASH
bool
depends on BCMA_DRIVER_MIPS
......
bcma-y += main.o scan.o core.o sprom.o
bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
bcma-y += driver_chipcommon_b.o
bcma-$(CONFIG_BCMA_PFLASH) += driver_chipcommon_pflash.o
bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
bcma-$(CONFIG_BCMA_DRIVER_PCI) += driver_pci.o
......
......@@ -47,9 +47,6 @@ int bcma_sprom_get(struct bcma_bus *bus);
void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable);
#ifdef CONFIG_BCMA_DRIVER_MIPS
extern struct platform_device bcma_pflash_dev;
#endif /* CONFIG_BCMA_DRIVER_MIPS */
/* driver_chipcommon_b.c */
int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
......@@ -61,6 +58,21 @@ void bcma_pmu_init(struct bcma_drv_cc *cc);
u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
/**************************************************
* driver_chipcommon_sflash.c
**************************************************/
#ifdef CONFIG_BCMA_PFLASH
extern struct platform_device bcma_pflash_dev;
int bcma_pflash_init(struct bcma_drv_cc *cc);
#else
static inline int bcma_pflash_init(struct bcma_drv_cc *cc)
{
bcma_err(cc->core->bus, "Parallel flash not supported\n");
return 0;
}
#endif /* CONFIG_BCMA_PFLASH */
#ifdef CONFIG_BCMA_SFLASH
/* driver_chipcommon_sflash.c */
int bcma_sflash_init(struct bcma_drv_cc *cc);
......
......@@ -115,6 +115,33 @@ int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
return 0;
}
static void bcma_core_chipcommon_flash_detect(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
case BCMA_CC_FLASHT_STSER:
case BCMA_CC_FLASHT_ATSER:
bcma_debug(bus, "Found serial flash\n");
bcma_sflash_init(cc);
break;
case BCMA_CC_FLASHT_PARA:
bcma_debug(bus, "Found parallel flash\n");
bcma_pflash_init(cc);
break;
default:
bcma_err(bus, "Flash type not supported\n");
}
if (cc->core->id.rev == 38 ||
bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
bcma_debug(bus, "Found NAND flash\n");
bcma_nflash_init(cc);
}
}
}
void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
......@@ -136,6 +163,9 @@ void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC)
bcma_chipco_serial_init(cc);
if (bus->hosttype == BCMA_HOSTTYPE_SOC)
bcma_core_chipcommon_flash_detect(cc);
cc->early_setup_done = true;
}
......
/*
* Broadcom specific AMBA
* ChipCommon parallel flash
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
#include "bcma_private.h"
#include <linux/bcma/bcma.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
static const char * const part_probes[] = { "bcm47xxpart", NULL };
static struct physmap_flash_data bcma_pflash_data = {
.part_probe_types = part_probes,
};
static struct resource bcma_pflash_resource = {
.name = "bcma_pflash",
.flags = IORESOURCE_MEM,
};
struct platform_device bcma_pflash_dev = {
.name = "physmap-flash",
.dev = {
.platform_data = &bcma_pflash_data,
},
.resource = &bcma_pflash_resource,
.num_resources = 1,
};
int bcma_pflash_init(struct bcma_drv_cc *cc)
{
struct bcma_pflash *pflash = &cc->pflash;
pflash->present = true;
if (!(bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & BCMA_CC_FLASH_CFG_DS))
bcma_pflash_data.width = 1;
else
bcma_pflash_data.width = 2;
bcma_pflash_resource.start = BCMA_SOC_FLASH2;
bcma_pflash_resource.end = BCMA_SOC_FLASH2 + BCMA_SOC_FLASH2_SZ;
return 0;
}
......@@ -14,8 +14,6 @@
#include <linux/bcma/bcma.h>
#include <linux/mtd/physmap.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
......@@ -32,26 +30,6 @@ enum bcma_boot_dev {
BCMA_BOOT_DEV_NAND,
};
static const char * const part_probes[] = { "bcm47xxpart", NULL };
static struct physmap_flash_data bcma_pflash_data = {
.part_probe_types = part_probes,
};
static struct resource bcma_pflash_resource = {
.name = "bcma_pflash",
.flags = IORESOURCE_MEM,
};
struct platform_device bcma_pflash_dev = {
.name = "physmap-flash",
.dev = {
.platform_data = &bcma_pflash_data,
},
.resource = &bcma_pflash_resource,
.num_resources = 1,
};
/* The 47162a0 hangs when reading MIPS DMP registers registers */
static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
{
......@@ -272,48 +250,11 @@ static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
return BCMA_BOOT_DEV_SERIAL;
}
static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
static void bcma_core_mips_nvram_init(struct bcma_drv_mips *mcore)
{
struct bcma_bus *bus = mcore->core->bus;
struct bcma_drv_cc *cc = &bus->drv_cc;
struct bcma_pflash *pflash = &cc->pflash;
enum bcma_boot_dev boot_dev;
switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
case BCMA_CC_FLASHT_STSER:
case BCMA_CC_FLASHT_ATSER:
bcma_debug(bus, "Found serial flash\n");
bcma_sflash_init(cc);
break;
case BCMA_CC_FLASHT_PARA:
bcma_debug(bus, "Found parallel flash\n");
pflash->present = true;
pflash->window = BCMA_SOC_FLASH2;
pflash->window_size = BCMA_SOC_FLASH2_SZ;
if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
BCMA_CC_FLASH_CFG_DS) == 0)
pflash->buswidth = 1;
else
pflash->buswidth = 2;
bcma_pflash_data.width = pflash->buswidth;
bcma_pflash_resource.start = pflash->window;
bcma_pflash_resource.end = pflash->window + pflash->window_size;
break;
default:
bcma_err(bus, "Flash type not supported\n");
}
if (cc->core->id.rev == 38 ||
bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
bcma_debug(bus, "Found NAND flash\n");
bcma_nflash_init(cc);
}
}
/* Determine flash type this SoC boots from */
boot_dev = bcma_boot_dev(bus);
switch (boot_dev) {
......@@ -340,7 +281,7 @@ void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
if (mcore->early_setup_done)
return;
bcma_core_mips_flash_detect(mcore);
bcma_core_mips_nvram_init(mcore);
mcore->early_setup_done = true;
}
......
......@@ -350,7 +350,7 @@ static int bcma_register_devices(struct bcma_bus *bus)
bcma_register_core(bus, core);
}
#ifdef CONFIG_BCMA_DRIVER_MIPS
#ifdef CONFIG_BCMA_PFLASH
if (bus->drv_cc.pflash.present) {
err = platform_device_register(&bcma_pflash_dev);
if (err)
......
......@@ -15,6 +15,12 @@ config ATH10K_PCI
---help---
This module adds support for PCIE bus
config ATH10K_AHB
bool "Atheros ath10k AHB support"
depends on ATH10K_PCI && OF && RESET_CONTROLLER
---help---
This module adds support for AHB bus
config ATH10K_DEBUG
bool "Atheros ath10k debugging"
depends on ATH10K
......
......@@ -25,5 +25,7 @@ obj-$(CONFIG_ATH10K_PCI) += ath10k_pci.o
ath10k_pci-y += pci.o \
ce.o
ath10k_pci-$(CONFIG_ATH10K_AHB) += ahb.o
# for tracing framework to find trace.h
CFLAGS_trace.o := -I$(src)
This diff is collapsed.
/*
* Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved.
* Copyright (c) 2015 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _AHB_H_
#define _AHB_H_
#include <linux/platform_device.h>
struct ath10k_ahb {
struct platform_device *pdev;
void __iomem *mem;
unsigned long mem_len;
void __iomem *gcc_mem;
void __iomem *tcsr_mem;
int irq;
struct clk *cmd_clk;
struct clk *ref_clk;
struct clk *rtc_clk;
struct reset_control *core_cold_rst;
struct reset_control *radio_cold_rst;
struct reset_control *radio_warm_rst;
struct reset_control *radio_srif_rst;
struct reset_control *cpu_init_rst;
};
#ifdef CONFIG_ATH10K_AHB
#define ATH10K_GCC_REG_BASE 0x1800000
#define ATH10K_GCC_REG_SIZE 0x60000
#define ATH10K_TCSR_REG_BASE 0x1900000
#define ATH10K_TCSR_REG_SIZE 0x80000
#define ATH10K_AHB_GCC_FEPLL_PLL_DIV 0x2f020
#define ATH10K_AHB_WIFI_SCRATCH_5_REG 0x4f014
#define ATH10K_AHB_WLAN_CORE_ID_REG 0x82030
#define ATH10K_AHB_TCSR_WIFI0_GLB_CFG 0x49000
#define ATH10K_AHB_TCSR_WIFI1_GLB_CFG 0x49004
#define TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK BIT(25)
#define ATH10K_AHB_TCSR_WCSS0_HALTREQ 0x52000
#define ATH10K_AHB_TCSR_WCSS1_HALTREQ 0x52010
#define ATH10K_AHB_TCSR_WCSS0_HALTACK 0x52004
#define ATH10K_AHB_TCSR_WCSS1_HALTACK 0x52014
#define ATH10K_AHB_AXI_BUS_HALT_TIMEOUT 10 /* msec */
#define AHB_AXI_BUS_HALT_REQ 1
#define AHB_AXI_BUS_HALT_ACK 1
#define ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK 1
int ath10k_ahb_init(void);
void ath10k_ahb_exit(void);
#else /* CONFIG_ATH10K_AHB */
static inline int ath10k_ahb_init(void)
{
return 0;
}
static inline void ath10k_ahb_exit(void)
{
}
#endif /* CONFIG_ATH10K_AHB */
#endif /* _AHB_H_ */
......@@ -156,6 +156,11 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.channel_counters_freq_hz = 150000,
.max_probe_resp_desc_thres = 24,
.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
.num_msdu_desc = 1424,
.qcache_active_peers = 50,
.tx_chain_mask = 0xf,
.rx_chain_mask = 0xf,
.max_spatial_stream = 4,
.fw = {
.dir = QCA99X0_HW_2_0_FW_DIR,
.fw = QCA99X0_HW_2_0_FW_FILE,
......@@ -201,6 +206,31 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
},
},
{
.id = QCA4019_HW_1_0_DEV_VERSION,
.dev_id = 0,
.name = "qca4019 hw1.0",
.patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
.uart_pin = 7,
.otp_exe_param = 0x0010000,
.continuous_frag_desc = true,
.channel_counters_freq_hz = 125000,
.max_probe_resp_desc_thres = 24,
.hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
.num_msdu_desc = 2500,
.qcache_active_peers = 35,
.tx_chain_mask = 0x3,
.rx_chain_mask = 0x3,
.max_spatial_stream = 2,
.fw = {
.dir = QCA4019_HW_1_0_FW_DIR,
.fw = QCA4019_HW_1_0_FW_FILE,
.otp = QCA4019_HW_1_0_OTP_FILE,
.board = QCA4019_HW_1_0_BOARD_DATA_FILE,
.board_size = QCA4019_BOARD_DATA_SZ,
.board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
},
},
};
static const char *const ath10k_core_fw_feature_str[] = {
......@@ -217,6 +247,7 @@ static const char *const ath10k_core_fw_feature_str[] = {
[ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
[ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
[ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
[ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
};
static unsigned int ath10k_core_get_fw_feature_str(char *buf,
......@@ -1478,8 +1509,13 @@ static int ath10k_core_init_firmware_features(struct ath10k *ar)
case ATH10K_FW_WMI_OP_VERSION_10_1:
case ATH10K_FW_WMI_OP_VERSION_10_2:
case ATH10K_FW_WMI_OP_VERSION_10_2_4:
ar->max_num_peers = TARGET_10X_NUM_PEERS;
ar->max_num_stations = TARGET_10X_NUM_STATIONS;
if (test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map)) {
ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
} else {
ar->max_num_peers = TARGET_10X_NUM_PEERS;
ar->max_num_stations = TARGET_10X_NUM_STATIONS;
}
ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
ar->fw_stats_req_mask = WMI_STAT_PEER;
......@@ -1502,9 +1538,9 @@ static int ath10k_core_init_firmware_features(struct ath10k *ar)
ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
ar->htt.max_num_pending_tx = ar->hw_params.num_msdu_desc;
ar->fw_stats_req_mask = WMI_STAT_PEER;
ar->max_spatial_stream = WMI_10_4_MAX_SPATIAL_STREAM;
ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
break;
case ATH10K_FW_WMI_OP_VERSION_UNSET:
case ATH10K_FW_WMI_OP_VERSION_MAX:
......@@ -1979,6 +2015,10 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
ar->regs = &qca99x0_regs;
ar->hw_values = &qca99x0_values;
break;
case ATH10K_HW_QCA4019:
ar->regs = &qca4019_regs;
ar->hw_values = &qca4019_values;
break;
default:
ath10k_err(ar, "unsupported core hardware revision %d\n",
hw_rev);
......
......@@ -69,6 +69,7 @@ struct ath10k;
enum ath10k_bus {
ATH10K_BUS_PCI,
ATH10K_BUS_AHB,
};
static inline const char *ath10k_bus_str(enum ath10k_bus bus)
......@@ -76,6 +77,8 @@ static inline const char *ath10k_bus_str(enum ath10k_bus bus)
switch (bus) {
case ATH10K_BUS_PCI:
return "pci";
case ATH10K_BUS_AHB:
return "ahb";
}
return "unknown";
......@@ -159,6 +162,7 @@ struct ath10k_fw_stats_peer {
u32 peer_rssi;
u32 peer_tx_rate;
u32 peer_rx_rate; /* 10x only */
u32 rx_duration;
};
struct ath10k_fw_stats_vdev {
......@@ -315,6 +319,7 @@ struct ath10k_sta {
#ifdef CONFIG_MAC80211_DEBUGFS
/* protected by conf_mutex */
bool aggr_mode;
u64 rx_duration;
#endif
};
......@@ -510,6 +515,15 @@ enum ath10k_fw_features {
/* Firmware supports management frame protection */
ATH10K_FW_FEATURE_MFP_SUPPORT = 12,
/* Firmware supports pull-push model where host shares it's software
* queue state with firmware and firmware generates fetch requests
* telling host which queues to dequeue tx from.
*
* Primary function of this is improved MU-MIMO performance with
* multiple clients.
*/
ATH10K_FW_FEATURE_PEER_FLOW_CONTROL = 13,
/* keep last */
ATH10K_FW_FEATURE_COUNT,
};
......@@ -666,6 +680,12 @@ struct ath10k {
/* The padding bytes's location is different on various chips */
enum ath10k_hw_4addr_pad hw_4addr_pad;
u32 num_msdu_desc;
u32 qcache_active_peers;
u32 tx_chain_mask;
u32 rx_chain_mask;
u32 max_spatial_stream;
struct ath10k_hw_params_fw {
const char *dir;
const char *fw;
......
......@@ -276,7 +276,7 @@ static const struct file_operations fops_wmi_services = {
.llseek = default_llseek,
};
static void ath10k_debug_fw_stats_pdevs_free(struct list_head *head)