Commit 0ee537ab authored by Chris Wilson's avatar Chris Wilson
Browse files

Revert "drm/i915: fix corruptions on i8xx due to relaxed fencing"

This reverts commit c2e0eb16.

As it turns out, userspace already depends upon being able to enable
tiling on existing bo which it promises to be large enough for its
purposes i.e. it will not access beyond the end of the last full-tile
row.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35016

Reported-and-tested-by: default avatarKamal Mostafa <kamal@canonical.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 6927faf3
......@@ -184,7 +184,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
static bool
i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
{
int tile_width, tile_height;
int tile_width;
/* Linear is always fine */
if (tiling_mode == I915_TILING_NONE)
......@@ -215,20 +215,6 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
}
}
if (IS_GEN2(dev) ||
(tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
tile_height = 32;
else
tile_height = 8;
/* i8xx is strange: It has 2 interleaved rows of tiles, so needs an even
* number of tile rows. */
if (IS_GEN2(dev))
tile_height *= 2;
/* Size needs to be aligned to a full tile row */
if (size & (tile_height * stride - 1))
return false;
/* 965+ just needs multiples of tile width */
if (INTEL_INFO(dev)->gen >= 4) {
if (stride & (tile_width - 1))
......
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