Commit 0f12d5b3 authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Matthias Brugger
Browse files

arm64: dts: mt7622: add usb device nodes



add xhci node and usb3 phy nodes
Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Tested-by: default avatarJumin Li <jumin.li@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent a39251ee
......@@ -52,6 +52,24 @@
memory {
reg = <0 0x40000000 0 0x3F000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
&pcie {
......@@ -343,6 +361,16 @@
status = "okay";
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&u3phy {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
......
......@@ -535,6 +535,57 @@
#reset-cells = <1>;
};
ssusb: usb@1a0c0000 {
compatible = "mediatek,mt7622-xhci",
"mediatek,mtk-xhci";
reg = <0 0x1a0c0000 0 0x01000>,
<0 0x1a0c4700 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
<&ssusbsys CLK_SSUSB_REF_EN>,
<&ssusbsys CLK_SSUSB_MCU_EN>,
<&ssusbsys CLK_SSUSB_DMA_EN>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
status = "disabled";
};
u3phy: usb-phy@1a0c4000 {
compatible = "mediatek,mt7622-u3phy",
"mediatek,generic-tphy-v1";
reg = <0 0x1a0c4000 0 0x700>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
u2port0: usb-phy@1a0c4800 {
reg = <0 0x1a0c4800 0 0x0100>;
#phy-cells = <1>;
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
clock-names = "ref";
};
u3port0: usb-phy@1a0c4900 {
reg = <0 0x1a0c4900 0 0x0700>;
#phy-cells = <1>;
clocks = <&clk25m>;
clock-names = "ref";
};
u2port1: usb-phy@1a0c5000 {
reg = <0 0x1a0c5000 0 0x0100>;
#phy-cells = <1>;
clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
clock-names = "ref";
};
};
pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys",
"syscon";
......
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