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xenomai
ipipe-x86
Commits
1561747d
Commit
1561747d
authored
Mar 12, 2011
by
David S. Miller
Browse files
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/jkirsher/net-next-2.6
parents
ab1ebc95
1f4a0244
Changes
29
Hide whitespace changes
Inline
Side-by-side
drivers/net/igb/e1000_82575.c
View file @
1561747d
...
...
@@ -64,7 +64,14 @@ static s32 igb_reset_init_script_82575(struct e1000_hw *);
static
s32
igb_read_mac_addr_82575
(
struct
e1000_hw
*
);
static
s32
igb_set_pcie_completion_timeout
(
struct
e1000_hw
*
hw
);
static
s32
igb_reset_mdicnfg_82580
(
struct
e1000_hw
*
hw
);
static
s32
igb_validate_nvm_checksum_82580
(
struct
e1000_hw
*
hw
);
static
s32
igb_update_nvm_checksum_82580
(
struct
e1000_hw
*
hw
);
static
s32
igb_update_nvm_checksum_with_offset
(
struct
e1000_hw
*
hw
,
u16
offset
);
static
s32
igb_validate_nvm_checksum_with_offset
(
struct
e1000_hw
*
hw
,
u16
offset
);
static
s32
igb_validate_nvm_checksum_i350
(
struct
e1000_hw
*
hw
);
static
s32
igb_update_nvm_checksum_i350
(
struct
e1000_hw
*
hw
);
static
const
u16
e1000_82580_rxpbs_table
[]
=
{
36
,
72
,
144
,
1
,
2
,
4
,
8
,
16
,
35
,
70
,
140
};
...
...
@@ -195,7 +202,11 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
mac
->
arc_subsystem_valid
=
(
rd32
(
E1000_FWSM
)
&
E1000_FWSM_MODE_MASK
)
?
true
:
false
;
/* enable EEE on i350 parts */
if
(
mac
->
type
==
e1000_i350
)
dev_spec
->
eee_disable
=
false
;
else
dev_spec
->
eee_disable
=
true
;
/* physical interface link setup */
mac
->
ops
.
setup_physical_interface
=
(
hw
->
phy
.
media_type
==
e1000_media_type_copper
)
...
...
@@ -233,10 +244,32 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
*/
size
+=
NVM_WORD_SIZE_BASE_SHIFT
;
/* EEPROM access above 16k is unsupported */
if
(
size
>
14
)
size
=
14
;
nvm
->
word_size
=
1
<<
size
;
if
(
nvm
->
word_size
==
(
1
<<
15
))
nvm
->
page_size
=
128
;
/* NVM Function Pointers */
nvm
->
ops
.
acquire
=
igb_acquire_nvm_82575
;
if
(
nvm
->
word_size
<
(
1
<<
15
))
nvm
->
ops
.
read
=
igb_read_nvm_eerd
;
else
nvm
->
ops
.
read
=
igb_read_nvm_spi
;
nvm
->
ops
.
release
=
igb_release_nvm_82575
;
switch
(
hw
->
mac
.
type
)
{
case
e1000_82580
:
nvm
->
ops
.
validate
=
igb_validate_nvm_checksum_82580
;
nvm
->
ops
.
update
=
igb_update_nvm_checksum_82580
;
break
;
case
e1000_i350
:
nvm
->
ops
.
validate
=
igb_validate_nvm_checksum_i350
;
nvm
->
ops
.
update
=
igb_update_nvm_checksum_i350
;
break
;
default:
nvm
->
ops
.
validate
=
igb_validate_nvm_checksum
;
nvm
->
ops
.
update
=
igb_update_nvm_checksum
;
}
nvm
->
ops
.
write
=
igb_write_nvm_spi
;
/* if part supports SR-IOV then initialize mailbox parameters */
switch
(
mac
->
type
)
{
...
...
@@ -1754,6 +1787,248 @@ u16 igb_rxpbs_adjust_82580(u32 data)
return
ret_val
;
}
/**
* igb_validate_nvm_checksum_with_offset - Validate EEPROM
* checksum
* @hw: pointer to the HW structure
* @offset: offset in words of the checksum protected region
*
* Calculates the EEPROM checksum by reading/adding each word of the EEPROM
* and then verifies that the sum of the EEPROM is equal to 0xBABA.
**/
s32
igb_validate_nvm_checksum_with_offset
(
struct
e1000_hw
*
hw
,
u16
offset
)
{
s32
ret_val
=
0
;
u16
checksum
=
0
;
u16
i
,
nvm_data
;
for
(
i
=
offset
;
i
<
((
NVM_CHECKSUM_REG
+
offset
)
+
1
);
i
++
)
{
ret_val
=
hw
->
nvm
.
ops
.
read
(
hw
,
i
,
1
,
&
nvm_data
);
if
(
ret_val
)
{
hw_dbg
(
"NVM Read Error
\n
"
);
goto
out
;
}
checksum
+=
nvm_data
;
}
if
(
checksum
!=
(
u16
)
NVM_SUM
)
{
hw_dbg
(
"NVM Checksum Invalid
\n
"
);
ret_val
=
-
E1000_ERR_NVM
;
goto
out
;
}
out:
return
ret_val
;
}
/**
* igb_update_nvm_checksum_with_offset - Update EEPROM
* checksum
* @hw: pointer to the HW structure
* @offset: offset in words of the checksum protected region
*
* Updates the EEPROM checksum by reading/adding each word of the EEPROM
* up to the checksum. Then calculates the EEPROM checksum and writes the
* value to the EEPROM.
**/
s32
igb_update_nvm_checksum_with_offset
(
struct
e1000_hw
*
hw
,
u16
offset
)
{
s32
ret_val
;
u16
checksum
=
0
;
u16
i
,
nvm_data
;
for
(
i
=
offset
;
i
<
(
NVM_CHECKSUM_REG
+
offset
);
i
++
)
{
ret_val
=
hw
->
nvm
.
ops
.
read
(
hw
,
i
,
1
,
&
nvm_data
);
if
(
ret_val
)
{
hw_dbg
(
"NVM Read Error while updating checksum.
\n
"
);
goto
out
;
}
checksum
+=
nvm_data
;
}
checksum
=
(
u16
)
NVM_SUM
-
checksum
;
ret_val
=
hw
->
nvm
.
ops
.
write
(
hw
,
(
NVM_CHECKSUM_REG
+
offset
),
1
,
&
checksum
);
if
(
ret_val
)
hw_dbg
(
"NVM Write Error while updating checksum.
\n
"
);
out:
return
ret_val
;
}
/**
* igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
* @hw: pointer to the HW structure
*
* Calculates the EEPROM section checksum by reading/adding each word of
* the EEPROM and then verifies that the sum of the EEPROM is
* equal to 0xBABA.
**/
static
s32
igb_validate_nvm_checksum_82580
(
struct
e1000_hw
*
hw
)
{
s32
ret_val
=
0
;
u16
eeprom_regions_count
=
1
;
u16
j
,
nvm_data
;
u16
nvm_offset
;
ret_val
=
hw
->
nvm
.
ops
.
read
(
hw
,
NVM_COMPATIBILITY_REG_3
,
1
,
&
nvm_data
);
if
(
ret_val
)
{
hw_dbg
(
"NVM Read Error
\n
"
);
goto
out
;
}
if
(
nvm_data
&
NVM_COMPATIBILITY_BIT_MASK
)
{
/* if chekcsums compatibility bit is set validate checksums
* for all 4 ports. */
eeprom_regions_count
=
4
;
}
for
(
j
=
0
;
j
<
eeprom_regions_count
;
j
++
)
{
nvm_offset
=
NVM_82580_LAN_FUNC_OFFSET
(
j
);
ret_val
=
igb_validate_nvm_checksum_with_offset
(
hw
,
nvm_offset
);
if
(
ret_val
!=
0
)
goto
out
;
}
out:
return
ret_val
;
}
/**
* igb_update_nvm_checksum_82580 - Update EEPROM checksum
* @hw: pointer to the HW structure
*
* Updates the EEPROM section checksums for all 4 ports by reading/adding
* each word of the EEPROM up to the checksum. Then calculates the EEPROM
* checksum and writes the value to the EEPROM.
**/
static
s32
igb_update_nvm_checksum_82580
(
struct
e1000_hw
*
hw
)
{
s32
ret_val
;
u16
j
,
nvm_data
;
u16
nvm_offset
;
ret_val
=
hw
->
nvm
.
ops
.
read
(
hw
,
NVM_COMPATIBILITY_REG_3
,
1
,
&
nvm_data
);
if
(
ret_val
)
{
hw_dbg
(
"NVM Read Error while updating checksum"
" compatibility bit.
\n
"
);
goto
out
;
}
if
((
nvm_data
&
NVM_COMPATIBILITY_BIT_MASK
)
==
0
)
{
/* set compatibility bit to validate checksums appropriately */
nvm_data
=
nvm_data
|
NVM_COMPATIBILITY_BIT_MASK
;
ret_val
=
hw
->
nvm
.
ops
.
write
(
hw
,
NVM_COMPATIBILITY_REG_3
,
1
,
&
nvm_data
);
if
(
ret_val
)
{
hw_dbg
(
"NVM Write Error while updating checksum"
" compatibility bit.
\n
"
);
goto
out
;
}
}
for
(
j
=
0
;
j
<
4
;
j
++
)
{
nvm_offset
=
NVM_82580_LAN_FUNC_OFFSET
(
j
);
ret_val
=
igb_update_nvm_checksum_with_offset
(
hw
,
nvm_offset
);
if
(
ret_val
)
goto
out
;
}
out:
return
ret_val
;
}
/**
* igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
* @hw: pointer to the HW structure
*
* Calculates the EEPROM section checksum by reading/adding each word of
* the EEPROM and then verifies that the sum of the EEPROM is
* equal to 0xBABA.
**/
static
s32
igb_validate_nvm_checksum_i350
(
struct
e1000_hw
*
hw
)
{
s32
ret_val
=
0
;
u16
j
;
u16
nvm_offset
;
for
(
j
=
0
;
j
<
4
;
j
++
)
{
nvm_offset
=
NVM_82580_LAN_FUNC_OFFSET
(
j
);
ret_val
=
igb_validate_nvm_checksum_with_offset
(
hw
,
nvm_offset
);
if
(
ret_val
!=
0
)
goto
out
;
}
out:
return
ret_val
;
}
/**
* igb_update_nvm_checksum_i350 - Update EEPROM checksum
* @hw: pointer to the HW structure
*
* Updates the EEPROM section checksums for all 4 ports by reading/adding
* each word of the EEPROM up to the checksum. Then calculates the EEPROM
* checksum and writes the value to the EEPROM.
**/
static
s32
igb_update_nvm_checksum_i350
(
struct
e1000_hw
*
hw
)
{
s32
ret_val
=
0
;
u16
j
;
u16
nvm_offset
;
for
(
j
=
0
;
j
<
4
;
j
++
)
{
nvm_offset
=
NVM_82580_LAN_FUNC_OFFSET
(
j
);
ret_val
=
igb_update_nvm_checksum_with_offset
(
hw
,
nvm_offset
);
if
(
ret_val
!=
0
)
goto
out
;
}
out:
return
ret_val
;
}
/**
* igb_set_eee_i350 - Enable/disable EEE support
* @hw: pointer to the HW structure
*
* Enable/disable EEE based on setting in dev_spec structure.
*
**/
s32
igb_set_eee_i350
(
struct
e1000_hw
*
hw
)
{
s32
ret_val
=
0
;
u32
ipcnfg
,
eeer
,
ctrl_ext
;
ctrl_ext
=
rd32
(
E1000_CTRL_EXT
);
if
((
hw
->
mac
.
type
!=
e1000_i350
)
||
(
ctrl_ext
&
E1000_CTRL_EXT_LINK_MODE_MASK
))
goto
out
;
ipcnfg
=
rd32
(
E1000_IPCNFG
);
eeer
=
rd32
(
E1000_EEER
);
/* enable or disable per user setting */
if
(
!
(
hw
->
dev_spec
.
_82575
.
eee_disable
))
{
ipcnfg
|=
(
E1000_IPCNFG_EEE_1G_AN
|
E1000_IPCNFG_EEE_100M_AN
);
eeer
|=
(
E1000_EEER_TX_LPI_EN
|
E1000_EEER_RX_LPI_EN
|
E1000_EEER_LPI_FC
);
}
else
{
ipcnfg
&=
~
(
E1000_IPCNFG_EEE_1G_AN
|
E1000_IPCNFG_EEE_100M_AN
);
eeer
&=
~
(
E1000_EEER_TX_LPI_EN
|
E1000_EEER_RX_LPI_EN
|
E1000_EEER_LPI_FC
);
}
wr32
(
E1000_IPCNFG
,
ipcnfg
);
wr32
(
E1000_EEER
,
eeer
);
out:
return
ret_val
;
}
static
struct
e1000_mac_operations
e1000_mac_ops_82575
=
{
.
init_hw
=
igb_init_hw_82575
,
.
check_for_link
=
igb_check_for_link_82575
,
...
...
drivers/net/igb/e1000_82575.h
View file @
1561747d
...
...
@@ -251,5 +251,6 @@ void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
void
igb_vmdq_set_loopback_pf
(
struct
e1000_hw
*
,
bool
);
void
igb_vmdq_set_replication_pf
(
struct
e1000_hw
*
,
bool
);
u16
igb_rxpbs_adjust_82580
(
u32
data
);
s32
igb_set_eee_i350
(
struct
e1000_hw
*
);
#endif
drivers/net/igb/e1000_defines.h
View file @
1561747d
...
...
@@ -287,7 +287,34 @@
#define E1000_TCTL_COLD 0x003ff000
/* collision distance */
#define E1000_TCTL_RTLC 0x01000000
/* Re-transmit on late collision */
/* Transmit Arbitration Count */
/* DMA Coalescing register fields */
#define E1000_DMACR_DMACWT_MASK 0x00003FFF
/* DMA Coalescing
* Watchdog Timer */
#define E1000_DMACR_DMACTHR_MASK 0x00FF0000
/* DMA Coalescing Receive
* Threshold */
#define E1000_DMACR_DMACTHR_SHIFT 16
#define E1000_DMACR_DMAC_LX_MASK 0x30000000
/* Lx when no PCIe
* transactions */
#define E1000_DMACR_DMAC_LX_SHIFT 28
#define E1000_DMACR_DMAC_EN 0x80000000
/* Enable DMA Coalescing */
#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF
/* DMA Coalescing Transmit
* Threshold */
#define E1000_DMCTLX_TTLX_MASK 0x00000FFF
/* Time to LX request */
#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF
/* Receive Traffic Rate
* Threshold */
#define E1000_DMCRTRH_LRPRCW 0x80000000
/* Rcv packet rate in
* current window */
#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF
/* DMA Coal Rcv Traffic
* Current Cnt */
#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0
/* Flow ctrl Rcv Threshold
* High val */
#define E1000_FCRTC_RTH_COAL_SHIFT 4
#define E1000_PCIEMISC_LX_DECISION 0x00000080
/* Lx power decision */
/* SerDes Control */
#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
...
...
@@ -566,6 +593,8 @@
#define NVM_INIT_CONTROL3_PORT_A 0x0024
#define NVM_ALT_MAC_ADDR_PTR 0x0037
#define NVM_CHECKSUM_REG 0x003F
#define NVM_COMPATIBILITY_REG_3 0x0003
#define NVM_COMPATIBILITY_BIT_MASK 0x8000
#define E1000_NVM_CFG_DONE_PORT_0 0x040000
/* MNG config cycle done */
#define E1000_NVM_CFG_DONE_PORT_1 0x080000
/* ...for second port */
...
...
@@ -600,6 +629,7 @@
/* NVM Commands - SPI */
#define NVM_MAX_RETRY_SPI 5000
/* Max wait of 5ms, for RDY signal */
#define NVM_WRITE_OPCODE_SPI 0x02
/* NVM write opcode */
#define NVM_READ_OPCODE_SPI 0x03
/* NVM read opcode */
#define NVM_A8_OPCODE_SPI 0x08
/* opcode bit-3 = address bit-8 */
#define NVM_WREN_OPCODE_SPI 0x06
/* NVM set Write Enable latch */
#define NVM_RDSR_OPCODE_SPI 0x05
/* NVM read Status register */
...
...
@@ -758,6 +788,13 @@
#define E1000_MDIC_ERROR 0x40000000
#define E1000_MDIC_DEST 0x80000000
/* Energy Efficient Ethernet */
#define E1000_IPCNFG_EEE_1G_AN 0x00000008
/* EEE Enable 1G AN */
#define E1000_IPCNFG_EEE_100M_AN 0x00000004
/* EEE Enable 100M AN */
#define E1000_EEER_TX_LPI_EN 0x00010000
/* EEE Tx LPI Enable */
#define E1000_EEER_RX_LPI_EN 0x00020000
/* EEE Rx LPI Enable */
#define E1000_EEER_LPI_FC 0x00040000
/* EEE Enable on FC */
/* SerDes Control */
#define E1000_GEN_CTL_READY 0x80000000
#define E1000_GEN_CTL_ADDRESS_SHIFT 8
...
...
drivers/net/igb/e1000_hw.h
View file @
1561747d
...
...
@@ -336,6 +336,8 @@ struct e1000_nvm_operations {
s32
(
*
read
)(
struct
e1000_hw
*
,
u16
,
u16
,
u16
*
);
void
(
*
release
)(
struct
e1000_hw
*
);
s32
(
*
write
)(
struct
e1000_hw
*
,
u16
,
u16
,
u16
*
);
s32
(
*
update
)(
struct
e1000_hw
*
);
s32
(
*
validate
)(
struct
e1000_hw
*
);
};
struct
e1000_info
{
...
...
@@ -422,7 +424,6 @@ struct e1000_phy_info {
struct
e1000_nvm_info
{
struct
e1000_nvm_operations
ops
;
enum
e1000_nvm_type
type
;
enum
e1000_nvm_override
override
;
...
...
@@ -488,6 +489,7 @@ struct e1000_mbx_info {
struct
e1000_dev_spec_82575
{
bool
sgmii_active
;
bool
global_device_reset
;
bool
eee_disable
;
};
struct
e1000_hw
{
...
...
drivers/net/igb/e1000_nvm.c
View file @
1561747d
...
...
@@ -317,6 +317,68 @@ static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
return
ret_val
;
}
/**
* igb_read_nvm_spi - Read EEPROM's using SPI
* @hw: pointer to the HW structure
* @offset: offset of word in the EEPROM to read
* @words: number of words to read
* @data: word read from the EEPROM
*
* Reads a 16 bit word from the EEPROM.
**/
s32
igb_read_nvm_spi
(
struct
e1000_hw
*
hw
,
u16
offset
,
u16
words
,
u16
*
data
)
{
struct
e1000_nvm_info
*
nvm
=
&
hw
->
nvm
;
u32
i
=
0
;
s32
ret_val
;
u16
word_in
;
u8
read_opcode
=
NVM_READ_OPCODE_SPI
;
/*
* A check for invalid values: offset too large, too many words,
* and not enough words.
*/
if
((
offset
>=
nvm
->
word_size
)
||
(
words
>
(
nvm
->
word_size
-
offset
))
||
(
words
==
0
))
{
hw_dbg
(
"nvm parameter(s) out of bounds
\n
"
);
ret_val
=
-
E1000_ERR_NVM
;
goto
out
;
}
ret_val
=
nvm
->
ops
.
acquire
(
hw
);
if
(
ret_val
)
goto
out
;
ret_val
=
igb_ready_nvm_eeprom
(
hw
);
if
(
ret_val
)
goto
release
;
igb_standby_nvm
(
hw
);
if
((
nvm
->
address_bits
==
8
)
&&
(
offset
>=
128
))
read_opcode
|=
NVM_A8_OPCODE_SPI
;
/* Send the READ command (opcode + addr) */
igb_shift_out_eec_bits
(
hw
,
read_opcode
,
nvm
->
opcode_bits
);
igb_shift_out_eec_bits
(
hw
,
(
u16
)(
offset
*
2
),
nvm
->
address_bits
);
/*
* Read the data. SPI NVMs increment the address with each byte
* read and will roll over if reading beyond the end. This allows
* us to read the whole NVM from any offset
*/
for
(
i
=
0
;
i
<
words
;
i
++
)
{
word_in
=
igb_shift_in_eec_bits
(
hw
,
16
);
data
[
i
]
=
(
word_in
>>
8
)
|
(
word_in
<<
8
);
}
release:
nvm
->
ops
.
release
(
hw
);
out:
return
ret_val
;
}
/**
* igb_read_nvm_eerd - Reads EEPROM using EERD register
* @hw: pointer to the HW structure
...
...
@@ -353,7 +415,7 @@ s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
break
;
data
[
i
]
=
(
rd32
(
E1000_EERD
)
>>
E1000_NVM_RW_REG_DATA
);
E1000_NVM_RW_REG_DATA
);
}
out:
...
...
drivers/net/igb/e1000_nvm.h
View file @
1561747d
...
...
@@ -35,6 +35,7 @@ s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num);
s32
igb_read_part_string
(
struct
e1000_hw
*
hw
,
u8
*
part_num
,
u32
part_num_size
);
s32
igb_read_nvm_eerd
(
struct
e1000_hw
*
hw
,
u16
offset
,
u16
words
,
u16
*
data
);
s32
igb_read_nvm_spi
(
struct
e1000_hw
*
hw
,
u16
offset
,
u16
words
,
u16
*
data
);
s32
igb_write_nvm_spi
(
struct
e1000_hw
*
hw
,
u16
offset
,
u16
words
,
u16
*
data
);
s32
igb_validate_nvm_checksum
(
struct
e1000_hw
*
hw
);
s32
igb_update_nvm_checksum
(
struct
e1000_hw
*
hw
);
...
...
drivers/net/igb/e1000_regs.h
View file @
1561747d
...
...
@@ -106,6 +106,15 @@
#define E1000_RQDPC(_n) (0x0C030 + ((_n) * 0x40))
/* DMA Coalescing registers */
#define E1000_DMACR 0x02508
/* Control Register */
#define E1000_DMCTXTH 0x03550
/* Transmit Threshold */
#define E1000_DMCTLX 0x02514
/* Time to Lx Request */
#define E1000_DMCRTRH 0x05DD0
/* Receive Packet Rate Threshold */
#define E1000_DMCCNT 0x05DD4
/* Current Rx Count */
#define E1000_FCRTC 0x02170
/* Flow Control Rx high watermark */
#define E1000_PCIEMISC 0x05BB8
/* PCIE misc config register */
/* TX Rate Limit Registers */
#define E1000_RTTDQSEL 0x3604
/* Tx Desc Plane Queue Select - WO */
#define E1000_RTTBCNRC 0x36B0
/* Tx BCN Rate-Scheduler Config - WO */
...
...
@@ -329,6 +338,10 @@
/* DMA Coalescing registers */
#define E1000_PCIEMISC 0x05BB8
/* PCIE misc config register */
/* Energy Efficient Ethernet "EEE" register */
#define E1000_IPCNFG 0x0E38
/* Internal PHY Configuration */
#define E1000_EEER 0x0E30
/* Energy Efficient Ethernet */
/* OS2BMC Registers */
#define E1000_B2OSPC 0x08FE0
/* BMC2OS packets sent by BMC */
#define E1000_B2OGPRC 0x04158
/* BMC2OS packets received by host */
...
...
drivers/net/igb/igb.h
View file @
1561747d
...
...
@@ -333,6 +333,12 @@ struct igb_adapter {
#define IGB_FLAG_DCA_ENABLED (1 << 1)
#define IGB_FLAG_QUAD_PORT_A (1 << 2)
#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
#define IGB_FLAG_DMAC (1 << 4)
/* DMA Coalescing defines */
#define IGB_MIN_TXPBSIZE 20408
#define IGB_TX_BUF_4096 4096
#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000
/* Disable DMA Coal Flush */
#define IGB_82576_TSYNC_SHIFT 19
#define IGB_82580_TSYNC_SHIFT 24
...
...
drivers/net/igb/igb_ethtool.c
View file @
1561747d
...
...
@@ -721,7 +721,7 @@ static int igb_set_eeprom(struct net_device *netdev,
/* Update the checksum over the first part of the EEPROM if needed
* and flush shadow RAM for 82573 controllers */
if
((
ret_val
==
0
)
&&
((
first_word
<=
NVM_CHECKSUM_REG
)))
igb_update_nvm_checksum
(
hw
);
hw
->
nvm
.
ops
.
update
(
hw
);
kfree
(
eeprom_buff
);
return
ret_val
;
...
...
@@ -2009,6 +2009,12 @@ static int igb_set_coalesce(struct net_device *netdev,
if
((
adapter
->
flags
&
IGB_FLAG_QUEUE_PAIRS
)
&&
ec
->
tx_coalesce_usecs
)
return
-
EINVAL
;
/* If ITR is disabled, disable DMAC */
if
(
ec
->
rx_coalesce_usecs
==
0
)
{
if
(
adapter
->
flags
&
IGB_FLAG_DMAC
)
adapter
->
flags
&=
~
IGB_FLAG_DMAC
;
}
/* convert to rate of irq's per second */
if
(
ec
->
rx_coalesce_usecs
&&
ec
->
rx_coalesce_usecs
<=
3
)
adapter
->
rx_itr_setting
=
ec
->
rx_coalesce_usecs
;
...
...
drivers/net/igb/igb_main.c
View file @
1561747d
...
...
@@ -50,7 +50,12 @@
#endif
#include
"igb.h"
#define DRV_VERSION "2.4.13-k2"
#define MAJ 3
#define MIN 0
#define BUILD 6
#define KFIX 2
#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
__stringify(BUILD) "-k" __stringify(KFIX)
char
igb_driver_name
[]
=
"igb"
;
char
igb_driver_version
[]
=
DRV_VERSION
;
static
const
char
igb_driver_string
[]
=
...
...
@@ -1674,7 +1679,58 @@ void igb_reset(struct igb_adapter *adapter)
if
(
hw
->
mac
.
ops
.
init_hw
(
hw
))
dev_err
(
&
pdev
->
dev
,
"Hardware Error
\n
"
);
if
(
hw
->
mac
.
type
>
e1000_82580
)
{
if
(
adapter
->
flags
&
IGB_FLAG_DMAC
)
{
u32
reg
;
/*
* DMA Coalescing high water mark needs to be higher
* than * the * Rx threshold. The Rx threshold is
* currently * pba - 6, so we * should use a high water
* mark of pba * - 4. */
hwm
=
(
pba
-
4
)
<<
10
;
reg
=
(((
pba
-
6
)
<<
E1000_DMACR_DMACTHR_SHIFT
)
&
E1000_DMACR_DMACTHR_MASK
);
/* transition to L0x or L1 if available..*/
reg
|=
(
E1000_DMACR_DMAC_EN
|
E1000_DMACR_DMAC_LX_MASK
);
/* watchdog timer= +-1000 usec in 32usec intervals */
reg
|=
(
1000
>>
5
);
wr32
(
E1000_DMACR
,
reg
);
/* no lower threshold to disable coalescing(smart fifb)
* -UTRESH=0*/
wr32
(
E1000_DMCRTRH
,
0
);
/* set hwm to PBA - 2 * max frame size */
wr32
(
E1000_FCRTC
,
hwm
);
/*
* This sets the time to wait before requesting tran-
* sition to * low power state to number of usecs needed
* to receive 1 512 * byte frame at gigabit line rate
*/
reg
=
rd32
(
E1000_DMCTLX
);
reg
|=
IGB_DMCTLX_DCFLUSH_DIS
;
/* Delay 255 usec before entering Lx state. */
reg
|=
0xFF
;
wr32
(
E1000_DMCTLX
,
reg
);
/* free space in Tx packet buffer to wake from DMAC */
wr32
(
E1000_DMCTXTH
,