Commit 20fd5767 authored by Arnaud Patard's avatar Arnaud Patard Committed by Linus Torvalds
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[PATCH] s3c2410fb: ARM S3C2410 framebuffer driver



This set of two patches add support for the framebuffer of the Samsung S3C2410
ARM SoC.  This driver was started about one year ago and is now used on iPAQ
h1930/h1940, Acer n30 and probably other s3c2410-based machines I'm not aware
of.  I've also heard yesterday that it's working also on iPAQ rx3715/rx3115
(s3c2440-based machines).
Signed-Off-By: default avatarArnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: default avatarAntonino Daplas <adaplas@pol.net>
Signed-off-by: default avatarBen Dooks <ben@trinity.fluff.org>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 3b4abffb
......@@ -1516,6 +1516,30 @@ config FB_S1D13XXX
working with S1D13806). Product specs at
<http://www.erd.epson.com/vdc/html/legacy_13xxx.htm>
config FB_S3C2410
tristate "S3C2410 LCD framebuffer support"
depends on FB && ARCH_S3C2410
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
select FB_SOFT_CURSOR
---help---
Frame buffer driver for the built-in LCD controller in the Samsung
S3C2410 processor.
This driver is also available as a module ( = code which can be
inserted and removed from the running kernel whenever you want). The
module will be called s3c2410fb. If you want to compile it as a module,
say M here and read <file:Documentation/modules.txt>.
If unsure, say N.
config FB_S3C2410_DEBUG
bool "S3C2410 lcd debug messages"
depends on FB_S3C2410
help
Turn on debugging messages. Note that you can set/unset at run time
through sysfs
config FB_VIRTUAL
tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
depends on FB
......
......@@ -94,6 +94,7 @@ obj-$(CONFIG_FB_MAXINE) += maxinefb.o
obj-$(CONFIG_FB_TX3912) += tx3912fb.o
obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o
obj-$(CONFIG_FB_IMX) += imxfb.o
obj-$(CONFIG_FB_S3C2410) += s3c2410fb.o
# Platform or fallback drivers go here
obj-$(CONFIG_FB_VESA) += vesafb.o
......
This diff is collapsed.
/*
* linux/drivers/s3c2410fb.h
* Copyright (c) Arnaud Patard
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* S3C2410 LCD Controller Frame Buffer Driver
* based on skeletonfb.c, sa1100fb.h
*
* ChangeLog
*
* 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
* - Moved dprintk to s3c2410fb.c
*
* 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
* - Renamed from h1940fb.h to s3c2410fb.h
* - Chenged h1940 to s3c2410
*
* 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
* - First version
*/
#ifndef __S3C2410FB_H
#define __S3C2410FB_H
struct s3c2410fb_info {
struct fb_info *fb;
struct device *dev;
struct clk *clk;
struct s3c2410fb_mach_info *mach_info;
/* raw memory addresses */
dma_addr_t map_dma; /* physical */
u_char * map_cpu; /* virtual */
u_int map_size;
struct s3c2410fb_hw regs;
/* addresses of pieces placed in raw buffer */
u_char * screen_cpu; /* virtual address of buffer */
dma_addr_t screen_dma; /* physical address of buffer */
unsigned int palette_ready;
/* keep these registers in case we need to re-write palette */
u32 palette_buffer[256];
u32 pseudo_pal[16];
};
#define PALETTE_BUFF_CLEAR (0x80000000) /* entry is clear/invalid */
int s3c2410fb_init(void);
#endif
/* linux/include/asm/arch-s3c2410/fb.h
*
* Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
*
* Inspired by pxafb.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
* Changelog:
* 07-Sep-2004 RTP Created file
* 03-Nov-2004 BJD Updated and minor cleanups
* 03-Aug-2005 RTP Renamed to fb.h
*/
#ifndef __ASM_ARM_FB_H
#define __ASM_ARM_FB_H
#include <asm/arch/regs-lcd.h>
struct s3c2410fb_val {
unsigned int defval;
unsigned int min;
unsigned int max;
};
struct s3c2410fb_hw {
unsigned long lcdcon1;
unsigned long lcdcon2;
unsigned long lcdcon3;
unsigned long lcdcon4;
unsigned long lcdcon5;
};
struct s3c2410fb_mach_info {
unsigned char fixed_syncs; /* do not update sync/border */
/* Screen size */
int width;
int height;
/* Screen info */
struct s3c2410fb_val xres;
struct s3c2410fb_val yres;
struct s3c2410fb_val bpp;
/* lcd configuration registers */
struct s3c2410fb_hw regs;
/* GPIOs */
unsigned long gpcup;
unsigned long gpcup_mask;
unsigned long gpccon;
unsigned long gpccon_mask;
unsigned long gpdup;
unsigned long gpdup_mask;
unsigned long gpdcon;
unsigned long gpdcon_mask;
/* lpc3600 control register */
unsigned long lpcsel;
};
void __init set_s3c2410fb_info(struct s3c2410fb_mach_info *hard_s3c2410fb_info);
#endif /* __ASM_ARM_FB_H */
......@@ -51,21 +51,32 @@
#define S3C2410_LCDCON1_ENVID (1)
#define S3C2410_LCDCON1_MODEMASK 0x1E
#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
#define S3C2410_LCDCON5_BPP24BL (1<<12)
#define S3C2410_LCDCON5_FRM565 (1<<11)
#define S3C2410_LCDCON5_INVVCLK (1<<10)
......@@ -100,10 +111,16 @@
#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
#define S3C2410_TPAL S3C2410_LCDREG(0x50)
#define S3C2410_TPAL_EN (1<<24)
/* interrupt info */
#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
#define S3C2410_LCDINT_FIWSEL (1<<2)
#define S3C2410_LCDINT_FRSYNC (1<<1)
#define S3C2410_LCDINT_FICNT (1<<0)
#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
......
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