Commit 25a64025 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/sec: namespace + nvidia gpu names (no binary change)



The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 4d34686e
#ifndef __NVKM_SEC_H__
#define __NVKM_SEC_H__
extern struct nouveau_oclass nv98_sec_oclass;
#include <core/engine.h>
extern struct nvkm_oclass g98_sec_oclass;
#endif
......@@ -255,7 +255,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
......@@ -313,7 +313,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
......@@ -342,7 +342,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &nv98_sec_oclass;
device->oclass[NVDEV_ENGINE_SEC ] = &g98_sec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &g98_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &g98_msppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = g94_disp_oclass;
......
nvkm-y += nvkm/engine/sec/nv98.o
nvkm-y += nvkm/engine/sec/g98.o
/*
* fuc microcode for nv98 psec engine
* fuc microcode for g98 psec engine
* Copyright (C) 2010 Marcin Kościelnicki
*
* This program is free software; you can redistribute it and/or modify
......@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
.section #nv98_psec_data
.section #g98_psec_data
ctx_dma:
ctx_dma_query: .b32 0
......@@ -94,7 +94,7 @@ sec_dtable:
.align 0x100
.section #nv98_psec_code
.section #g98_psec_code
// $r0 is always set to 0 in our code - this allows some space savings.
clear b32 $r0
......
uint32_t nv98_psec_data[] = {
uint32_t g98_psec_data[] = {
/* 0x0000: ctx_dma */
/* 0x0000: ctx_dma_query */
0x00000000,
......@@ -150,7 +150,7 @@ uint32_t nv98_psec_data[] = {
0x00000000,
};
uint32_t nv98_psec_code[] = {
uint32_t g98_psec_code[] = {
0x17f004bd,
0x0010fe35,
0xf10004fe,
......
......@@ -21,32 +21,25 @@
*
* Authors: Ben Skeggs
*/
#include <engine/sec.h>
#include <engine/falcon.h>
#include "fuc/g98.fuc0s.h"
#include <core/client.h>
#include <core/os.h>
#include <core/enum.h>
#include <core/engctx.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <engine/falcon.h>
#include <engine/fifo.h>
#include <engine/sec.h>
#include "fuc/nv98.fuc0s.h"
struct nv98_sec_priv {
struct nouveau_falcon base;
struct g98_sec_priv {
struct nvkm_falcon base;
};
/*******************************************************************************
* Crypt object classes
******************************************************************************/
static struct nouveau_oclass
nv98_sec_sclass[] = {
{ 0x88b4, &nouveau_object_ofuncs },
static struct nvkm_oclass
g98_sec_sclass[] = {
{ 0x88b4, &nvkm_object_ofuncs },
{},
};
......@@ -54,16 +47,16 @@ nv98_sec_sclass[] = {
* PSEC context
******************************************************************************/
static struct nouveau_oclass
nv98_sec_cclass = {
static struct nvkm_oclass
g98_sec_cclass = {
.handle = NV_ENGCTX(SEC, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = _nouveau_falcon_context_ctor,
.dtor = _nouveau_falcon_context_dtor,
.init = _nouveau_falcon_context_init,
.fini = _nouveau_falcon_context_fini,
.rd32 = _nouveau_falcon_context_rd32,
.wr32 = _nouveau_falcon_context_wr32,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = _nvkm_falcon_context_ctor,
.dtor = _nvkm_falcon_context_dtor,
.init = _nvkm_falcon_context_init,
.fini = _nvkm_falcon_context_fini,
.rd32 = _nvkm_falcon_context_rd32,
.wr32 = _nvkm_falcon_context_wr32,
},
};
......@@ -71,7 +64,7 @@ nv98_sec_cclass = {
* PSEC engine/subdev functions
******************************************************************************/
static const struct nouveau_enum nv98_sec_isr_error_name[] = {
static const struct nvkm_enum g98_sec_isr_error_name[] = {
{ 0x0000, "ILLEGAL_MTHD" },
{ 0x0001, "INVALID_BITFIELD" },
{ 0x0002, "INVALID_ENUM" },
......@@ -80,12 +73,12 @@ static const struct nouveau_enum nv98_sec_isr_error_name[] = {
};
static void
nv98_sec_intr(struct nouveau_subdev *subdev)
g98_sec_intr(struct nvkm_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
struct nv98_sec_priv *priv = (void *)subdev;
struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
struct nvkm_engine *engine = nv_engine(subdev);
struct nvkm_object *engctx;
struct g98_sec_priv *priv = (void *)subdev;
u32 disp = nv_rd32(priv, 0x08701c);
u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16);
u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff;
......@@ -96,14 +89,14 @@ nv98_sec_intr(struct nouveau_subdev *subdev)
u32 data = nv_rd32(priv, 0x087044);
int chid;
engctx = nouveau_engctx_get(engine, inst);
engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x00000040) {
nv_error(priv, "DISPATCH_ERROR [");
nouveau_enum_print(nv98_sec_isr_error_name, ssta);
nvkm_enum_print(g98_sec_isr_error_name, ssta);
pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, nouveau_client_name(engctx),
chid, (u64)inst << 12, nvkm_client_name(engctx),
subc, mthd, data);
nv_wr32(priv, 0x087004, 0x00000040);
stat &= ~0x00000040;
......@@ -114,43 +107,43 @@ nv98_sec_intr(struct nouveau_subdev *subdev)
nv_wr32(priv, 0x087004, stat);
}
nouveau_engctx_put(engctx);
nvkm_engctx_put(engctx);
}
static int
nv98_sec_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv98_sec_priv *priv;
struct g98_sec_priv *priv;
int ret;
ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true,
"PSEC", "sec", &priv);
ret = nvkm_falcon_create(parent, engine, oclass, 0x087000, true,
"PSEC", "sec", &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00004000;
nv_subdev(priv)->intr = nv98_sec_intr;
nv_engine(priv)->cclass = &nv98_sec_cclass;
nv_engine(priv)->sclass = nv98_sec_sclass;
nv_falcon(priv)->code.data = nv98_psec_code;
nv_falcon(priv)->code.size = sizeof(nv98_psec_code);
nv_falcon(priv)->data.data = nv98_psec_data;
nv_falcon(priv)->data.size = sizeof(nv98_psec_data);
nv_subdev(priv)->intr = g98_sec_intr;
nv_engine(priv)->cclass = &g98_sec_cclass;
nv_engine(priv)->sclass = g98_sec_sclass;
nv_falcon(priv)->code.data = g98_psec_code;
nv_falcon(priv)->code.size = sizeof(g98_psec_code);
nv_falcon(priv)->data.data = g98_psec_data;
nv_falcon(priv)->data.size = sizeof(g98_psec_data);
return 0;
}
struct nouveau_oclass
nv98_sec_oclass = {
struct nvkm_oclass
g98_sec_oclass = {
.handle = NV_ENGINE(SEC, 0x98),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv98_sec_ctor,
.dtor = _nouveau_falcon_dtor,
.init = _nouveau_falcon_init,
.fini = _nouveau_falcon_fini,
.rd32 = _nouveau_falcon_rd32,
.wr32 = _nouveau_falcon_wr32,
.ofuncs = &(struct nvkm_ofuncs) {
.ctor = g98_sec_ctor,
.dtor = _nvkm_falcon_dtor,
.init = _nvkm_falcon_init,
.fini = _nvkm_falcon_fini,
.rd32 = _nvkm_falcon_rd32,
.wr32 = _nvkm_falcon_wr32,
},
};
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