Commit 349ac71f authored by jubin.john@intel.com's avatar jubin.john@intel.com Committed by Doug Ledford
Browse files

staging/hfi1: Use BIT macro



This patch fixes the checkpatch issue:
CHECK: Prefer using the BIT macro

Use of BIT macro for HDRQ_INCREMENT in chip.h causes a change in
format specifier for error message in init.c in order to avoid a
build warning.
Reviewed-by: default avatarDean Luick <dean.luick@intel.com>
Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Reviewed-by: default avatarMike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: default avatarJubin John <jubin.john@intel.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent a06e825a
......@@ -242,18 +242,18 @@
#define HCMD_SUCCESS 2
/* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR - error flags */
#define SPICO_ROM_FAILED (1 << 0)
#define UNKNOWN_FRAME (1 << 1)
#define TARGET_BER_NOT_MET (1 << 2)
#define FAILED_SERDES_INTERNAL_LOOPBACK (1 << 3)
#define FAILED_SERDES_INIT (1 << 4)
#define FAILED_LNI_POLLING (1 << 5)
#define FAILED_LNI_DEBOUNCE (1 << 6)
#define FAILED_LNI_ESTBCOMM (1 << 7)
#define FAILED_LNI_OPTEQ (1 << 8)
#define FAILED_LNI_VERIFY_CAP1 (1 << 9)
#define FAILED_LNI_VERIFY_CAP2 (1 << 10)
#define FAILED_LNI_CONFIGLT (1 << 11)
#define SPICO_ROM_FAILED BIT(0)
#define UNKNOWN_FRAME BIT(1)
#define TARGET_BER_NOT_MET BIT(2)
#define FAILED_SERDES_INTERNAL_LOOPBACK BIT(3)
#define FAILED_SERDES_INIT BIT(4)
#define FAILED_LNI_POLLING BIT(5)
#define FAILED_LNI_DEBOUNCE BIT(6)
#define FAILED_LNI_ESTBCOMM BIT(7)
#define FAILED_LNI_OPTEQ BIT(8)
#define FAILED_LNI_VERIFY_CAP1 BIT(9)
#define FAILED_LNI_VERIFY_CAP2 BIT(10)
#define FAILED_LNI_CONFIGLT BIT(11)
#define FAILED_LNI (FAILED_LNI_POLLING | FAILED_LNI_DEBOUNCE \
| FAILED_LNI_ESTBCOMM | FAILED_LNI_OPTEQ \
......@@ -262,16 +262,16 @@
| FAILED_LNI_CONFIGLT)
/* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG - host message flags */
#define HOST_REQ_DONE (1 << 0)
#define BC_PWR_MGM_MSG (1 << 1)
#define BC_SMA_MSG (1 << 2)
#define BC_BCC_UNKOWN_MSG (1 << 3)
#define BC_IDLE_UNKNOWN_MSG (1 << 4)
#define EXT_DEVICE_CFG_REQ (1 << 5)
#define VERIFY_CAP_FRAME (1 << 6)
#define LINKUP_ACHIEVED (1 << 7)
#define LINK_GOING_DOWN (1 << 8)
#define LINK_WIDTH_DOWNGRADED (1 << 9)
#define HOST_REQ_DONE BIT(0)
#define BC_PWR_MGM_MSG BIT(1)
#define BC_SMA_MSG BIT(2)
#define BC_BCC_UNKNOWN_MSG BIT(3)
#define BC_IDLE_UNKNOWN_MSG BIT(4)
#define EXT_DEVICE_CFG_REQ BIT(5)
#define VERIFY_CAP_FRAME BIT(6)
#define LINKUP_ACHIEVED BIT(7)
#define LINK_GOING_DOWN BIT(8)
#define LINK_WIDTH_DOWNGRADED BIT(9)
/* DC_DC8051_CFG_EXT_DEV_1.REQ_TYPE - 8051 host requests */
#define HREQ_LOAD_CONFIG 0x01
......@@ -335,14 +335,14 @@
* the CSR fields hold multiples of this value.
*/
#define RCV_SHIFT 3
#define RCV_INCREMENT (1 << RCV_SHIFT)
#define RCV_INCREMENT BIT(RCV_SHIFT)
/*
* Receive header queue entry increment - the CSR holds multiples of
* this value.
*/
#define HDRQ_SIZE_SHIFT 5
#define HDRQ_INCREMENT (1 << HDRQ_SIZE_SHIFT)
#define HDRQ_INCREMENT BIT(HDRQ_SIZE_SHIFT)
/*
* Freeze handling flags
......
......@@ -349,10 +349,10 @@ struct hfi1_message_header {
#define HFI1_QPN_MASK 0xFFFFFF
#define HFI1_FECN_SHIFT 31
#define HFI1_FECN_MASK 1
#define HFI1_FECN_SMASK (1 << HFI1_FECN_SHIFT)
#define HFI1_FECN_SMASK BIT(HFI1_FECN_SHIFT)
#define HFI1_BECN_SHIFT 30
#define HFI1_BECN_MASK 1
#define HFI1_BECN_SMASK (1 << HFI1_BECN_SHIFT)
#define HFI1_BECN_SMASK BIT(HFI1_BECN_SHIFT)
#define HFI1_MULTICAST_LID_BASE 0xC000
static inline __u64 rhf_to_cpu(const __le32 *rbuf)
......
......@@ -424,17 +424,17 @@ struct hfi1_sge_state;
#define __HLS_GOING_OFFLINE_BP 9
#define __HLS_LINK_COOLDOWN_BP 10
#define HLS_UP_INIT (1 << __HLS_UP_INIT_BP)
#define HLS_UP_ARMED (1 << __HLS_UP_ARMED_BP)
#define HLS_UP_ACTIVE (1 << __HLS_UP_ACTIVE_BP)
#define HLS_DN_DOWNDEF (1 << __HLS_DN_DOWNDEF_BP) /* link down default */
#define HLS_DN_POLL (1 << __HLS_DN_POLL_BP)
#define HLS_DN_DISABLE (1 << __HLS_DN_DISABLE_BP)
#define HLS_DN_OFFLINE (1 << __HLS_DN_OFFLINE_BP)
#define HLS_VERIFY_CAP (1 << __HLS_VERIFY_CAP_BP)
#define HLS_GOING_UP (1 << __HLS_GOING_UP_BP)
#define HLS_GOING_OFFLINE (1 << __HLS_GOING_OFFLINE_BP)
#define HLS_LINK_COOLDOWN (1 << __HLS_LINK_COOLDOWN_BP)
#define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
#define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
#define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
#define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
#define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
#define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
#define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
#define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
#define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
#define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
#define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
#define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
......
......@@ -260,7 +260,7 @@ struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, u32 ctxt)
/* Validate and initialize Rcv Hdr Q variables */
if (rcvhdrcnt % HDRQ_INCREMENT) {
dd_dev_err(dd,
"ctxt%u: header queue count %d must be divisible by %d\n",
"ctxt%u: header queue count %d must be divisible by %lu\n",
rcd->ctxt, rcvhdrcnt, HDRQ_INCREMENT);
goto bail;
}
......
......@@ -1782,7 +1782,7 @@ static int __subn_get_opa_cable_info(struct opa_smp *smp, u32 am, u8 *data,
u32 len = OPA_AM_CI_LEN(am) + 1;
int ret;
#define __CI_PAGE_SIZE (1 << 7) /* 128 bytes */
#define __CI_PAGE_SIZE BIT(7) /* 128 bytes */
#define __CI_PAGE_MASK ~(__CI_PAGE_SIZE - 1)
#define __CI_PAGE_NUM(a) ((a) & __CI_PAGE_MASK)
......@@ -3402,7 +3402,7 @@ struct opa_led_info {
};
#define OPA_LED_SHIFT 31
#define OPA_LED_MASK (1 << OPA_LED_SHIFT)
#define OPA_LED_MASK BIT(OPA_LED_SHIFT)
static int __subn_get_opa_led_info(struct opa_smp *smp, u32 am, u8 *data,
struct ib_device *ibdev, u8 port,
......
......@@ -54,7 +54,7 @@
#include "verbs.h"
#include "sdma.h"
#define QPN_MAX (1 << 24)
#define QPN_MAX BIT(24)
#define QPNMAP_ENTRIES (QPN_MAX / PAGE_SIZE / BITS_PER_BYTE)
/*
......
......@@ -59,11 +59,11 @@
* Below are masks for QSFP pins. Pins are the same for HFI0 and HFI1.
* _N means asserted low
*/
#define QSFP_HFI0_I2CCLK (1 << 0)
#define QSFP_HFI0_I2CDAT (1 << 1)
#define QSFP_HFI0_RESET_N (1 << 2)
#define QSFP_HFI0_INT_N (1 << 3)
#define QSFP_HFI0_MODPRST_N (1 << 4)
#define QSFP_HFI0_I2CCLK BIT(0)
#define QSFP_HFI0_I2CDAT BIT(1)
#define QSFP_HFI0_RESET_N BIT(2)
#define QSFP_HFI0_INT_N BIT(3)
#define QSFP_HFI0_MODPRST_N BIT(4)
/* QSFP is paged at 256 bytes */
#define QSFP_PAGESIZE 256
......
......@@ -112,10 +112,10 @@ MODULE_PARM_DESC(desct_intr, "Number of SDMA descriptor before interrupt");
| SD(ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK))
/* sdma_sendctrl operations */
#define SDMA_SENDCTRL_OP_ENABLE (1U << 0)
#define SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
#define SDMA_SENDCTRL_OP_HALT (1U << 2)
#define SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
#define SDMA_SENDCTRL_OP_ENABLE BIT(0)
#define SDMA_SENDCTRL_OP_INTENABLE BIT(1)
#define SDMA_SENDCTRL_OP_HALT BIT(2)
#define SDMA_SENDCTRL_OP_CLEANUP BIT(3)
/* handle long defines */
#define SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \
......
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