Commit 42594600 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/mmu: namespace + nvidia gpu names (no binary change)



The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent d7e5fcd2
......@@ -240,5 +240,6 @@
#define nvc0_pte_storage_type_map gf100_pte_storage_type_map
#define nouveau_fuse nvkm_fuse
#define nouveau_mc nvkm_mc
#define nouveau_mmu nvkm_mmu
#endif
#ifndef __NVKM_CE_H__
#define __NVKM_CE_H__
#include <core/engine.h>
void nva3_ce_intr(struct nouveau_subdev *);
......
/*
* Copyright 2010 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#ifndef __NOUVEAU_MMU_H__
#define __NOUVEAU_MMU_H__
#include <core/object.h>
#ifndef __NVKM_MMU_H__
#define __NVKM_MMU_H__
#include <core/subdev.h>
#include <core/device.h>
#include <core/mm.h>
struct nvkm_device;
struct nvkm_mem;
struct nouveau_vm_pgt {
struct nouveau_gpuobj *obj[2];
struct nvkm_vm_pgt {
struct nvkm_gpuobj *obj[2];
u32 refcount[2];
};
struct nouveau_vm_pgd {
struct nvkm_vm_pgd {
struct list_head head;
struct nouveau_gpuobj *obj;
struct nvkm_gpuobj *obj;
};
struct nouveau_gpuobj;
struct nouveau_mem;
struct nouveau_vma {
struct nvkm_vma {
struct list_head head;
int refcount;
struct nouveau_vm *vm;
struct nouveau_mm_node *node;
struct nvkm_vm *vm;
struct nvkm_mm_node *node;
u64 offset;
u32 access;
};
struct nouveau_vm {
struct nouveau_mmu *mmu;
struct nouveau_mm mm;
struct nvkm_vm {
struct nvkm_mmu *mmu;
struct nvkm_mm mm;
struct kref refcount;
struct list_head pgd_list;
atomic_t engref[NVDEV_SUBDEV_NR];
struct nouveau_vm_pgt *pgt;
struct nvkm_vm_pgt *pgt;
u32 fpde;
u32 lpde;
};
struct nouveau_mmu {
struct nouveau_subdev base;
struct nvkm_mmu {
struct nvkm_subdev base;
u64 limit;
u8 dma_bits;
......@@ -74,62 +46,59 @@ struct nouveau_mmu {
u8 spg_shift;
u8 lpg_shift;
int (*create)(struct nouveau_mmu *, u64 offset, u64 length,
u64 mm_offset, struct nouveau_vm **);
int (*create)(struct nvkm_mmu *, u64 offset, u64 length,
u64 mm_offset, struct nvkm_vm **);
void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
struct nouveau_gpuobj *pgt[2]);
void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *,
struct nouveau_mem *, u32 pte, u32 cnt,
void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde,
struct nvkm_gpuobj *pgt[2]);
void (*map)(struct nvkm_vma *, struct nvkm_gpuobj *,
struct nvkm_mem *, u32 pte, u32 cnt,
u64 phys, u64 delta);
void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *,
struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);
void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt);
void (*flush)(struct nouveau_vm *);
void (*map_sg)(struct nvkm_vma *, struct nvkm_gpuobj *,
struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *);
void (*unmap)(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt);
void (*flush)(struct nvkm_vm *);
};
static inline struct nouveau_mmu *
nouveau_mmu(void *obj)
static inline struct nvkm_mmu *
nvkm_mmu(void *obj)
{
return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU);
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU);
}
#define nouveau_mmu_create(p,e,o,i,f,d) \
nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d))
#define nouveau_mmu_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
#define nouveau_mmu_init(p) \
nouveau_subdev_init(&(p)->base)
#define nouveau_mmu_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s))
#define _nouveau_mmu_dtor _nouveau_subdev_dtor
#define _nouveau_mmu_init _nouveau_subdev_init
#define _nouveau_mmu_fini _nouveau_subdev_fini
extern struct nouveau_oclass nv04_mmu_oclass;
extern struct nouveau_oclass nv41_mmu_oclass;
extern struct nouveau_oclass nv44_mmu_oclass;
extern struct nouveau_oclass nv50_mmu_oclass;
extern struct nouveau_oclass nvc0_mmu_oclass;
int nv04_vm_create(struct nouveau_mmu *, u64, u64, u64,
struct nouveau_vm **);
void nv04_mmu_dtor(struct nouveau_object *);
/* nouveau_vm.c */
int nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length,
u64 mm_offset, u32 block, struct nouveau_vm **);
int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length,
u64 mm_offset, struct nouveau_vm **);
int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **,
struct nouveau_gpuobj *pgd);
int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift,
u32 access, struct nouveau_vma *);
void nouveau_vm_put(struct nouveau_vma *);
void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *);
void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *);
void nouveau_vm_unmap(struct nouveau_vma *);
void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
#define nvkm_mmu_create(p,e,o,i,f,d) \
nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d))
#define nvkm_mmu_destroy(p) \
nvkm_subdev_destroy(&(p)->base)
#define nvkm_mmu_init(p) \
nvkm_subdev_init(&(p)->base)
#define nvkm_mmu_fini(p,s) \
nvkm_subdev_fini(&(p)->base, (s))
#define _nvkm_mmu_dtor _nvkm_subdev_dtor
#define _nvkm_mmu_init _nvkm_subdev_init
#define _nvkm_mmu_fini _nvkm_subdev_fini
extern struct nvkm_oclass nv04_mmu_oclass;
extern struct nvkm_oclass nv41_mmu_oclass;
extern struct nvkm_oclass nv44_mmu_oclass;
extern struct nvkm_oclass nv50_mmu_oclass;
extern struct nvkm_oclass gf100_mmu_oclass;
int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64,
struct nvkm_vm **);
void nv04_mmu_dtor(struct nvkm_object *);
int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
u32 block, struct nvkm_vm **);
int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset,
struct nvkm_vm **);
int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd);
int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access,
struct nvkm_vma *);
void nvkm_vm_put(struct nvkm_vma *);
void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *);
void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *);
void nvkm_vm_unmap(struct nvkm_vma *);
void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length);
#endif
......@@ -22,6 +22,7 @@
* Authors: Ben Skeggs
*/
#include <core/engctx.h>
#include <core/engine.h>
#include <core/client.h>
static inline int
......
......@@ -22,6 +22,7 @@
* Authors: Ben Skeggs
*/
#include <core/gpuobj.h>
#include <core/engine.h>
#include <subdev/instmem.h>
#include <subdev/bar.h>
......
......@@ -30,6 +30,7 @@
#include <subdev/mmu.h>
#include <core/client.h>
#include <core/device.h>
#include <core/enum.h>
......
......@@ -76,7 +76,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
......@@ -120,7 +120,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
#if 0
......
......@@ -76,7 +76,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -109,7 +109,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -142,7 +142,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -174,7 +174,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -207,7 +207,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -239,7 +239,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -271,7 +271,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -336,7 +336,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
......
......@@ -76,7 +76,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -110,7 +110,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -144,7 +144,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -172,7 +172,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
......@@ -200,7 +200,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -234,7 +234,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -268,7 +268,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......@@ -301,7 +301,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
......
......@@ -24,6 +24,7 @@
#include <core/object.h>
#include <core/client.h>
#include <core/device.h>
#include <nvif/unpack.h>
#include <nvif/class.h>
......
......@@ -23,6 +23,7 @@
*/
#include <core/client.h>
#include <core/device.h>
#include <nvif/unpack.h>
#include <nvif/class.h>
#include <core/engctx.h>
......
......@@ -20,6 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <core/device.h>
#include <core/gpuobj.h>
#define CP_FLAG_CLEAR 0
......
......@@ -23,6 +23,7 @@
*/
#include <core/client.h>
#include <core/device.h>
#include <core/os.h>
#include <core/handle.h>
......
......@@ -20,6 +20,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <engine/xtensa.h>
#include <core/device.h>
#include <core/engctx.h>
......
......@@ -23,6 +23,7 @@
*/
#include "priv.h"
#include <core/device.h>
#include <core/gpuobj.h>
#include <subdev/fb.h>
#include <subdev/mmu.h>
......
......@@ -23,6 +23,8 @@
*/
#include "gf100.h"
#include <core/device.h>
extern const u8 gf100_pte_storage_type_map[256];
bool
......
......@@ -25,6 +25,8 @@
*/
#include "nv04.h"
#include <core/device.h>
void
nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
u32 flags, struct nvkm_fb_tile *tile)
......
......@@ -24,6 +24,7 @@
#include "nv50.h"
#include <core/client.h>
#include <core/device.h>
#include <core/engctx.h>
#include <core/enum.h>
......
......@@ -21,6 +21,8 @@
*/
#include "priv.h"
#include <core/device.h>
struct gk20a_mem {
struct nvkm_mem base;
void *cpuaddr;
......
......@@ -23,6 +23,8 @@
*/
#include "priv.h"
#include <core/device.h>
static int
nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
......
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