Commit 622ec01a authored by Ian Abbott's avatar Ian Abbott Committed by Greg Kroah-Hartman
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staging: comedi: s626: distinguish counter src from encoder mode



The macros `S626_CLKSRC_COUNTER`, `S626_CLKSRC_TIMER` and
`S626_CLKSRC_EXTENDER` are used logically to set the operating mode of
an encoder channel.  `S626_CLKSRC_COUNTER` (0) is also used as a 2-bit
physical value to set the counter source of an encoder channel to
"encoder".

Rename the macros to `S626_ENCMODE_COUNTER`, `S626_ENCMODE_TIMER` and
`S626_ENCMODE_EXTENDER` and rename some other macros and (unused)
functions relating to the encoder mode for consistency.

Define new macros to specify the physical counter source values for the
'CRA' register and rename the corresponding bitshift and mask macros
accordingly.  The physical values for the counter source are:

  S626_CNTSRC_ENCODER = 0      // encoder
  S626_CNTSRC_DIGIN = 1        // digital inputs
  S626_CNTSRC_SYSCLK = 2       // system clock up
  S626_CNTSRC_SYSCLK_DOWN = 3  // system clock down

Also use the `S626_CNTSRC_SYSCLK` value as a bitmask (bit 1) to indicate
either of the system clock values, with the direction (bit 0) indicated
separately in this case.
Signed-off-by: default avatarIan Abbott <abbotti@mev.co.uk>
Reviewed-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 72938088
......@@ -720,19 +720,19 @@ static uint16_t s626_get_mode_a(struct comedi_device *dev,
S626_STDMSK_CLKENAB); /* ClkEnab = ClkEnabA. */
/* Adjust mode-dependent parameters. */
if (cra & (2 << S626_CRABIT_CLKSRC_A)) {
/* Timer mode (ClkSrcA<1> == 1): */
if (cra & (S626_CNTSRC_SYSCLK << S626_CRABIT_CNTSRC_A)) {
/* Timer mode (CntSrcA<1> == 1): */
/* Indicate Timer mode. */
setup |= S626_CLKSRC_TIMER << S626_STDBIT_CLKSRC;
/* Set ClkPol to indicate count direction (ClkSrcA<0>). */
setup |= (cra << (S626_STDBIT_CLKPOL - S626_CRABIT_CLKSRC_A)) &
setup |= S626_ENCMODE_TIMER << S626_STDBIT_ENCMODE;
/* Set ClkPol to indicate count direction (CntSrcA<0>). */
setup |= (cra << (S626_STDBIT_CLKPOL - S626_CRABIT_CNTSRC_A)) &
S626_STDMSK_CLKPOL;
/* ClkMult must be 1x in Timer mode. */
setup |= S626_MULT_X1 << S626_STDBIT_CLKMULT;
} else {
/* Counter mode (ClkSrcA<1> == 0): */
/* Counter mode (CntSrcA<1> == 0): */
/* Indicate Counter mode. */
setup |= S626_CLKSRC_COUNTER << S626_STDBIT_CLKSRC;
setup |= S626_ENCMODE_COUNTER << S626_STDBIT_ENCMODE;
/* Pass through ClkPol. */
setup |= (cra >> (S626_CRABIT_CLKPOL_A - S626_STDBIT_CLKPOL)) &
S626_STDMSK_CLKPOL;
......@@ -783,25 +783,25 @@ static uint16_t s626_get_mode_b(struct comedi_device *dev,
(S626_MULT_X0 << S626_CRBBIT_CLKMULT_B)) {
/* Extender mode (ClkMultB == S626_MULT_X0): */
/* Indicate Extender mode. */
setup |= S626_CLKSRC_EXTENDER << S626_STDBIT_CLKSRC;
setup |= S626_ENCMODE_EXTENDER << S626_STDBIT_ENCMODE;
/* Indicate multiplier is 1x. */
setup |= S626_MULT_X1 << S626_STDBIT_CLKMULT;
/* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
setup |= (cra >> (S626_CRABIT_CLKSRC_B - S626_STDBIT_CLKPOL)) &
/* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
setup |= (cra >> (S626_CRABIT_CNTSRC_B - S626_STDBIT_CLKPOL)) &
S626_STDMSK_CLKPOL;
} else if (cra & (2 << S626_CRABIT_CLKSRC_B)) {
/* Timer mode (ClkSrcB<1> == 1): */
} else if (cra & (S626_CNTSRC_SYSCLK << S626_CRABIT_CNTSRC_B)) {
/* Timer mode (CntSrcB<1> == 1): */
/* Indicate Timer mode. */
setup |= S626_CLKSRC_TIMER << S626_STDBIT_CLKSRC;
setup |= S626_ENCMODE_TIMER << S626_STDBIT_ENCMODE;
/* Indicate multiplier is 1x. */
setup |= S626_MULT_X1 << S626_STDBIT_CLKMULT;
/* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
setup |= (cra >> (S626_CRABIT_CLKSRC_B - S626_STDBIT_CLKPOL)) &
/* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
setup |= (cra >> (S626_CRABIT_CNTSRC_B - S626_STDBIT_CLKPOL)) &
S626_STDMSK_CLKPOL;
} else {
/* If Counter mode (ClkSrcB<1> == 0): */
/* If Counter mode (CntSrcB<1> == 0): */
/* Indicate Counter mode. */
setup |= S626_CLKSRC_COUNTER << S626_STDBIT_CLKSRC;
setup |= S626_ENCMODE_COUNTER << S626_STDBIT_ENCMODE;
/* Clock multiplier is passed through. */
setup |= (crb >> (S626_CRBBIT_CLKMULT_B -
S626_STDBIT_CLKMULT)) & S626_STDMSK_CLKMULT;
......@@ -847,16 +847,16 @@ static void s626_set_mode_a(struct comedi_device *dev,
(S626_STDBIT_INTSRC - S626_CRABIT_INTSRC_A);
/* Populate all mode-dependent attributes of CRA & CRB images. */
switch ((setup & S626_STDMSK_CLKSRC) >> S626_STDBIT_CLKSRC) {
case S626_CLKSRC_EXTENDER: /* Extender Mode: */
switch ((setup & S626_STDMSK_ENCMODE) >> S626_STDBIT_ENCMODE) {
case S626_ENCMODE_EXTENDER: /* Extender Mode: */
/* Force to Timer mode (Extender valid only for B counters). */
/* Fall through to case S626_CLKSRC_TIMER: */
case S626_CLKSRC_TIMER: /* Timer Mode: */
/* ClkSrcA<1> selects system clock */
cra |= 2 << S626_CRABIT_CLKSRC_A;
/* Count direction (ClkSrcA<0>) obtained from ClkPol. */
/* Fall through to case S626_ENCMODE_TIMER: */
case S626_ENCMODE_TIMER: /* Timer Mode: */
/* CntSrcA<1> selects system clock */
cra |= S626_CNTSRC_SYSCLK << S626_CRABIT_CNTSRC_A;
/* Count direction (CntSrcA<0>) obtained from ClkPol. */
cra |= (setup & S626_STDMSK_CLKPOL) >>
(S626_STDBIT_CLKPOL - S626_CRABIT_CLKSRC_A);
(S626_STDBIT_CLKPOL - S626_CRABIT_CNTSRC_A);
/* ClkPolA behaves as always-on clock enable. */
cra |= 1 << S626_CRABIT_CLKPOL_A;
/* ClkMult must be 1x. */
......@@ -864,7 +864,7 @@ static void s626_set_mode_a(struct comedi_device *dev,
break;
default: /* Counter Mode: */
/* Select ENC_C and ENC_D as clock/direction inputs. */
cra |= S626_CLKSRC_COUNTER << S626_CRABIT_CLKSRC_A;
cra |= S626_CNTSRC_ENCODER << S626_CRABIT_CNTSRC_A;
/* Clock polarity is passed through. */
cra |= (setup & S626_STDMSK_CLKPOL) <<
(S626_CRABIT_CLKPOL_A - S626_STDBIT_CLKPOL);
......@@ -898,7 +898,7 @@ static void s626_set_mode_a(struct comedi_device *dev,
* new counter operating mode.
*/
s626_debi_replace(dev, k->my_cra,
S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CLKSRC_B, cra);
S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
s626_debi_replace(dev, k->my_crb,
~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
}
......@@ -931,24 +931,24 @@ static void s626_set_mode_b(struct comedi_device *dev,
(S626_STDBIT_INTSRC - S626_CRBBIT_INTSRC_B);
/* Populate all mode-dependent attributes of CRA & CRB images. */
switch ((setup & S626_STDMSK_CLKSRC) >> S626_STDBIT_CLKSRC) {
case S626_CLKSRC_TIMER: /* Timer Mode: */
/* ClkSrcB<1> selects system clock */
cra |= 2 << S626_CRABIT_CLKSRC_B;
/* with direction (ClkSrcB<0>) obtained from ClkPol. */
switch ((setup & S626_STDMSK_ENCMODE) >> S626_STDBIT_ENCMODE) {
case S626_ENCMODE_TIMER: /* Timer Mode: */
/* CntSrcB<1> selects system clock */
cra |= S626_CNTSRC_SYSCLK << S626_CRABIT_CNTSRC_B;
/* with direction (CntSrcB<0>) obtained from ClkPol. */
cra |= (setup & S626_STDMSK_CLKPOL) <<
(S626_CRABIT_CLKSRC_B - S626_STDBIT_CLKPOL);
(S626_CRABIT_CNTSRC_B - S626_STDBIT_CLKPOL);
/* ClkPolB behaves as always-on clock enable. */
crb |= 1 << S626_CRBBIT_CLKPOL_B;
/* ClkMultB must be 1x. */
crb |= S626_MULT_X1 << S626_CRBBIT_CLKMULT_B;
break;
case S626_CLKSRC_EXTENDER: /* Extender Mode: */
/* ClkSrcB source is OverflowA (same as "timer") */
cra |= 2 << S626_CRABIT_CLKSRC_B;
case S626_ENCMODE_EXTENDER: /* Extender Mode: */
/* CntSrcB source is OverflowA (same as "timer") */
cra |= S626_CNTSRC_SYSCLK << S626_CRABIT_CNTSRC_B;
/* with direction obtained from ClkPol. */
cra |= (setup & S626_STDMSK_CLKPOL) <<
(S626_CRABIT_CLKSRC_B - S626_STDBIT_CLKPOL);
(S626_CRABIT_CNTSRC_B - S626_STDBIT_CLKPOL);
/* ClkPolB controls IndexB -- always set to active. */
crb |= 1 << S626_CRBBIT_CLKPOL_B;
/* ClkMultB selects OverflowA as the clock source. */
......@@ -956,7 +956,7 @@ static void s626_set_mode_b(struct comedi_device *dev,
break;
default: /* Counter Mode: */
/* Select ENC_C and ENC_D as clock/direction inputs. */
cra |= S626_CLKSRC_COUNTER << S626_CRABIT_CLKSRC_B;
cra |= S626_CNTSRC_ENCODER << S626_CRABIT_CNTSRC_B;
/* ClkPol is passed through. */
crb |= (setup & S626_STDMSK_CLKPOL) >>
(S626_STDBIT_CLKPOL - S626_CRBBIT_CLKPOL_B);
......@@ -990,7 +990,7 @@ static void s626_set_mode_b(struct comedi_device *dev,
* new counter operating mode.
*/
s626_debi_replace(dev, k->my_cra,
~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CLKSRC_B), cra);
~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
s626_debi_replace(dev, k->my_crb,
S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
}
......@@ -1162,19 +1162,19 @@ static uint16_t s626_get_clk_pol(struct comedi_device *dev,
}
/*
* Return/set the clock source.
* Return/set the encoder mode.
*/
static void s626_set_clk_src(struct comedi_device *dev,
const struct s626_enc_info *k, uint16_t value)
static void s626_set_enc_mode(struct comedi_device *dev,
const struct s626_enc_info *k, uint16_t value)
{
k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_CLKSRC) |
(value << S626_STDBIT_CLKSRC)), false);
k->set_mode(dev, k, ((k->get_mode(dev, k) & ~S626_STDMSK_ENCMODE) |
(value << S626_STDBIT_ENCMODE)), false);
}
static uint16_t s626_get_clk_src(struct comedi_device *dev,
const struct s626_enc_info *k)
static uint16_t s626_get_enc_mode(struct comedi_device *dev,
const struct s626_enc_info *k)
{
return (k->get_mode(dev, k) >> S626_STDBIT_CLKSRC) & 3;
return (k->get_mode(dev, k) >> S626_STDBIT_ENCMODE) & 3;
}
/*
......@@ -2035,7 +2035,7 @@ static void s626_timer_load(struct comedi_device *dev,
/* Disable hardware index. */
(S626_INDXSRC_SOFT << S626_BF_INDXSRC) |
/* Operating mode is Timer. */
(S626_CLKSRC_TIMER << S626_BF_CLKSRC) |
(S626_ENCMODE_TIMER << S626_BF_ENCMODE) |
/* Count direction is Down. */
(S626_CNTDIR_DOWN << S626_BF_CLKPOL) |
/* Clock multiplier is 1x. */
......@@ -2427,7 +2427,7 @@ static int s626_enc_insn_config(struct comedi_device *dev,
/* Disable hardware index. */
(S626_INDXSRC_SOFT << S626_BF_INDXSRC) |
/* Operating mode is Counter. */
(S626_CLKSRC_COUNTER << S626_BF_CLKSRC) |
(S626_ENCMODE_COUNTER << S626_BF_ENCMODE) |
/* Active high clock. */
(S626_CLKPOL_POS << S626_BF_CLKPOL) |
/* Clock multiplier is 1x. */
......@@ -2523,7 +2523,7 @@ static void s626_counters_init(struct comedi_device *dev)
/* Disable hardware index. */
(S626_INDXSRC_SOFT << S626_BF_INDXSRC) |
/* Operating mode is counter. */
(S626_CLKSRC_COUNTER << S626_BF_CLKSRC) |
(S626_ENCMODE_COUNTER << S626_BF_ENCMODE) |
/* Active high clock. */
(S626_CLKPOL_POS << S626_BF_CLKPOL) |
/* Clock multiplier is 1x. */
......
......@@ -469,10 +469,16 @@
#define S626_INDXPOL_POS 0 /* Index input is active high. */
#define S626_INDXPOL_NEG 1 /* Index input is active low. */
/* ClkSrc values: */
#define S626_CLKSRC_COUNTER 0 /* Counter mode. */
#define S626_CLKSRC_TIMER 2 /* Timer mode. */
#define S626_CLKSRC_EXTENDER 3 /* Extender mode. */
/* Logical encoder mode values: */
#define S626_ENCMODE_COUNTER 0 /* Counter mode. */
#define S626_ENCMODE_TIMER 2 /* Timer mode. */
#define S626_ENCMODE_EXTENDER 3 /* Extender mode. */
/* Physical CntSrc values (for Counter A source and Counter B source): */
#define S626_CNTSRC_ENCODER 0 /* Encoder */
#define S626_CNTSRC_DIGIN 1 /* Digital inputs */
#define S626_CNTSRC_SYSCLK 2 /* System clock up */
#define S626_CNTSRC_SYSCLK_DOWN 3 /* System clock down */
/* ClkPol values: */
#define S626_CLKPOL_POS 0 /* Counter/Extender clock is
......@@ -495,7 +501,7 @@
#define S626_BF_LOADSRC 9 /* Preload trigger. */
#define S626_BF_INDXSRC 7 /* Index source. */
#define S626_BF_INDXPOL 6 /* Index polarity. */
#define S626_BF_CLKSRC 4 /* Clock source. */
#define S626_BF_ENCMODE 4 /* Encoder mode. */
#define S626_BF_CLKPOL 3 /* Clock polarity/count direction. */
#define S626_BF_CLKMULT 1 /* Clock multiplier. */
#define S626_BF_CLKENAB 0 /* Clock enable. */
......@@ -528,14 +534,14 @@
/* Bit field positions in CRA: */
#define S626_CRABIT_INDXSRC_B 14 /* B index source. */
#define S626_CRABIT_CLKSRC_B 12 /* B clock source. */
#define S626_CRABIT_CNTSRC_B 12 /* B counter source. */
#define S626_CRABIT_INDXPOL_A 11 /* A index polarity. */
#define S626_CRABIT_LOADSRC_A 9 /* A preload trigger. */
#define S626_CRABIT_CLKMULT_A 7 /* A clock multiplier. */
#define S626_CRABIT_INTSRC_A 5 /* A interrupt source. */
#define S626_CRABIT_CLKPOL_A 4 /* A clock polarity. */
#define S626_CRABIT_INDXSRC_A 2 /* A index source. */
#define S626_CRABIT_CLKSRC_A 0 /* A clock source. */
#define S626_CRABIT_CNTSRC_A 0 /* A counter source. */
/* Bit field positions in CRB: */
#define S626_CRBBIT_INTRESETCMD 15 /* Interrupt reset command. */
......@@ -553,14 +559,14 @@
/* Bit field masks for CRA and CRB. */
#define S626_CRAMSK_INDXSRC_B (3 << S626_CRABIT_INDXSRC_B)
#define S626_CRAMSK_CLKSRC_B (3 << S626_CRABIT_CLKSRC_B)
#define S626_CRAMSK_CNTSRC_B (3 << S626_CRABIT_CNTSRC_B)
#define S626_CRAMSK_INDXPOL_A (1 << S626_CRABIT_INDXPOL_A)
#define S626_CRAMSK_LOADSRC_A (3 << S626_CRABIT_LOADSRC_A)
#define S626_CRAMSK_CLKMULT_A (3 << S626_CRABIT_CLKMULT_A)
#define S626_CRAMSK_INTSRC_A (3 << S626_CRABIT_INTSRC_A)
#define S626_CRAMSK_CLKPOL_A (3 << S626_CRABIT_CLKPOL_A)
#define S626_CRAMSK_INDXSRC_A (3 << S626_CRABIT_INDXSRC_A)
#define S626_CRAMSK_CLKSRC_A (3 << S626_CRABIT_CLKSRC_A)
#define S626_CRAMSK_CNTSRC_A (3 << S626_CRABIT_CNTSRC_A)
#define S626_CRBMSK_INTRESETCMD (1 << S626_CRBBIT_INTRESETCMD)
#define S626_CRBMSK_INTRESET_B (1 << S626_CRBBIT_INTRESET_B)
......@@ -586,7 +592,7 @@
#define S626_STDBIT_LOADSRC 9
#define S626_STDBIT_INDXSRC 7
#define S626_STDBIT_INDXPOL 6
#define S626_STDBIT_CLKSRC 4
#define S626_STDBIT_ENCMODE 4
#define S626_STDBIT_CLKPOL 3
#define S626_STDBIT_CLKMULT 1
#define S626_STDBIT_CLKENAB 0
......@@ -598,7 +604,7 @@
#define S626_STDMSK_LOADSRC (3 << S626_STDBIT_LOADSRC)
#define S626_STDMSK_INDXSRC (1 << S626_STDBIT_INDXSRC)
#define S626_STDMSK_INDXPOL (1 << S626_STDBIT_INDXPOL)
#define S626_STDMSK_CLKSRC (3 << S626_STDBIT_CLKSRC)
#define S626_STDMSK_ENCMODE (3 << S626_STDBIT_ENCMODE)
#define S626_STDMSK_CLKPOL (1 << S626_STDBIT_CLKPOL)
#define S626_STDMSK_CLKMULT (3 << S626_STDBIT_CLKMULT)
#define S626_STDMSK_CLKENAB (1 << S626_STDBIT_CLKENAB)
......
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