Commit 6c7b03e1 authored by Boris Brezillon's avatar Boris Brezillon
Browse files

clk: at91: pll: fix input range validity check



The PLL impose a certain input range to work correctly, but it appears that
this input range does not apply on the input clock (or parent clock) but
on the input clock after it has passed the PLL divisor.
Fix the implementation accordingly.

Cc: <stable@vger.kernel.org> # v3.14+
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: default avatarJonas Andersson <jonas@microbit.se>
parent 03bc10ab
......@@ -173,8 +173,7 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
int i = 0;
/* Check if parent_rate is a valid input rate */
if (parent_rate < characteristics->input.min ||
parent_rate > characteristics->input.max)
if (parent_rate < characteristics->input.min)
return -ERANGE;
/*
......@@ -187,6 +186,15 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
if (!mindiv)
mindiv = 1;
if (parent_rate > characteristics->input.max) {
tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
if (tmpdiv > PLL_DIV_MAX)
return -ERANGE;
if (tmpdiv > mindiv)
mindiv = tmpdiv;
}
/*
* Calculate the maximum divider which is limited by PLL register
* layout (limited by the MUL or DIV field size).
......
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