Commit 7ebdf956 authored by Gavin Shan's avatar Gavin Shan Committed by Benjamin Herrenschmidt
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powerpc/powernv: PE list based on creation order



The resource (I/O and MMIO) will be assigned on basis of PE from
top to bottom so that we can implement the trick here: the resource
that has been assigned to parent PE could be taken by child PE if
necessary.

The current implementation already has PE list per PHB basis, but
the list doesn't meet our requirment: tracing PE based on their
cration time from top to bottom. So the patch does rename for the
DMA based PE list and introduces the list to trace the PEs sequentially
based on their creation time.
Signed-off-by: default avatarGavin Shan <shangw@linux.vnet.ibm.com>
Reviewed-by: default avatarRam Pai <linuxram@us.ibm.com>
Reviewed-by: default avatarRichard Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent fb446ad0
......@@ -656,13 +656,13 @@ static void __devinit pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
{
struct pnv_ioda_pe *lpe;
list_for_each_entry(lpe, &phb->ioda.pe_list, link) {
list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
if (lpe->dma_weight < pe->dma_weight) {
list_add_tail(&pe->link, &lpe->link);
list_add_tail(&pe->dma_link, &lpe->dma_link);
return;
}
}
list_add_tail(&pe->link, &phb->ioda.pe_list);
list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
}
static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
......@@ -828,6 +828,9 @@ static void __devinit pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
/* Associate it with all child devices */
pnv_ioda_setup_same_PE(bus, pe);
/* Put PE to the list */
list_add_tail(&pe->list, &phb->ioda.pe_list);
/* Account for one DMA PE if at least one DMA capable device exist
* below the bridge
*/
......@@ -1011,7 +1014,7 @@ static void __devinit pnv_ioda_setup_dma(struct pnv_phb *phb)
remaining = phb->ioda.tce32_count;
tw = phb->ioda.dma_weight;
base = 0;
list_for_each_entry(pe, &phb->ioda.pe_list, link) {
list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
if (!pe->dma_weight)
continue;
if (!remaining) {
......@@ -1305,6 +1308,7 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
phb->ioda.pe_array = aux + pemap_off;
set_bit(0, phb->ioda.pe_alloc);
INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
INIT_LIST_HEAD(&phb->ioda.pe_list);
/* Calculate how many 32-bit TCE segments we have */
......
......@@ -17,9 +17,14 @@ enum pnv_phb_model {
};
#define PNV_PCI_DIAG_BUF_SIZE 4096
#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
/* Data associated with a PE, including IOMMU tracking etc.. */
struct pnv_ioda_pe {
unsigned long flags;
/* A PE can be associated with a single device or an
* entire bus (& children). In the former case, pdev
* is populated, in the later case, pbus is.
......@@ -40,11 +45,6 @@ struct pnv_ioda_pe {
*/
unsigned int dma_weight;
/* This is a PCI-E -> PCI-X bridge, this points to the
* corresponding bus PE
*/
struct pnv_ioda_pe *bus_pe;
/* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
int tce32_seg;
int tce32_segcount;
......@@ -59,7 +59,8 @@ struct pnv_ioda_pe {
int mve_number;
/* Link in list of PE#s */
struct list_head link;
struct list_head dma_link;
struct list_head list;
};
struct pnv_phb {
......@@ -107,6 +108,11 @@ struct pnv_phb {
unsigned int *io_segmap;
struct pnv_ioda_pe *pe_array;
/* Sorted list of used PE's based
* on the sequence of creation
*/
struct list_head pe_list;
/* Reverse map of PEs, will have to extend if
* we are to support more than 256 PEs, indexed
* bus { bus, devfn }
......@@ -125,7 +131,7 @@ struct pnv_phb {
/* Sorted list of used PE's, sorted at
* boot for resource allocation purposes
*/
struct list_head pe_list;
struct list_head pe_dma_list;
} ioda;
};
......
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