Commit 98488db9 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

powerpc: Use proper accessors for IRQ_* flags



Use the proper accessors instead of open access to irq_desc.
Converted with coccinelle.
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 68f20f43
......@@ -618,7 +618,7 @@ struct irq_host *irq_alloc_host(struct device_node *of_node,
smp_wmb();
/* Clear norequest flags */
irq_to_desc(i)->status &= ~IRQ_NOREQUEST;
irq_clear_status_flags(i, IRQ_NOREQUEST);
/* Legacy flags are left to default at this point,
* one can then use irq_create_mapping() to
......
......@@ -35,13 +35,13 @@ void machine_kexec_mask_interrupts(void) {
if (!chip)
continue;
if (chip->irq_eoi && desc->status & IRQ_INPROGRESS)
if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data))
chip->irq_eoi(&desc->irq_data);
if (chip->irq_mask)
chip->irq_mask(&desc->irq_data);
if (chip->irq_disable && !(desc->status & IRQ_DISABLED))
if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data))
chip->irq_disable(&desc->irq_data);
}
}
......
......@@ -132,7 +132,7 @@ static int
cpld_pic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq);
return 0;
}
......
......@@ -107,7 +107,7 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
/* Processing done; can reenable the cascade now */
raw_spin_lock(&desc->lock);
chip->irq_ack(&desc->irq_data);
if (!(desc->status & IRQ_DISABLED))
if (!irqd_irq_disabled(&desc->irq_data))
chip->irq_unmask(&desc->irq_data);
raw_spin_unlock(&desc->lock);
}
......
......@@ -106,7 +106,7 @@ static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_data(virq, h->host_data);
set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
return 0;
......
......@@ -245,7 +245,7 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hwirq)
{
/* All interrupts are LEVEL sensitive */
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip,
handle_fasteoi_irq);
......
......@@ -163,7 +163,7 @@ static int gef_pic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hwirq)
{
/* All interrupts are LEVEL sensitive */
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
return 0;
......
......@@ -136,14 +136,13 @@ static void beatic_pic_host_unmap(struct irq_host *h, unsigned int virq)
static int beatic_pic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
struct irq_desc *desc = irq_to_desc(virq);
int64_t err;
err = beat_construct_and_connect_irq_plug(virq, hw);
if (err < 0)
return -EIO;
desc->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq);
return 0;
}
......
......@@ -102,7 +102,7 @@ static int flipper_pic_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hwirq)
{
set_irq_chip_data(virq, h->host_data);
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
return 0;
}
......
......@@ -95,7 +95,7 @@ static int hlwd_pic_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hwirq)
{
set_irq_chip_data(virq, h->host_data);
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
return 0;
}
......@@ -145,7 +145,7 @@ static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
raw_spin_lock(&desc->lock);
chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
chip->irq_unmask(&desc->irq_data);
raw_spin_unlock(&desc->lock);
}
......
......@@ -289,7 +289,6 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
struct irq_desc *desc = irq_to_desc(virq);
int level;
if (hw >= max_irqs)
......@@ -300,7 +299,7 @@ static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
*/
level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
if (level)
desc->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &pmac_pic, level ?
handle_level_irq : handle_edge_irq);
return 0;
......
......@@ -470,7 +470,7 @@ static int xics_host_map(struct irq_host *h, unsigned int virq,
/* Insert the interrupt mapping into the radix tree for fast lookup */
irq_radix_revmap_insert(xics_host, virq, hw);
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
return 0;
}
......
......@@ -103,7 +103,7 @@ static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
{
pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
return 0;
}
......
......@@ -226,7 +226,7 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
{
pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
return 0;
}
......
......@@ -64,7 +64,7 @@ static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
struct fsl_msi *msi_data = h->host_data;
struct irq_chip *chip = &fsl_msi_chip;
irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
set_irq_chip_data(virq, msi_data);
set_irq_chip_and_handler(virq, chip, handle_edge_irq);
......
......@@ -175,12 +175,12 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq,
/* We block the internal cascade */
if (hw == 2)
irq_to_desc(virq)->status |= IRQ_NOREQUEST;
irq_set_status_flags(virq, IRQ_NOREQUEST);
/* We use the level handler only for now, we might want to
* be more cautious here but that works for now
*/
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq);
return 0;
}
......
......@@ -213,7 +213,7 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq,
{
int level1;
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
BUG_ON(level1 > MV64x60_LEVEL1_GPP);
......
......@@ -268,7 +268,7 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
chip = &qe_ic->hc_irq;
set_irq_chip_data(virq, qe_ic);
irq_to_desc(virq)->status |= IRQ_LEVEL;
irq_set_status_flags(virq, IRQ_LEVEL);
set_irq_chip_and_handler(virq, chip, handle_level_irq);
......
......@@ -391,7 +391,7 @@ static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
if ((virq >= 1) && (virq <= 4)){
irq = virq + IRQ_PCI_INTAD_BASE - 1;
irq_to_desc(irq)->status |= IRQ_LEVEL;
irq_set_status_flags(irq, IRQ_LEVEL);
set_irq_chip(irq, &tsi108_pci_irq);
}
return 0;
......
......@@ -244,9 +244,9 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
uic_irq_ret:
raw_spin_lock(&desc->lock);
if (desc->status & IRQ_LEVEL)
if (irqd_is_level_type(&desc->irq_data))
chip->irq_ack(&desc->irq_data);
if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
if (!(irq_is_disabled(&desc->irq_data) && chip->irq_unmask)
chip->irq_unmask(&desc->irq_data);
raw_spin_unlock(&desc->lock);
}
......
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