Commit c0cc5316 authored by David S. Miller's avatar David S. Miller
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net



Minor overlapping changes in the conflicts.

In the macsec case, the change of the default ID macro
name overlapped with the 64-bit netlink attribute alignment
fixes in net-next.
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 8c14586f f28f20da
......@@ -192,7 +192,6 @@ nodes to be present and contain the properties described below.
can be one of:
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,psci"
"arm,realview-smp"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15"
......
......@@ -8,15 +8,19 @@ Required properties:
of memory mapped region.
- clock-names: from common clock binding:
Required elements: "24m"
- rockchip,grf: phandle to the syscon managing the "general register files"
- #phy-cells : from the generic PHY bindings, must be 0;
Example:
edp_phy: edp-phy {
compatible = "rockchip,rk3288-dp-phy";
rockchip,grf = <&grf>;
clocks = <&cru SCLK_EDP_24M>;
clock-names = "24m";
#phy-cells = <0>;
grf: syscon@ff770000 {
compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
...
edp_phy: edp-phy {
compatible = "rockchip,rk3288-dp-phy";
clocks = <&cru SCLK_EDP_24M>;
clock-names = "24m";
#phy-cells = <0>;
};
};
......@@ -3,17 +3,23 @@ Rockchip EMMC PHY
Required properties:
- compatible: rockchip,rk3399-emmc-phy
- rockchip,grf : phandle to the syscon managing the "general
register files"
- #phy-cells: must be 0
- reg: PHY configure reg address offset in "general
- reg: PHY register address offset and length in "general
register files"
Example:
emmcphy: phy {
compatible = "rockchip,rk3399-emmc-phy";
rockchip,grf = <&grf>;
reg = <0xf780>;
#phy-cells = <0>;
grf: syscon@ff770000 {
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
...
emmcphy: phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x20>;
#phy-cells = <0>;
};
};
......@@ -173,6 +173,10 @@ A few EV_ABS codes have special meanings:
proximity of the device and while the value of the BTN_TOUCH code is 0. If
the input device may be used freely in three dimensions, consider ABS_Z
instead.
- BTN_TOOL_<name> should be set to 1 when the tool comes into detectable
proximity and set to 0 when the tool leaves detectable proximity.
BTN_TOOL_<name> signals the type of tool that is currently detected by the
hardware and is otherwise independent of ABS_DISTANCE and/or BTN_TOUCH.
* ABS_MT_<name>:
- Used to describe multitouch input events. Please see
......
......@@ -19,7 +19,7 @@ ffffff0000000000 - ffffff7fffffffff (=39 bits) %esp fixup stacks
ffffffef00000000 - ffffffff00000000 (=64 GB) EFI region mapping space
... unused hole ...
ffffffff80000000 - ffffffffa0000000 (=512 MB) kernel text mapping, from phys 0
ffffffffa0000000 - ffffffffff5fffff (=1525 MB) module mapping space
ffffffffa0000000 - ffffffffff5fffff (=1526 MB) module mapping space
ffffffffff600000 - ffffffffffdfffff (=8 MB) vsyscalls
ffffffffffe00000 - ffffffffffffffff (=2 MB) unused hole
......@@ -31,8 +31,8 @@ vmalloc space is lazily synchronized into the different PML4 pages of
the processes using the page fault handler, with init_level4_pgt as
reference.
Current X86-64 implementations only support 40 bits of address space,
but we support up to 46 bits. This expands into MBZ space in the page tables.
Current X86-64 implementations support up to 46 bits of address space (64 TB),
which is our current limit. This expands into MBZ space in the page tables.
We map EFI runtime services in the 'efi_pgd' PGD in a 64Gb large virtual
memory window (this size is arbitrary, it can be raised later if needed).
......
......@@ -11072,6 +11072,15 @@ S: Maintained
F: drivers/clk/ti/
F: include/linux/clk/ti.h
TI ETHERNET SWITCH DRIVER (CPSW)
M: Mugunthan V N <mugunthanvnm@ti.com>
R: Grygorii Strashko <grygorii.strashko@ti.com>
L: linux-omap@vger.kernel.org
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/ti/cpsw*
F: drivers/net/ethernet/ti/davinci*
TI FLASH MEDIA INTERFACE DRIVER
M: Alex Dubov <oakad@yahoo.com>
S: Maintained
......
VERSION = 4
PATCHLEVEL = 6
SUBLEVEL = 0
EXTRAVERSION = -rc4
EXTRAVERSION = -rc5
NAME = Blurry Fish Butt
# *DOCUMENTATION*
......@@ -1008,7 +1008,8 @@ prepare0: archprepare FORCE
prepare: prepare0 prepare-objtool
ifdef CONFIG_STACK_VALIDATION
has_libelf := $(shell echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf - &> /dev/null && echo 1 || echo 0)
has_libelf := $(call try-run,\
echo "int main() {}" | $(HOSTCC) -xc -o /dev/null -lelf -,1,0)
ifeq ($(has_libelf),1)
objtool_target := tools/objtool FORCE
else
......
......@@ -860,7 +860,7 @@
ti,no-idle-on-init;
reg = <0x50000000 0x2000>;
interrupts = <100>;
dmas = <&edma 52>;
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
......
......@@ -884,7 +884,7 @@
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
dmas = <&edma 52>;
dmas = <&edma 52 0>;
dma-names = "rxtx";
clocks = <&l3s_gclk>;
clock-names = "fck";
......
......@@ -99,13 +99,6 @@
#cooling-cells = <2>;
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&extcon_usb1_pins>;
};
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
......@@ -349,12 +342,6 @@
>;
};
extcon_usb1_pins: extcon_usb1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */
......@@ -706,10 +693,6 @@
pinctrl-0 = <&usb1_pins>;
};
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
......
......@@ -4,6 +4,157 @@
* published by the Free Software Foundation.
*/
&pllss {
/*
* See TRM "2.6.10 Connected outputso DPLLS" and
* "2.6.11 Connected Outputs of DPLLJ". Only clkout is
* connected except for hdmi and usb.
*/
adpll_mpu_ck: adpll@40 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-s-clock";
reg = <0x40 0x40>;
clocks = <&devosc_ck &devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow", "clkinphif";
clock-output-names = "481c5040.adpll.dcoclkldo",
"481c5040.adpll.clkout",
"481c5040.adpll.clkoutx2",
"481c5040.adpll.clkouthif";
};
adpll_dsp_ck: adpll@80 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x80 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c5080.adpll.dcoclkldo",
"481c5080.adpll.clkout",
"481c5080.adpll.clkoutldo";
};
adpll_sgx_ck: adpll@b0 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0xb0 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c50b0.adpll.dcoclkldo",
"481c50b0.adpll.clkout",
"481c50b0.adpll.clkoutldo";
};
adpll_hdvic_ck: adpll@e0 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0xe0 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c50e0.adpll.dcoclkldo",
"481c50e0.adpll.clkout",
"481c50e0.adpll.clkoutldo";
};
adpll_l3_ck: adpll@110 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x110 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c5110.adpll.dcoclkldo",
"481c5110.adpll.clkout",
"481c5110.adpll.clkoutldo";
};
adpll_isp_ck: adpll@140 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x140 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c5140.adpll.dcoclkldo",
"481c5140.adpll.clkout",
"481c5140.adpll.clkoutldo";
};
adpll_dss_ck: adpll@170 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x170 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c5170.adpll.dcoclkldo",
"481c5170.adpll.clkout",
"481c5170.adpll.clkoutldo";
};
adpll_video0_ck: adpll@1a0 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x1a0 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c51a0.adpll.dcoclkldo",
"481c51a0.adpll.clkout",
"481c51a0.adpll.clkoutldo";
};
adpll_video1_ck: adpll@1d0 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x1d0 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c51d0.adpll.dcoclkldo",
"481c51d0.adpll.clkout",
"481c51d0.adpll.clkoutldo";
};
adpll_hdmi_ck: adpll@200 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x200 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c5200.adpll.dcoclkldo",
"481c5200.adpll.clkout",
"481c5200.adpll.clkoutldo";
};
adpll_audio_ck: adpll@230 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x230 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c5230.adpll.dcoclkldo",
"481c5230.adpll.clkout",
"481c5230.adpll.clkoutldo";
};
adpll_usb_ck: adpll@260 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x260 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c5260.adpll.dcoclkldo",
"481c5260.adpll.clkout",
"481c5260.adpll.clkoutldo";
};
adpll_ddr_ck: adpll@290 {
#clock-cells = <1>;
compatible = "ti,dm814-adpll-lj-clock";
reg = <0x290 0x30>;
clocks = <&devosc_ck &devosc_ck>;
clock-names = "clkinp", "clkinpulow";
clock-output-names = "481c5290.adpll.dcoclkldo",
"481c5290.adpll.clkout",
"481c5290.adpll.clkoutldo";
};
};
&pllss_clocks {
timer1_fck: timer1_fck {
#clock-cells = <0>;
......@@ -23,6 +174,24 @@
reg = <0x2e0>;
};
/* CPTS_RFT_CLK in RMII_REFCLK_SRC, usually sourced from auiod */
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&adpll_video0_ck 1
&adpll_video1_ck 1
&adpll_audio_ck 1>;
ti,bit-shift = <1>;
reg = <0x2e8>;
};
/* REVISIT: Set up with a proper mux using RMII_REFCLK_SRC */
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
};
sysclk18_ck: sysclk18_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
......@@ -79,37 +248,6 @@
compatible = "fixed-clock";
clock-frequency = <1000000000>;
};
sysclk4_ck: sysclk4_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <222000000>;
};
sysclk6_ck: sysclk6_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
sysclk10_ck: sysclk10_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
};
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <250000000>;
};
};
&prcm_clocks {
......@@ -138,6 +276,49 @@
clock-div = <78125>;
};
/* L4_HS 220 MHz*/
sysclk4_ck: sysclk4_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&adpll_l3_ck 1>;
ti,clock-mult = <1>;
ti,clock-div = <1>;
};
/* L4_FWCFG */
sysclk5_ck: sysclk5_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&adpll_l3_ck 1>;
ti,clock-mult = <1>;
ti,clock-div = <2>;
};
/* L4_LS 110 MHz */
sysclk6_ck: sysclk6_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&adpll_l3_ck 1>;
ti,clock-mult = <1>;
ti,clock-div = <2>;
};
sysclk8_ck: sysclk8_ck {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&adpll_usb_ck 1>;
ti,clock-mult = <1>;
ti,clock-div = <1>;
};
sysclk10_ck: sysclk10_ck {
compatible = "ti,divider-clock";
reg = <0x324>;
ti,max-div = <7>;
#clock-cells = <0>;
clocks = <&adpll_usb_ck 1>;
};
aud_clkin0_ck: aud_clkin0_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
......
......@@ -6,6 +6,32 @@
#include "dm814x-clocks.dtsi"
/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
&adpll_hdvic_ck {
status = "disabled";
};
&adpll_l3_ck {
status = "disabled";
};
&adpll_dss_ck {
status = "disabled";
};
/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
&sysclk4_ck {
clocks = <&adpll_isp_ck 1>;
};
&sysclk5_ck {
clocks = <&adpll_isp_ck 1>;
};
&sysclk6_ck {
clocks = <&adpll_isp_ck 1>;
};
/*
* Compared to dm814x, dra62x has different shifts and more mux options.
* Please add the extra options for ysclk_14 and 16 if really needed.
......
......@@ -98,12 +98,20 @@
clock-frequency = <32768>;
};
sys_32k_ck: sys_32k_ck {
sys_clk32_crystal_ck: sys_clk32_crystal_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin1>;
clock-mult = <1>;
clock-div = <610>;
};
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
......@@ -2170,4 +2178,12 @@
ti,bit-shift = <22>;
reg = <0x0558>;
};
sys_32k_ck: sys_32k_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
ti,bit-shift = <8>;
reg = <0x6c4>;
};
};
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include "skeleton.dtsi"
......@@ -460,8 +460,6 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
};
spmi_bus: spmi@fc4cf000 {
......@@ -479,16 +477,6 @@
interrupt-controller;
#interrupt-cells = <4>;
};
blsp2_dma: dma-controller@f9944000 {
compatible = "qcom,bam-v1.4.0";
reg = <0xf9944000 0x19000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
};
};
smd {
......
......@@ -661,6 +661,7 @@
};
&pcie_bus_clk {
clock-frequency = <100000000>;
status = "okay";
};
......
......@@ -143,19 +143,11 @@
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif0_pins: serial0 {
renesas,groups = "scif0_data_d";
renesas,function = "scif0";
};
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth";
......@@ -229,11 +221,6 @@
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&ether {
pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-names = "default";
......@@ -414,6 +401,7 @@
};
&pcie_bus_clk {
clock-frequency = <100000000>;
status = "okay";
};
......
......@@ -1083,9 +1083,8 @@
pcie_bus_clk: pcie_bus_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-frequency = <0>;
clock-output-names = "pcie_bus";
status = "disabled";
};
/* External SCIF clock */
......@@ -1094,7 +1093,6 @@
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
status = "disabled";
};
/* External USB clock - can be overridden by the board */
......@@ -1112,7 +1110,6 @@
/* This value must be overridden by the board. */
clock-frequency = <0>;
clock-output-names = "can_clk";
status = "disabled";
};
/* Special CPG clocks */
......